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ASIC Design Implementation of Memory Efficient Infinite Impulse Response

UWB Equalizer

Article in PRZEGLĄD ELEKTROTECHNICZNY · March 2012

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 Muhammad Faisal SIDDIQI1,2 , Muhammad Kamran BHATTI4, Sana SHUJA1, Shaista JABEEN1,
Saeed AHMAD1,2, Adeel IQBAL1,2 , Ghufran SHAFIQ1,2, Ahmad Naseem ALVI2, Azhar YASEEN2,
Abid Ali MINHAS5, Shahzad A. MALIK2, Shahid A. KHAN2, Raja Ali RIAZ1,2,3
Center for Advanced Studies in Telecommunication, COMSATS Institute of Information Technology, Islamabad (1), Department Of
Electrical Engineering, COMSATS Institute of Information Technology, Islamabad (2), School of ECS, University of Southampton (3),
National Institute of Electronics (4), Bahria University (5)

ASIC Design Implementation of Memory Efficient Infinite

Impulse Response UWB Equalizer
Abstract. Channel Equalization plays an important role in reducing distortion and Inter-Symbol Interference (ISI) to improve the quality of
transmission in Ultra-Wide Band (UWB) channel. Many equalization techniques have been proposed in the past but the proposed techniques in this
paper describes Infinite Impulse Response (IIR) equalizer architecture which halves the memory requirement of conventional IIR equalizers. This is
achieved by exploiting the aperiodically repeated clusters of negative-exponentially decaying segments of Channel Impulse Response (CIR) and
hence by providing a single delay- line between the input and output of the equalizer. Further this architecture is realized by implementing on
Application Specific Integrated Circuit (ASIC) using Mentor Graphics IC Design tools. Mathematical modeling gives suitable parameters of the IIR
Filter, followed by Register Transfer Level (RTL) Design using Very High Descriptive Language (VHDL), ASIC synthesis to TSMC 0.35um process
technology, physical modeling using advanced layout techniques. The IIR equalization filter is designed using 8758 Metal Oxide Semi-conductor
(MOS) transistors with core cell area of 0.406mm2.

Streszczenie. W artykule zaproponowano architekturę ekwalizera NOI, która zmniejsza wymagania pamięci przy transmisji szerokopasmowej w
układach ASIC. Zaprezentowano układ w technologii 35 nm z tranzystorami MOS przy powierzchni celki jądra 0.406 mm2. (Projekt
szerokopasmowego ekwalizera NOI w układach ASIC)

Keywords: Quasi-cyclic LDPC codes, Protograph LDPC codes, Low complexity LDPC codes, Vandermonde Matrix.
Słowa kluczowe: układy ASIC – application specific integrated circuits, ekwalizer, filtry szerokopasmowe.

Introduction magnitude. This specific characteristic of UWB CIR results

The distinct clusters of dense multi path components in in a memory-reduction for the receivers IIR equalizer. A
UWB systems results in Channel Impulse Response (CIR) generic z-domain discrete-time transfer function derived for
potentially span over hundreds of transmitted symbols, UWB CIR [3] with L tap-clusters, each tap having
hence imposing excessive memory requirements on the Nakagami-m distribution was given in [1].
equalizers implementation. In [1] a generic discrete time z-
E  2 1   l 1 l z 
L 1
domain transfer function estimation technique was 

proposed, hypothesizing that a memory efficient Infinite

(1) H ( L)
(UWB ) 
T
 m
m

( z) 1 
 T d 1   z 1 
L

Impulse Response (IIR) UWB equalizer implementation m0
 l 1 
may be found. Hence the novel contribution of this letter is
that this memory efficient UWB IIR equalizer is indeed where ξm is a statistically independent positive random
found and the corresponding design is implemented on variable having a Nakagami-m probability density function
ASIC. The proposed equalizer attains exactly the same Bit (PDF) with m=1 for rays within a cluster, Φ(z) is the z-
Error Rate (BER) performance as conventional equalizer, transform of the UWB signaling-pulse of duration T and
despite requiring only half the memory as demonstrated energy E, τl is the cluster arrival time expressed in
against the bench marker designs provided in [1], [2]. This nanoseconds and Td is the sampling duration with Td ≫ τl.
work presents a very efficient design flow for digital IC Introducing
designing by implementing IIR equalization filter which  E
could be utilized as channel equalizer to cancel out
distortion in UWB channel. The specialty of equalization
(2) †  
m 0 T
m
 ( z )
m

filter is the proposed memory efficient architecture which in Eq (1) yields

halves the memory requirement. Fig. 1 shows the basic
 †  1  1z  2z   Lz 
1 2 L
building blocks of the implementation.
Mathematical modeling is performed and verified. Next, (3) H ( L ) ( z )   †   
T d  1  z  z   z
(UWB ) 1 2 L
its behavior is modeled using Hardware Description 
Language (HDL) such as VHDL and Verilog, which is then
synthesized to TSMC 0.35um ASIC technology. The where Ψ† is the Power Spectral Density (PSD) of the
synthesized net list is verified by using a new technique in received UWB signal, which depends on both Φ(z) and on
Mentor Graphics IC Design flow named post synthesis the tap-distribution determined by m. We can assume any
simulation technique. The next step is to generate a particular signaling pulse shape and find the corresponding
Schematic Driven Net list (SDL) from the gate level characteristics from [3]. Therefore, by employing any UWB
representation for layout preparation. Once the layout is signaling pulse shape having a linearly evolving phase shift
completed and verified. Finally, the resulting GDS-II file can corresponds to Eq (2), hence Eq (3) can be approximated
be sent for successful tape out. as:
2 †  1  1z  2z   Lz 
1 2 L

H ((UWB ) ( z) 
Mathematical Modeling and verification L)
(4)  1 2 L 
A. Design Preliminaries
The UWB CIR is constituted by aperiodically repeated
T d  1 z  z   z 
clusters of negative-exponentially decaying segments, As 1/Tdis the sampling frequency, which is twice the
which gives a frequency having a gradually tapering bandwidth of the system and Ψ† s the known PSD of the

PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 3b/2012 223

signaling-pulse, we introduce the product of these two C. Memory Efficient IIR Equalizer Design
constants as: The aim of this design is to combine the two delay-lines
of Fig. 2 into a single one, as Eq (8) cannot be implemented
by a single delay-line. But this design requires two recursive
difference equations for interpreting the input-output
relationship of the equalizer in order to rely on a single
delay-line, which halves the IIR equalizers memory
requirement. These equations should be causal so that the
new memory efficient equalizer design remains practically
realizable. To achieve this objective, we solve Eq (6) again
for Y(z), which yields:
(2)
 L

: Y ( z ) : V ( z )  ★     z  
★
(9) ( L)
H (UWB ) ( z)
 1 
IIR
where V(z) is given by:
Fig. 1. Design Methodology X ( z)
(10) V ( z) 
1   1 z 
L
2 †
(5)   ★

T d Finally, solving Eq (10) for X(z) and taking the inverse

ztransform of Eq (9) and Eq (10) we arrive at the required
Finally, upon substituting Eq (5) in Eq (4), after a few pair of causal recursive difference equations, which results
algebraic simplifications we arrive at: in the halved-memory IIR UWB equalizer design as:
(6) L
 ★   L ★ z  (11) x[n]   v[n   ]
Y ( z ) 
 1
 0
  1   z 
L
H (UWB ) ( z ) 
( L)
L
X ( z)   1


 
★
  †
  for  1, 2,..., L (12) y[n]  ★v[n]   ★
 v[ n   ]
 1
which is the required transfer function of the UWB IIR
equalizer. The architecture modeling of Eq (11) and Eq (12) is shown
in Fig. 3.
B. Conventional IIR Equalizer Design
This design hinges on the extension of Eq (6) into a
difference equation. Upon solving Eq (6) for Y(z) we obtain:
(7)
(1)
 L
  L

: Y ( z ) 1   z    X ( z )  ★    z  
★
H ((UWB
L)
) ( z)
  1    1 
IIR
Finally, taking the inverse z-transform of Eq (7) gives the
causal recursive difference equation for the conventional IIR
UWB equalizer design in the form of:
L L
(8) y[n]  ★ x[n]   y[n  v]  ★
 x[ n  w]
v 1  1
The architecture modeling Eq (7) is shown in Fig. 2. Fig. 3. Memory-Efficient UWB IIR equalizer with L ray-clusters and
Nakagami-m distribution.

HDL Modeling and verification

The mathematical model for memory efficient IIR
Equalization filter is constructed in previous design step, it
is necessary to come up with a circuit model to realize the
design. This realization is done on ASIC design, the
behavior of systems is typically modeled in HDL using
VHDL or Verilog for flexibility, portability and rapid
prototyping [4]. Fig. 5 shows the simulation results obtained
from this behavioral VHDL model using Mentor Graphics
and ModelSim. By contrasting Eq (8), Eq (11) and Eq (12)
as well as Fig. 2 and Fig. 3, it becomes evident that the
proposed design requires a single delay-line, which halves
the memory requirement of the conventional design. Both
Fig. 2. Conventional UWB IIR equalizer for L ray-clusters and equalizer designs are characterized in the context of UWB
Nakagami-m distribution. prolate spheroidal wave signalling functions (PSWF) having

224 PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 3b/2012

duration of 0.15 ns, which were transmitted every 120 ns as A. Front End Design
in [1], [2]. We obtain exactly the same BER performance as This is the top level of abstraction which consists of
in [1], [2] as evidenced in Fig. 4 for both designs, despite different steps starting from the synthesis of behavioral
halving the memory requirements. VHDL description to technology specific gate level
architecture and then the mapping of this gate level
architecture to transistor level schematic Fig. 6 shows the
front end design flow. The technology used for the
implementation is TSMC 0.35um.

Fig. 4. BER performance of the UWB equalizer designs of Figs 2

and 3, both of which are capable of approaching the analytical
solution with a degree n = 3 in Eq(19) of [2] and corresponding to
(i;j) memory registers, where i is used in memory-efficient design
and j is in the conventional design.

Fig. 6. Front End Design Flow Chart

Fig. 5. BER Behavioral VHDL Simulation Results

ASIC Design Flow

Integrated circuits are much smaller both transistors and
Fig. 7. Post Synthesis Simulation Results
wires are shrunk to micrometer sizes, compared to the
millimeter and centimeter scales of discrete components.
Synthesis
Small size leads to advantages in speed and power
Synthesizing VHDL takes the design to next level of
consumption, since smaller components have smaller
abstraction that is structural description. Leonardo
parasitic resistances, capacitances, and inductances. The
Spectrum software was used for this purpose. Synthesized
high speed of circuit onchip is due to their small size, lower
netlist describes the constituent electronic components and
power consumption is largely due to the small size of
necessary circuit details that combine to define a block of a
circuits on the chip smaller parasitic capacitances and
system. The netlist includes primitives like logic gates and
resistances require less power to drive them [5].
large pre designed blocks called standard cells. Extensive
The digital design flow involves several processes that
simulations are performed to verify for the desired
together take the design from the specifications level to a
operation. Successful simulations ensure building of an
verified GDS-II layout. The digital flow start point is a set of
electronic circuit to match the behavioral description. At this
detailed block level specifications describing the
stage clock frequency is an important factor to be taken
functionality required on a micro-architecture level.
care of for high-performance digital integrated circuits.
Specifications for different blocks are determined in the
Gauging the ability of a circuit to operate at the specified
preceding design partitioning phase. Different architectures
speed requires ability to measure, during the design
may be examined when designing and implementing digital
process, its delay at numerous steps. Clock frequency
part blocks where specifications are always kept forefront,
specifies the clock periods for all clocks in your design.
with some emphasis on the capacity of the architecture to
Clock frequency used for the implementation of IIR
meet the required timing, area as well as power constraints
equalizer is 50MHz and the design is optimized to cater for
[6]. Digital ASIC Design flow can be partitioned into Front
delays.
end design known as schematic design and Back end
design known as physical design [7]. Verification

PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 3b/2012 225

 Verification of gate level netlist is performed by there is no violation of any design rules, power and signal
simulating it using ModelSim. The results at this stage are integrity.
matched with the previous results being observed at In other words, a complete layout is designed and
behavioral level. This verification is termed as post- verified. This is how the IC would look, if we took a closer
synthesis simulation as shown in Fig. 7. After verification look at it through the microscope. Fig. 9 shows the core cell
the schematic mapping is being performed. layout design of a memory efficient IIR equalization filter for
UWB. After the routing phase, Design rule checks and
layout vs schematic checks are performed to verify layout
block. Table 2 describes the detailed specification of Back
End Design.

Fig. 9. Core Cell Layout

Fig. 8. Back End Design Flow Chart

Table 1. Front End Design Specifications

Clock Number of Power Slack
Frequency Gates Dissipation
50MHz 1673 1.8097mW 6.65ns

Schematic Mapping
Schematics mapping can be considered to be at a lower
level of abstraction since the synthesized gate level design
is mapped to transistor level schematic using Design
Architect software. Just as in the previous stage, various
electronic components like logic gates and standard cells
are placed and interconnected to make the circuit blocks.
Now the functionality of these logic gates and standard cells
are controlled by MOS transistors. The primary goal of
schematic mapping is to create schematic driven layout
(SDL) viewpoints, to be used for backend designing. The
overall behavior of equalization filter is described in Table. 1
B. Back End Design
Fig. 8 shows the backend design flow it describes the
lowest level of abstraction possible in circuit description Fig. 10. Final Chip Design
using IC Station tool. This process include steps like Table 2. Back End Design Specifications
partitioning, floor planning, placements, routing, Design NMOS NMOS Total No. of Core Area
Rule Check (DRC), Layout Versus Schematic (LVS), and Transistors Transistors Transistors Cell
generation of GDS-II which is submitted to foundry for chip
4379 4379 8758 0.406mm2
fabrication. For this purpose Calibre DRC and Calibre LVS
tool is used. Before sending the GDS-II for mask
preparation the design should be verified to confirm that

226 PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 3b/2012

LVS end design was completed and verified successfully using
A Layout vs. Schematic (LVS) check is performed. This TSMC 0.35um technology up to GDS II format which could
ensures that the layout is in conformance with the be fabricated and used as an independent chip to equalize
schematic. The design process moves back and forth the distortion effects in UWB channel.
between Layout, LVS and DRC.
Acknowledgements
DRC The authors would like to thank the staff of Multi-
This stage is often dependent on the final process Processor Lab at University of Southampton for their
technology that is used to manufacture the Chip. The support and patience in exhaustive simulations, running for
design rule check ensures that the rules laid down by the long durations. Also acknowlwdge the hardwork done by
fabrication process technology are not violated. A good project director IC design centre National Institute of
example would be, some processes need transistors, wires Electronics to promote this field in Pakistan.
and polysilicon to be of a certain minimum width. The layout
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Authors: prof. Ph.D. Raja A. Riaz, B. Sc. Saeed Ahmad, B.Sc. M.
Conclusion Faisal Siddiqi, B.Sc.Ghufran Shafiq, B.Sc. Adeel Iqbal , Center for
We have presented a memory efficient IIR equalizer Advanced Studies in Telecommunication Studies (CAST),
which halves the memory requirement of the conventional COMSATS Institute of Information Technology, Park Road, Chak
design. Both equalizer designs are characterized in context Shehzad Campus, 44000, Islamabad, Pakistan,
of UWB prolate spheroidal wave signaling function (PSWF) email:[email protected],http://cast.org.pk,email:raj
[email protected],http://ciitisb.edu.pk,email:faisal_siddiqui@co
having a duration of 0.15ns, which were transmitted every
msats.edu.pk, B.Sc. Sana Shuja, B.Sc. Shaista Jabeen, M. Sc.
120 ns as in [1], [2]. We obtain exactly the same BER Naseem Alvi, M.Sc. Azhar Yaseen, COMSATS Institute of
performance as in [1], [2]. The memory efficient IIR Information Technology, Park Road, Chak Shehzad Campus,
equalizer was modeled in HDL for implementing the design 44000, Islamabad, Pakistan, M. Sc. M. Kamran Bhatti,National
on ASIC using a Mentor Graphics IC design flow which Institute of Electronics (NIE), Pakistan, http://nie.gov.pk.
provides an extra level of verification using post synthesis
simulation technique at gate level. The front end and back

PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 3b/2012 227

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