2023 The 8th International Conference on Integrated Circuits and Microsystems

Architecture Analysis and Simulink Modeling of a High Resolution Zoom ADC

Shuaiyang Zhou1,2, Nan Liu2, Peng Ding2, Zhizhen Yin2,Suzhen Cheng1,2, Zhanqiang Ru2*, Helun Song2*
1
School of Nano-Tech and Nano-Bionics, University of Science and Technology of China
2023 8th International Conference on Integrated Circuits and Microsystems (ICICM) | 979-8-3503-1851-7/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICICM59499.2023.10365867

Hefei,China
2
Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences
Suzhou,China
E-mail:[email protected]

Abstract — This paper analyzes the principle of the the requirements of sensor application [1]-[4].
architecture and key circuit modules of a high resolution The coarse SAR ADC performs high N bits quantization on
discrete Zoom Analog-to-Digital Converter (Zoom ADC) the input signal, and its high-order digital output greatly
used in multicolor detectors, and uses Matlab Simulink to reduces the swing of the input signal of the loop filter by
model in the behavior level and verifies its function and dynamically adjusting the reference voltage of the fine SDM,
performance. Zoom ADC uses a front-end coarse 5-bit thus enabling the use of transconductance amplifiers(OTA)
Asynchronous Successive Approximation Register Analog- based on inverters, greatly reducing the power consumption of
to-Digital Converter (SAR ADC) to dynamically adjust the OTA, and thus achieving high energy efficiency [1]-[4],[6]-[8].
reference voltage of a back-end fine third order 2-bit It also improves the system's robustness against out-of-band
Sigma-Delta modulator (SDM) to effectively improve the interference [1]-[2]. The final digital output of Zoom ADC can
dynamic range of the system. An additional feedforward be obtained by simply adding the digital outputs of the two-
path combined with a 2-bit quantizer minimizes stage converter .
quantization noise in SAR ADC, and the Data Weighted
Average (DWA) algorithm performs first order noise By analyzing the structure of Zoom ADC and the principle
shaping for capacitor mismatches in 5-bit fine Capacitance and function of its key circuit modules, this paper uses
Digital-to-Analog Converter (CDAC),and introduces the MATLAB Simulink to conduct behavior-level modeling, and
over-ranging factor M, which not only relaxes the fully verifies its function and performance. The rest is
quantization error of SAR ADC, but also effectively organized as follows: Section 2 details the architecture of the
prevents SDM overload. Simulink modeling results show Zoom ADC and the principle of the key circuit modules.
that the signal to noise distortion ratio (SNDR) of the Section 3 introduces the design of ideal model and nonideal
output signal is greater than 117 dB and the effective bit model in MATLAB Simulink in detail. In the fourth part, the
(ENOB) is greater than 19 bits when the input signal function and performance of key circuit modules and system
frequency is within the bandwidth of 10 KHz, the models are compared and verified. In the fifth part, the work of
oversampling rate is 128, and the signal amplitude is -0.9 this paper is summarized.
dBFS.
Ⅱ. INTRODUCTION TO ZOOM ADC ARCHITECTURE AND KEY
CIRCUIT PRINCIPLES
Keywords — Zoom ADC, SAR ADC, Sigma-Delta
Modulator, Over-ranging factor, Feedforward path, DWA The simplified Zoom ADC architecture is shown in Figure
1, which includes asynchronous SAR ADC, SDM, and
Combine circuits, where asynchronous SAR ADC and SDM
I. INTRODUCTION work synchronously [1].
Sensor application systems usually require Analog-to- The input signal ��� is first converted to high N-bit by the
Digital Converters (ADC) with high dynamic range (DR), high coarse SAR ADC, and then combined with the output of the
energy efficiency, and low area [1]-[2]. Although Successive SDM quantizer to dynamically adjust the reference voltage of
Approximation Register Analog-to-Digital (SAR ADC) has the SDM. The reference voltage formulas of SDM is shown in (1)
characteristics of high energy efficiency, its resolution is and (2)
usually limited to 12-14bits, Sigma-Delta Analog-to-Digital
(Sigma-Delta ADC) has the characteristics of high resolution, VREF   ( k  1) * VLSB (1)
but its performance in energy efficiency is poor [2]. By
combining highly energy-efficient SAR ADC with high-
VREF   k * VLSB (2)
resolution Sigma-Delta ADC, Zoom ADC perfectly meets all where k is the digital output of the coarse SAR ADC and ����
is the least significant bit of the fine CDAC in Figure 1. The
Supported by Jiangsu Province "Six Talent Peak" high-level Talent dynamically adjusted reference voltage ����± is subtracted
Project (XYDXX-211). from the input signal ��� , and finally sent to SDM for

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processing to get the rest of the low bit digital outputs. The low the device itself, as shown in Figure 2(b), result in the
bit digital output and high bit digital output can be obtained by quantization output of SAR ADC being in k=d-1, at which
simply adding the Combine circuit to get the final digital time the corresponding positive reference voltage ����+ is
output [1]. smaller than the input signal ��� , as shown in equation (4)
VREF   d * VLSB  Vin (4)
this will cause the input signal ��� to fall outside the input
range of the loop filter, ultimately leading to SDM overload.
To solve this problem, an over-range factor M is introduced
to broaden the input range of SDM. As shown in Figure 2(c), a
schematic diagram of M=1 is given based on the nonideal
factor conditions in Figure 2(b). At this time, the reference
voltage of the fine SDM is shown in formulas (5) and (6):
VREF   ( k  M  1) * VLSB (5)
Fig. 1. Zoom ADC schematic diagram VREF   ( k  1) * VLSB (6)
A. Over-ranging factor It can be seen that the input range of the loop filter has been
expanded to three times ���� , which leaves a larger error
In order to ensure that the input reference voltage ����± of space for coarse errors,thus greatly relaxing the accuracy
the modulator stably straddles the input signal ��� and the requirements of SAR ADC and improving the robustness of
modulator remains in its stable operating region, an over-range the system. The larger the M value, the higher the error
factor M is introduced, and its working principle is shown in tolerance of SAR ADC. The larger the input range and better
Figure 2. the stability of SDM, but at the same time, the power
consumption and quantization noise of SDM are increased. In
The quantization process of SAR ADC and the dynamic addition, the linearity of SDM will also become worse.
adjustment relationship of fine CDAC output reference voltage Therefore, in the paper, M=1 is chosen as a trade-off [2]-[4].
����± are shown in Figure 2(a). The input signal ��� is
quantized by SAR ADC to obtain a digital output k=d, and the B. Feedforward path
digital output is then processed by fine CDAC to obtain a
reference voltage ����+ ,����− , resulting in As shown in Figure 1, based on the final architecture
parameters selected in the paper, there are formulas (7)-(9)
VREF   Vin  VREF  (3)
this ensures that the input signal ��� is within the input range of Yout  V in  Q SA R ( ST F  1)  Q 2 _ b * N T F (7)
the loop filter. However, due to the presence of very close 1 (8)
situations, such as ��� ≈����+ or ��� ≈����− , this may lead to NTF 
1  K * H 3 (z)
SDM overload(especially in the case of higher order
1 (9)
modulators); Even more, the mismatch and noise inherent in STF  1    NTF
1  K * H 3 (z)

Fig. 2. (a). Quantization operation of SAR ADC and reference voltage selection of fine DAC (b). Adding mismatch and noise to SAR ADC based on (a)
(c).Adding over range factor based on (b)

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where ���� is the quantization noise of SAR ADC, STF is the Assuming the starting position of the pointer in the DWA
signal transfer function of SDM, �2_� is the quantization noise algorithm is 1, when the input number code of DAC is 3, basic
of SDM, NTF is the noise transfer function of SDM, and K is units 1, 2, and 3 are selected. When the input code is 6, basic
the gain of the quantizer in SDM. It can be seen that in units 4, 5, 6, 7, 8, and 1 are selected. When the input code is 4,
addition to quantization noise �2_� shaped by third-order noise, basic units 2, 3, 4, and 5 are selected. In the long run, the
there is also some out of band noise leakage of ���� at the probability of each basic unit being selected within the DAC is
output end [1]-[2]. the same. From a mathematical point of view, the DWA
algorithm has a first-order noise shaping effect on mismatch
Drawing on the idea of feedforward path of the Sigma- noise, as shown in formula (12)
Delta ADC, a feedforward path is added to the Zoom ADC to
p ( z ) 1
eliminate the noise leakage of ���� to the greatest extent . The  Ci
schematic diagram is shown in Figure 3. At this point, there E ( z )  (1  z 1 ) i 0 E (C i )
(12)
are formulas (10) and (11)
where �(�) is the mismatch noise, �(�� ) is the average value
GK  KH of all capacitor components, and ∆�� is the difference between
STF  1  1 (10)
1  KH the i-th capacitor �� and �(�� ) . From the formula. It can be
GK  1 (11) seen that the mismatch noise is processed through first-order
where G is the gain of the feedforward path ���� , and K is the noise shaping, and the mismatch noise within the band is
greatly attenuated, thereby optimizing the SNDR.
gain of the two bit quantizer. It can be seen that the addition of
feedforward paths can make ��� -1=0, thereby completely In summary, the final Zoom ADC architecture adopted in
the paper is shown in Figure 5.
eliminating noise leakage and improving the SNDR of the
system.

Fig. 5. Schematic Architecture of Zoom ADC

Ⅲ. MATLAB SIMULINK MODEL DESIGN

Fig. 3. Zoom ADC architecture with feedforward path
A. Ideal Model Design
C. DWA algorithm The noise transfer function of Zoom ADC is designed by
using the MATLAB SDToolbox. The initial parameters of the
Since the SNDR of Zoom ADC is prone to be limited by
noise transfer function are calculated according to the order L
the reference voltage of fine CDAC, and the mismatch of
of loop filter, the oversampling rate (OSR), the quantization
capacitors in CDAC seriously affects the reference voltage, the
levels nLev, the maximum NTF gain H0_inf and other
data weighted average (DWA) algorithm is introduced to deal
parameters. In order to better implement the model by the
with the mismatch of capacitors, and its working principle is
circuit, directional optimization is carried out on the initial
shown in Figure 4.
coefficients, and root trajectory analysis is performed on the
optimized NTF to determine the stability and stability
conditions of the system [5].
The ideal model is modeled based on the optimized NTF,
and the model is shown in Figure 6,including 5-bit
asynchronous SAR ADC, feedforward path, Combine circuit,
5-bit fine CDAC, third-order feedforward loop filter, active
adder, and two-bit quantizer. The modeling result shows that
under the conditions of an input signal frequency within a
bandwidth of 10kHz, an amplitude of -0.9dBFS, and an OSR
of 128, the SNDR of the output signal can reach over 130dB.
Fig. 4. Schematic diagram of DWA algorithm

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 Fig. 6. Zoom ADC Ideal Model

Fig. 7. Zoom ADC Nonideal Model

The modeling results of ideal and nonideal models are

B. Nonideal model design shown in Figure 8.
Considering the influence of various nonideal factors on
the stability and accuracy of the system,which mainly include
sampling clock jitter noise, switch nonlinearity, switch
thermal noise (kT/C noise), limited gain, limited bandwidth,
limited voltage swing rate and input noise of operational
amplifiers, and mismatch of CDAC capacitors, all nonideal
factors should be taken into account when modeling and its
nonideal model is shown in Figure 7. The modeling results
show that the SNDR of the output signal can reach above
117dB when the input signal frequency is within the
bandwidth of 10kHz, the amplitude is -0.9 dBFS, and the OSR
is 128.
Fig. 8. Power Spectrum of Ideal and Nonideal Models

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 It can be seen that under the consideration of various C. Functional verification of DWA algorithm
nonideal factors, the noise shaping effect of the power
Figure 11 shows a comparison of the output signal power
spectrum of the output signal of the nonideal model is
spectrum of the model with and without the DWA algorithm.
significantly worse in the near band and wide frequency range
It can be seen from the data in the figure that the overall noise
compared to the power spectrum of the ideal model output
base of the output power spectrum of the model with the
signal, and the SNDR is also reduced by about 15dB,
DWA algorithm is lowered, and the SNDR of the system is
indicating that the design of the nonideal model is very close
improved by about 37dB, which is related to the mismatch
to the circuit level design.
rate added in the model, which is 0.1% in the model. It can be
Ⅳ. ZOOM ADC MODEL VERIFICATION seen that the DWA algorithm can effectively perform first-
order noise shaping on the mismatch noise of CDAC
A. Overrange factor M Functional verification
capacitors, thereby elevating the SNDR of the system.
Figure 9 shows the waveform of ����+ , ����− , ���� , and
��� after introducing the over-range factor M (M=1) based on
two bit quantization. From the figure, it can be seen that ���
stably straddles between ����± , which is due to the addition
of the over-range factor; ���� tightly surrounds ��� , and the
width of ���� is 1LSB, ensuring low swing of the input signal
of the loop filter,which thanks to the use of a two-bit quantizer.

Fig. 11. Output power spectrum with DWA turned on or off

@(Vin = -0.9dBFS OSR=128 G=1/K)
Table I summarizes the performance of this Zoom adc's
non-ideal model and compares it to the performance of several
other state-of-the-art zoom adc chips.By comparing the data in
the table, we can see that the performance of the Zoom adc has
Fig. 9. Relationship between CDAC output and Vin certain advantages, and there is enough margin for circuit level
@ (2-bit quantization, M=1) design.

B. Functional verification of feedforward path TABLE I. PERFORANCE COMPARISON

Figure 10 shows the power spectrum of the output signal

of the nonideal model when opening and closing the
feedforward path. As can be seen from the figure, the power
spectrum of the output signal whose feedforward path is
turned on is compared with that whose feedforward path is
turned off，the noise floor at high frequencies of the former is
reduced to about -150dB, and the SNDR of the system is
increased by about 9dB, which is consistent with the principle V. CONCLUSION
analysis of the feedforward path in section 1.2.
This paper analyzes the Zoom ADC and the principle of
the over-range factor M, the DWA algorithm and the
feedforward path. Then, based on the consideration of various
nonideal factors in circuit design, MATLAB Simulink is used
to design the system model. Finally, the function and
performance of each module and system are compared and
verified. The modeling results based on the final Zoom ADC
architecture show that the SNDR and ENOB of the output
signal can reach 117.5dB and 19.1bits when the frequency of
the input signal is in the full bandwidth range, the amplitude is
-0.9dBFS and the OSR is 128, meeting the performance
requirements of the multicolor detector for ADC.

Fig. 10. Output power Spectrum with Feedforward Path turned on

or off @(Vin = -0.9dBFS OSR=128)

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