EXPERIMENT – 9

Transistor Level Circuit Analysis on Cadence EDA Tool

OBJECTIVES:
I To obtain schematic of CMOS Inverter at 180nm GPDK.
II. To do DC analysis to obtain transfer characteristic and obtain midpoint voltage for
different size of NMOS and PMOS Transistor
III To do Transient analysis and obtain fmax for different size of NMOS and PMOS Transistor.

THEORY:
The DC characteristics of the CMOS inverter shown in fig. 8.1 are portrayed in the voltage
transfer characteristic(VTC), which is a plot of Vout as a function of Vin as shown in figure 8.2 .
The midpoint voltage Vm is the point where the VTC intersects the unity gain line that is defined
by Vout= Vin=Vm. From inverter analysis, we obtain the equation for Vm is

VM =
This equation shows that VM can be set by adjusting the ratio β n/βp, and Vtn = Vtp, then VM =
VDD/2. Increasing this ratio decrease the inverter switching voltage. If the nFET and pFET are
of equal size, then βn > βp (as kn’>kp’), and VM< VDD/2.
Note: The mobility of holes in p-channels is about half that of electrons in n-channels, u p = un /
2, which implies that we must adjust the width-length ratios to compensate:
kn’= kp’-- > (W/L)p = 2(W/L)n

Fig.8.1 CMOS Inverter Fig.8.2 Inverter Characteristic depends on βn/ βp

n = Rn Cout = P = Rp Cout =

If kn’> kp’, equal size transistors will give tLH > tLH. To obtain symmetrical switching, the
pFET must have an aspect ratio of (W/L) p = kn’> kp’ (W/L)n. This illustrates that which the ratio
of β values sets the DC switching voltage VM, the individual choices for βn and βp determine
the transient switching times. In general, fast switching requires large transistors, illustrating
the speed vs. area trade-off in CMOS design. The propagation delay time exhibits the same
dependence.
 Fig. 8.3 Switch Model of an inverter Fig. 8.4 Transient Characteristics of an Inverter

PROCEDURE:

1. Draw a schmetic for CMOS Inverter on Virtuoso environment as per steps listed in APPENDIX-B
2. Measure midpoint voltage Vm for a given width(W) of nFET and pFET.
3. Now change the width of nFET and pFET and measure Vm.
4. Repeat same task for other values of widths and measure Vm.
5. Repeat above step 2 and 3 to measure rise time and fall time for given input square wave.
6. Plot Vout versus Vin for different βn / βp .
7. Plot Vout Versus time t for different values of βn and βp.
8. Derive your conclusion.

OBSERVATION:
A. Observe the change of Vm with respect to change in size of nFET and pFET.

Width of NMOS: Width of PMOS: Midpoint Voltage:

WN WP VM
400nm 400nm
400nm 800nm
800nm 400nm

B. Observe the changes of rise time and fall time with respect to change in size of nFET and pFET.

Width of NMOS: Width of PMOS: Rise Time Fall Time Maximum Frequency
WN WP tr tf fM
400nm 400nm
400nm 800nm
800nm 400nm

CONCLUSION:

EXERCISE: Obtain switching characteristics of nFET Pass transistor and show that rr = 18
Rn Cout and rf = 2.84 Rn Cout
 APPENDIX-B
Transistor level Simulation on Cadence EDA Tool
Schematic capture and Circuit simulation of CMOS inverter at 180nm CMOS
technology using Cadence Virtuoso with GPDK180 library

Cadence File Organization

To start a design in Cadence, you must first create a library where you can store
your design cells. Every Library is associated with a technology file and it is the
technology file that supplies the color maps, layer maps, design rules, and
extraction parameters required to view, design,simulate and fabricate your
circuit.Cadence stores its files in libraries, cells, and cellviews.
A library (which actually appears as a directory in UNIX) contains cells
(subdirectories), which in turn contain views. Each library contains a catalog of all
cells, viewed along with the actual UNIX paths to the data files. Each cell in a
library uses the same mask layers, colors, design rules, symbolic devices, and
parameter values (i.e. the information contained in the technology file). A cell is
the basic design object. It forms an individual building block of a chip or system.
It is a logic, rather than a physical, design object. Each cell has one or more views,
which are files that store specific data for each cell. A cellview is the virtual data
file created to store information in Cadence. A cell may have many cellviews,
signifying different ways to represent the same data represented by the cell (for
example, a layout, schematic, etc).
Example Organization:
Library: logic_gates
Cell: inv
View: schematic
View: symbol
Cell: nand2
View: schematic
View: symbol
View: layout
View: extracted
Library: ripple_carry_adder
Cell: 1bit_adder
View: schematic
Cell: 2bit_adder
View: schematic

Schematic Capture:

In order to launch Cadence Virtuoso for schematic design follow below mentioned
steps.
Step 1.Create your own directory using file explorer. Open terminal after pressing
right click from same directory.
Step 2.Open terminal and type csh. $csh is command to open Cshell in OS.
Step 3. Configure your system properly using source command
$source /home/install/cshrc
This is particularly useful for configuration files or scripts that set environment
variables, define functions, or perform other shell-related tasks.

Step 4.Type virtuoso & command on terminal to open Cadence Virtuoso

environment.
Step 5. Create your working environment ‐ Design Library
After starting cadence, the first thing to do is create a new library. From the main
Virtuoso window,select Tools > Library Manager ... This will open the Library
Manager (Figure 1) from which we can browse the existing libraries. From the
Library Manager window go to File > New > Library .

Step 6. At this point you will be asked to choose a name for our library;
When asked which Technology File you would like to use for the library,
check ‘Attach to an existing technology library’ , confirm and select
gpdk180 from the Technology Library list.
We will use this library for saving all the cells used in this tutorial. At this point we
are ready to design our first schematic.

Step 7. Now select File => New => Cellview. Use the Create New File window
that pops up to
create the schematic view for an inverter cell.
Select your library from drop-down list. Enter the Cell Name “inv”.
Click on Type drop-down list and select Schematic. This is where you choose
which Cadence tool you want to use and the appropriate View Name for each tool
will be filled in
automatically. Here we will be creating the schematic view.

Click the OK button. The Virtuoso schematic editing tool will open with an empty
Schematic Editing window as shown below.
Step 8. In the Schematic Editing window Select Create => Instance to activate
the Create Instance
tool for adding components (transistors, sources, etc.) to your schematic.Click
Browse to the cell you want to add to the schematic (select “symbol” as view).
In this tutorial we need a NMOS and a PMOS, they are both in the gpdk180
library. Use “nmos” for NMOS and “pmos” for PMOS.
The instance property window should pop out. Fill in the necessary information for
the instance. Here we need to fill in the “Width” and “Length”.
Place the instance by clicking on the schematic drawing window. You can place
the
same instance as many times as you want by clicking multiple times on the
drawing
window, press ESC to leave the add-instance mode.
Step 9. Place pins to inputs and outputs nodes.
Select Create -> Pin for placing pins in the schematic.
Enter the pin name and the direction. In this tutorial we need an input pin and an
output pin.

Step 10 Add wire using create menu.

Click on Create->Wire (narrow) for placing wire in the schematic.
First a single click to start wiring, if this wire ends up at a node of an instance or
any part of a wire, a single click to end wiring, otherwise double click to end
wiring. Press ESC to leave wiring mode.

Step 11. Check for errors in the schematic.

The schematic view of the inverter is shown below. Before going any further we
need to check the schematic, fix any errors or warning if there are any, and save
it.
click Check -> Current Cellview for error checking.
Warnings and errors will be shown as below.

If errors exist the error section will blink in the Schematic Editing window.
Step 12. In the Schematic Editing window, select Create => Cellview => From
Cellview.
In the Cellview From Cellview window that pops up, you should notice source
(From View Name) set to schematic and the destination (To View Name) set to
symbol, which is linked to
the Composer-Symbol tool. You should not have to modify this window.

Click on OK in the Cellview From Cellview window.

A Symbol Generation Options window will popup. Change or modify the pins as
shown as below.

The Symbol Editing window will pop up showing the default symbol, a rectangle
with red
square dots for input and out pins. You can keep this symbol, but it would be
helpful if you
modified it to a more meaningful symbol (such as a triangle for an inverter).
Explore the
options on this window and the tips below to define your symbol graphic.

When the symbol is complete, save it. In the Symbol Editing window select File
=> Save or
click on the Save icon at the top of the toolbar.
In the Symbol Editing window, select File => Close to close the symbol.
Symbol can be used for simulation or drawing layout.
Step 13. Simulation
Create a new schematic and add your symbol for simulation.

Place other components like Vdc,Ground from analogLib as shown as below.

Step 14. Connect the all the components of the circuit using wires. we can use a
voltage pulse generator as the input. It is “vpulse” in analogLib. Place it to the
schematic and connect it to the input.In this tutorial we also need a capacitor at
the output. Use “cap” in the analogLib with 10fF as its capacitance. Place it to
the schematic and connect it to the output.

Step 15. In the Schematic Editing window select Launch => ADE L, and the
Virtuoso Analog Design Environment window will open.
In Virtuoso Analog Design Environment window, select Outputs => to be
plotted => Select
on Schematic. This will activate the Schematic Window allowing you to pick
which signals
(nets/wires) you would like to have plotted during the simulation.
• In the Schematic Window click on the wire that is the input to your inverter and
also click on
the output wire. This will complete the simulation setup.
In Virtuoso Analog Design Environment window, select Analyses => Choose.
• In the window that pops up, select dc to choose a DC analysis.
• Choose Save DC Operating Point and press OK.
In the Virtuoso Analog Design Environment window select Simulation =>
Netlist and Run.
After a successful simulation, an output signal plot will pop up showing the
voltage transfer
curve. If the plot does not look like you would expect, check your steps and repeat
until the
correct output is obtained.
Step 16 In the window that pops up, select tran to choose a transient analysis.
• Enter the time limits for simulation: Set the Stop Time to “100n”.
• Choose Enabled at the bottom of the screen and press OK