Coa Chapter 4
Coa Chapter 4
MEMORY ORGANIZATION
5.1 MEMORY HIERARCHY
The hierarchical arrangement of storage in current computer architectures is called the memory
hierarchy. The memory unit is an essential component in any digital computer since it is needed for
storing programs and data.
The memory unit that communicates directly with the CPU is called the Main Memory (or
Primary memory).
Devices that provide backup storage are called auxiliary Memory (or Secondary).
Only programs and data currently needed by the processor reside in Main memory. All other
information is stored in Auxiliary memory and transferred to main memory when needed.
The Memory hierarchy system consists of all storage devices employed in a computer system from the
slow but high capacity auxiliary
iliary memory to a relatively faster main memory, to an even smaller and
faster cache memory accessible to the high speed processing logic.
When programs not residing in main memory are needed by the CPU, they are brought in from auxiliary
memory. Programs not currently needed in main memory are transferred into auxiliary memory to
provide space for currently used programs and data.
The cache is used for storing segments of programs currently being executed in the CPU and temporary
data frequently needed in the present calculations.
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By making programs and data available at a rapid rate, it is possible to increase the performance rate of
the computer. While the I/O processor manages data transfers between auxiliary memory and main
memory, the cache organization is concerned with the transfer of information between main memory
and CPU. Thus each is involved with a different level in the memory hierarchy is economics.
The static RAM (SRAM) consists essentially of internal flip flops that store the binary information. The
stored information remains valid as long as power is applied to the unit.
The dynamic RAM (DRAM) stores the binary information in the form of electric charges that are applied
to capacitors. The capacitors are provided inside the chip by MOS transistors. The stored charge on the
capacitors tend to discharge with time and the capacitors must be periodically recharged by refreshing
the dynamic memory. Refreshing is done by cycling through the words every few milliseconds to
restore the decaying charge. The dynamic RAM offers reduced power consumption and larger storage
capacity in a single memory chip. The static RAM is easier to use and has shorter read and write cycles.
The ROM portion of main memory is needed for storing an initial program called a Bootstrap Loader.
The bootstrap loader is a program whose function is to start the computer software operating when
power is turned on. The contents of ROM remain unchanged after power is turned off and on again. The
start-up of a computer consists of turning the power on and starting the execution of an initial program.
Thus when power is turned on, the hardware of the computer sets the program counter to the first
address of the bootstrap loader. The bootstrap program loads a portion of the operating system from
disk to main memory and control is then transferred to the operating system, which prepares the
computer for general use.
To demonstrate the chip interconnection, we will show an example of a memory constructed with
128 x 8 RAM chips and 512 x 8 ROM chips.
RAM and ROM chips are available in a variety of sizes. If the memory needed for the computer is larger
than the capacity of one chip, it is necessary to combine a number of chips to form the required
memory size.
A RAM chip is better suited for communication with the CPU if it has one or more control inputs that
select the chip only when needed. Another common feature is a bidirectional data bus that allows the
transfer of data either from memory to CPU during a read operation, or from CPU to memory during a
write operation.
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Chip select 1 CS1
Chip select 2 CS2
Read RD 128x8 8 bit data bus
WR RAM
Write AD7
7-bit address
A bidirectional bus can be constructed with three state buffers. A three state buffer output can be
placed in one of these possible states: a signal equivalent to logic 1, a signal equivalent to logic 0, or a
high impedance state. The logic 1 and 0 are normal digital signals. The high impedance state behaves
like an open circuit, which means that the output does not carry a signal and has no logic significance.
The capacity of the memory is 128 words of 8 bits per word. This requires a 7 bit address and an 8 bit
bidirectional data bus. The read and write inputs specify the memory operation and the two chips select
(CS) control inputs are for enabling the chip only when it is selected by the microprocessor. The
availability of more than one control input to select the chip facilitates the decoding of the address lines
when multiple chips are used in the microcomputer. When the chip is selected, the two binary states in
this line specify the two operations of read or write.
The unit is in operation only when CS1=1 and CS2=0. The bar on top of the second select variable
indicates that this input is enabled when it is equal to 0.
If the chip select inputs are not enabled, or if they are enabled but the read or write inputs are not
enabled, the memory is inhibited and it data bus is in a high impedance state. When CS1=1 and CS2=0,
the memory can be placed in a write or read mode.
When the WR input is enabled, the memory stores a byte from the data bus into a location specified by
the address input lines. When the RD input is enabled, the content of the selected byte is placed into
the data bus. The RD and WR signals control the memory operation as well as the bus buffers associated
with the bidirectional data bus.
A ROM chip is organized externally in a similar manner, however, since a ROM can only read, the data
bus can only be in an output mode.
The two chip select inputs must be CS1=1 and CS2=0 for the unit to operate. Otherwise, the data bus is
in a high impedance state. There is no need for a read or write control because the unit can only read.
Thus when the chip is enabled by the two select inputs, the byte selected by the address lines appears
on the data bus.
The interconnection between memory and processor is then established from knowledge of the size of
memory needed and the type of RAM and ROM chips available.
The addressing of memory can be established by means of a table that specifies the memory address
assigned to each chip. The table, called a memory address map, is a pictorial representation of assigned
address space for each chip in the system.
To demonstrate with a particular example, assume that a computer system needs 512 bytes of RAM and
512 bytes of ROM.
The component column specifies whether a RAM or a ROM chip is used. The hexadecimal address
column assigns a range of hexadecimal equivalent address for each chip.
The address bus lines are listed in the third column. Although there are 16 lines in the address bus, the
table shows only 10 lines because the other 6 are not used in this example and are assumed to be zero.
The small x’s under the address lines designate those lines that must be connected to the address inputs
in each chip.
The RAM chips have 128 bytes and need seven address lines. The ROM chip has 512 bytes and needs 9
address lines. The x’s are always assigned to the low order bus lines: lines 1 through 7 for the RAM and
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lines 1 through 9 for the ROM. It is now necessary to distinguish between four RAM chips by assigning to
each a different address.
For
or this particular example we choose bus lines 8 and 9 to represent four distinct binary combinations.
The table clearly shows that the 9 low order bus lines constitute a memory space for RAM equal to 29 =
512 bytes. The distinction between a RAM and ROM addressaddress is done with another bus line. Here we
choose line 10 for this purpose.
When line 10 is 0, the CPU selects a RAM, and when this line is equal to 1, it select the ROM. The
equivalent hexadecimal address for each chip is obtained from the informatio
information under the address bus
assignment. The address bus lines are subdivided into groups of 4 bits each so that each group can be
represented with a hexadecimal digit.
RAM and ROM chips are connected to a CPU through the data and address buses. The low order lines in
the address bus select the byte within the chips and other lines in the address bus select a particular
chip through its chip select inputs.
Thus, when address lines 8 and 9 are equal to 00, the firs RAM chip is selected. When 01, the second
RAM chip is selected, and so on. The RD and WR outputs from the microprocessor are applied to the
inputs of each RAM chip.
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the surface as it passes through a read head.
Magnetic disks:
A magnetic disk is a circular plate constructed of metal or plastic coated with magnetized material.
Often both sides of the disk are used and several disks may be stacked on one spindle with read/write
heads available on each surface. All disks rotate together at high speed and are not stopped or started
for access purposes. Bits are stored in the magnetized surface in spots along concentric circles called
tracks. The tracks are commonly divided into sections called sectors.
The number of bytes stored in each sector is kept same. All tracks store the same amount of data. This
results higher bit density in inner tracks than that of the outer tracks.
Since the same number of bytes is stored in each sector, the size of the inner sectors decides the storage
capacity for all other sectors on the disk. Ex. Hard disk, floppy disk...
Magnetic Tape:
Magnetic tapes are used for backup memory. A magnetic tapes transport consists of the electrical
mechanical, and electronic components to provide the parts and control mechanism for a magnetic tape
unit.
The tape itself is a strip of plastic coated with a magnetic recording medium. Bits are recorded as
magnetic sports on the tape along several tracks. Read/write heads are mounted one in each track so
that data can be recorded and read as a sequence of characters. Magnetic tape units can be stopped,
started to move forward or in reverse, or can be rewound.
However, they cannot be started or stopped fast enough between individual characters.
Optical disks:
Optical disks are used for backup memory. Information is written to or read from an optical disk using
laser beam. It has very high storing capacity as compared to magnetic floppy disks. It has very long life.
The capacity of optical disks varies from 650 MB to 17 GB. DVDs of 15,25,30 and 50 GB capacity etc., an
optical disk is a direct access device. As its read /write head does not touch the disk surface, there is no
disk wear and problem of head crash. Elaborate error checking codes can be used as there is no
problem of space because of its high storage capacity.
The greatest drawback of an optical disk drive system is its large access time as compared to magnetic
hard disk drive. An optical disk system the drive has to move on a sizable optical assembly across the
disk surface. This results in an increased access time.
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Types of optical disks: CD(compact disk), CD-R(recordable), CD-RW(read/write), DVD(digital versatile
disk), DVD-R, DVD-RW..
The time required to find an item stored in memory can be reduced considerably if stored data can be
identified for access by the content of the data itself rather than by an address. A memory unit accessed
by content is called an associative memory or content address memory (CAM).
This type of memory is accessed simultaneously and in parallel on the basis of data content rather than
by specific address or location. When a word is written in an associative memory, no address is given.
The memory is capable of finding an empty unused location to store the word. When a word is to be
read from an associative memory, the content of the word, or part of the word, is specified. The
memory locates all words which match the specified content and marks them for reading.
The cache is the fastest component in the memory hierarchy and approaches the speed of CPU
component.
When CPU needs to access memory, the cache is examined. If the word is found in the cache, it
is read from the fast memory. If the word addressed by the CPU is not found in the cache, the
main memory is accessed to read the word.
The performance of cache memory is frequently measured in terms of a quantity called hit ratio. When
the CPU refers to memory and finds the word in cache, it is said to produce a hit. Otherwise, it is a miss.
Associative mapping
Direct mapping
Set-associative mapping
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Associative mapping
The fastest and most flexible cache organization uses an associative memory.
The associative memory stores both the address and data of the memory word.
This permits any location in cache to store ant word from main memory.
The address value of 15 bits is shown as a five-digit octal number and its corresponding 12-bit word is
shown as a four-digit octal number.
Direct Mapping
Associative memory is expensive compared to RAM.
In general case, there are 2^k words in cache memory and 2^n words in main memory (in our
case, k=9, n=15)
The n bit memory address is divided into two fields: k-bits for the index and n-k bits for the tag
field
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Figure: Addressing relationships between main and cache memories.
The internal organization of the words in the cache memory is as shown in the above figure. Each
word in cache consists of the data word and its associated tag. When a new word is first brought into
the cache, the tag bits are stored alongside the data bits. When the CPU generates a memor
memory request,
the index field is used for the address to access the cache.
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The tag field of the CPU address is compared with the tag in the word read from the cache. If the
two tags match, there is a hit and the desired data word is in cache. If there is no match, there is a miss
and the required word is read from main memory. It is then the cache together with the new tag,
replacing the previous value.
The disadvantage of direct mapping is that the hit ratio can drop considerably if two or more
words whose addresses have the same index but different tags are accessed repeatedly.
Set-Associative Mapping
The disadvantage of direct mapping is that two words with the same index in their address but
with different tag values cannot reside in cache memory at the same time.
Set-Associative Mapping is an improvement over the direct-mapping in that each word of cache
can store two or more word of memory under the same index address.
each index address refers to two data words and their associated tags
Each tag requires six bits and each data word has 12 bits, so the word length is 2*(6+12) = 36 bits
The words stored at address 01000 and 02000 of main memory are stored in cache memory in index
address 000. Similarly, the words at addresses 02777 and 00777 are stored in cache at index address
777. When the CPU generates a memory request, the index value of the address is used to access the
cache. The tag field of the CPU address is then compared with both tags in the cache to determine if a
match occurs.
The hit ratio will improve as the set size increase because more words with the same index but different
tags can reside in cache. However, an increase in the set size increases the number of bits in words of
cache and requires more complex comparison logic.
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5.6 VIRTUAL MEMORY
For example: if auxiliary memory contains 1024K and main memory contains 32K and page size equals to
1K, then auxiliary memory has 1024 pages and main memory has 32 pages.
In our example, the address field of an instruction code will consist of 20 bits but physical memory
addresses must be specified with only 15 bits. Thus CPU will reference instructions and data with a 20
bit address, but the information
nformation at this address must be taken from physical memory because access to
auxiliary storage for individual words will be prohibitively long.
A table is then needed to map a virtual address of 20 bits to a physical address of 15 bits. The mapping is
a dynamic operation, which means that every address is translated immediately as a word is referenced
by CPU. The mapping table may be stored in a separate memory or in main memory.
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Figure: Memory table for mapping a virtual address
Address mapping using pages: The table implementation of the address mapping is simplified if the
information in the address space and the memory space are each divided into groups of fixed size. The
term page refers to groups of address space of the same size.
Consider a computer with an address space of 8K and a memory space of 4K. If we split each into groups
of 1K words we obtain eight pages and 4 blocks. At any given time, upto four pages of address space
may reside in main memory in any one of the four blocks. The mapping from address space to memory
space is facilitated if each virtual address is considered to be represented by two numbers: a page
number address and a line within the page.
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In the example,, a virtual address has 13 bits. Since each page consists of 210=1024 words, the high order
three bits of a virtual address will specify one of the eight pages and the low order 10 bits give the line
address within the page.
Note that the line address in address space and memory space is the same; the only mapping required is
from a page number to a block number.
The table shows that pages 1,2,5,6 are now available in main memory in blocks 3,0,1,2 respectively. A
presence bit in each location indicates whether the page has been transferred from auxiliary memory
into main memory. A 0 in the presence bit indicates that this page
page is not available in main memory. The
CPU references a word in memory with a virtual address of 13 bits. The 3 high order bits of the virtual
address specify a page number and also an address for the memory page table.
Replacement policies:
A virtual memory system is a combination of hardware and software technique. The memory
management software system handles all the software operations for the efficient utilization of memory
space. It must decide
(1) Which page in main memory ought to be removed to make room for a new page
(2) When a new page is to be transferred from auxiliary memory to main memory, and
(3) Where the page is to be placed in main memory.
When a program starts execution, one or more pages are transferred into main memory and the page
table is set to indicate their position. The program is executed from main memory until it attempts to
reference a page that is still in auxiliary memory. This condition is called page fault. When page fault
occurs, the execution of the present program is suspended until the required, page is brought into main
memory. Since loading a page from auxiliary memory to main memory is basically an I/O operation, the
operating system assigns this task to the I/O processor. In the meantime, control is transferred to the
next program in memory that is waiting to be processed in the CPU. Later, when the memory block has
been assigned and the transfer completed, the original program can resume its operation.
When a page fault occurs in a virtual memory system, it signifies that the page referenced by the CPU is
not in main memory. A new page is then transferred from auxiliary memory to main memory. If main
memory is full, it would be necessary to remove a page from a memory block to make room for the new
page. The policy for choosing pages to remove is determined from the replacement algorithm that is
used. Two of the most common replacement algorithms used are the first-in, first-out (FIFO) and the
least recently used (LRU). The FIFO algorithm selects for replacement the page that has been in memory
the longest time. Each time a page is loaded into memory, its identification number is pushed into a
FIFO stack.
FIFO will be full whenever memory has no more empty blocks. When a new page must be loaded, the
page least recently brought in is removed. The page to be removed is easily determined because its
identification number is at the top of the FIFO stack. The FIFO replacement policy has the advantage of
being easy to implement. It has the disadvantage that under certain circumstances pages are removed
and loaded from memory too frequently.
The LRU policy is more difficult to implement but has been more attractive on the assumption that the
least recently used page is a better candidate for removal than the least recently loaded page as in FIFO.
The LRU algorithm can be implemented by associating a counter with every page that is in main
memory. At fixed intervals of time, the counters associated with all pages presently in memory are
incremented by 1. The least recently used page is the page with the highest count. The counters are
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often called aging registers, as their count indicates their age, that is, how long ago their associated
pages have been referenced.
The fixed page size used in the virtual memory system causes certain difficulties with respect to program
size the logical structure of programs. It is more convenient to divide programs and data into logical
parts called segments.
A segment is a set of logically related instructions or data elements associated with a given name.
Segments may be generated by the programmer or by the operating system. Examples of segments are
a subroutine, an array of data, a table of symbols, or a user’s program. The sharing of common programs
is an integral part of a multiprogramming system. For example, several users wishing to compile their C
programs should be able to share a single copy of the compiler rather than each user having a separate
copy in memory. Other system programs residing in memory are also shared by all users in a
multiprogramming system without having to produce multiple copies.
The function of the memory management unit is to map logical addresses into physical addresses similar
to the virtual memory mapping concept.
Memory Protection:
Memory protection can be assigned to the physical address or the logical address. The protection of
memory through the physical address can be done by assigning to each block in memory a number of
protection bits that indicate the type of access allowed to its corresponding block. Every time a page is
moved from one block to another it would be necessary to update the block protection bits.
A much better place to apply protection is in logical address space rather than the physical address
space. This can be done by including protection information within the segment table or segment
register of the memory management hardware.
The protection information is set into the descriptor by the master control program of the operating
system. Some of the access rights of interest that are used for protecting the programs residing in
memory are:
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1. Full read and write privileges
2. Read Only (write protection)
3. Execute only (program protection)
4. System only (operating system protection)
Full read and write privileges are given to a program when it is executing its own instructions. Write
protection is useful for sharing system programs such as utility programs and other library routines.
These system programs are stored in an area of memory where they can be shared by many users. They
can be read by all programs, but no writing is allowed.
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