Design and Simulation of UART Serial

Communication Module Based on VHDL

FANG Yi-yuan CHEN Xue-jun

College of Electrical and Electronic Engineering
Shanghai University of Engineering Science
Shanghai, China
[email protected]

Abstract—UART (Universal Asynchronous Receiver asynchronous transmissions, a bit called the "Start Bit" is
Transmitter) is a kind of serial communication protocol; mostly added to the beginning of each word that is to be transmitted.
used for short-distance, low speed, low-cost data exchange The Start Bit is used to alert the receiver that a word of data is
between computer and peripherals. During the actual industrial about to be sent, and to force the clock in the receiver into
production, sometimes we do not need the full functionality of synchronization with the clock in the transmitter. These two
UART, but simply integrate its core part. UART includes three clocks must be accurate enough to not have the frequency drift
kernel modules which are the baud rate generator, receiver and by more than 10% during the transmission of the remaining
transmitter. The UART implemented with VHDL language can bits in the word [4].
be integrated into the FPGA to achieve compact, stable and
reliable data transmission. It’s significant for the design of SOC. After the Start Bit, the individual data bits of the word are
The simulation results with Quartus II are completely consistent sent, with the Least Significant Bit (LSB) being sent first. Each
with the UART protocol. bit in the transmission is transmitted for exactly the same
amount of time as all of the other bits, and the receiver “looks”
Keywords- UART; asynchronous serial communication; at the wire at approximately halfway through the period
VHDL; Quartus II; simulation assigned to each bit to determine if the bit is a 1 or a 0. For
example, if it takes two seconds to send each bit, the receiver
I. INTRODUCTION will examine the signal to determine if it is a 1 or a 0 after one
Asynchronous serial communication has advantages of less second has passed, then it will wait two seconds and then
transmission line, high reliability, and long transmission examine the value of the next bit, and so on.
distance, therefore is widely used in data exchange between When the entire data word has been sent, the transmitter
computer and peripherals. Asynchronous serial communication may add a Parity Bit that the transmitter generates. The Parity
is usually implemented by Universal Asynchronous Receiver Bit may be used by the receiver to perform simple error
Transmitter (UART) [1]. UART allows full-duplex checking. Then at least one Stop Bit is sent by the transmitter.
communication in serial link, thus has been widely used in the
data communications and control system. In actual When the receiver has received all of the bits in the data
applications, usually only a few key features of UART are word, it may check for the Parity Bits (both sender and receiver
needed. Specific interface chip will cause waste of resources must agree on whether a Parity Bit is to be used), and then the
and increased cost. Particularly in the field of electronic design, receiver looks for a Stop Bit. If the Stop Bit does not appear
SOC technology is recently becoming increasingly mature. when it is supposed to, the UART considers the entire word to
This situation results in the requirement of realizing the whole be garbled and will report a Framing Error to the host
system function in a single or a very few chips. Designers must processor when the data word is read. The usual cause of a
integrate the similar function module into FPGA. This paper Framing Error is that the sender and receiver clocks were not
uses VHDL to implement the UART core functions and running at the same speed, or that the signal was interrupted.
integrate them into a FPGA chip to achieve compact, stable Regardless of whether the data was received correctly or
and reliable data transmission, which effectively solves the not, the UART automatically discards the Start, Parity and Stop
above problem [2] [3]. bits. If the sender and receiver are configured identically, these
Basic UART communication needs only two signal lines bits are not passed to the host.
(RXD, TXD) to complete full-duplex data communication. If another word is ready for transmission, the Start Bit for
TXD is the transmit side, the output of UART; RXD is the the new word can be sent as soon as the Stop Bit for the
receiver, the input of UART. UART’s basic features are: There previous word has been sent. Because asynchronous data are
are two states in the signal line, using logic 1 (high) and logic 0 “self-synchronizing”, if there are no data to transmit, the
(low) to distinguish respectively. For example, when the transmission line can be idle. The UART frame format is
transmitter is idle, the data line is in the high logic state. shown in Fig. 1.
Otherwise when a word is given to the UART for

This work is supported by the PhD. Fund of Shanghai University of

Engineering Science（A-0501-10-001）

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978-1-4244-9857-4/11/$26.00 ©2011 IEEE
 correctly determine the start bit of a frame data. The receiver
module receives data from RXD pin. RXD jumps into logic 0
Data bits from logic 1 can be regarded as the beginning of a data frame.
When the UART receiver module is reset, it has been waiting
the RXD level to jump. The start bit is identified by detecting
1 2 3 4 5 6 7 8 RXD level changes from high to low. In order to avoid the
misjudgment of the start bit caused by noise, a start bit error
Idle bit Start bit Parity bit Stop bit detect function is added in this design, which requires the
received low level in RXD at least over 50% of the baud rate to
Figure 1. UART Frame Format be able to determine the start bit arrives. Since the receive
clock frequency is 16 times the baud rate in the design, the
II. IMPLEMENTATION OF UART RXD low level lasts at least 8 receiving clock cycles is
In this paper, the top to bottom (Top to Down) design considered start bit arrives. Once the start bit been identified,
method is used. The UART serial communication module is from the next bit, begin to count the rising edge of the baud
divided into three sub-modules: the baud rate generator, clock, and sample RXD when counting. Each sampled value of
receiver module and transmitter module, shown in Fig. 2. the logic level is deposited in the register rbuf [7, 0] by order.
Therefore, the implementation of the UART communication When the count equals 8, all the data bits are surely received,
module is actually the realization of the three sub-modules. The also the 8 serial bits are converted into a byte parallel data..
baud rate generator is used to produce a local clock signal The serial receiver module includes receiving, serial and
which is much higher than the baud rate to control the UART parallel transform, and receive caching, etc. In this paper we
receive and transmit; The UART receiver module is used to use finite state machine to design, shown in Fig. 3.
receive the serial signals at RXD, and convert them into
parallel data; The UART transmit module converts the bytes
into serial bits according to the basic frame format and RXD_SYNC=0
transmits those bits through TXD. R_START

Baud Rate Generator R_STOP RXD_SYNC=1 R_CENTER

RCNT16=0100
RCNT16=1110 AND
AND
Data Receiver Transmitter RBITCNT=FRAMELEN

RCNT16=1110 AND R_WAIT

R_SAMPLE
Figure 2. UART Module RBITCNT/ =FRAMELEN

A. Baud Rate Generator

Figure 3. UART Receiver State Machine
Baud Rate Generator is actually a frequency divider. The
baud rate frequency factor can be calculated according to a
given system clock frequency (oscillator clock) and the The state machine includes five states: R_START (waiting
requested baud rate. The calculated baud rate frequency factor for the start bit), R_CENTER (find midpoint), R_WAIT
is used as the divider factor. In this design, the frequency clock (waiting for the sampling), R_SAMPLE (sampling), and
produced by the baud rate generator is not the baud rate clock, R_STOP (receiving stop bit).
but 16 times the baud rate clock. The purpose is to precisely R_START Status: When the UART receiver is reset, the
sample the asynchronous serial data at the receiver. Assume receiver state machine will be in this state. In this state, the
that the system clock is 32MHz, baud rate is 9600bps, and then state machine has been waiting for the RXD level to jump over
the output clock frequency of baud rate generator should be 16 from logic 1 to logic 0, i.e. the start bit. This alerts the
* 9600Hz. Therefore the frequency coefficient (M) of the baud beginning of a new data frame. Once the start bit is identified,
rate generator is: the state machine will be transferred to R_CENTER state. In
M =32MHz/16*9600Hz=208 Fig. 3, RXD_SYNC is a synchronization signal of RXD.
Because when sampling logic 1 or logic 0, we do not want the
When the UART receives serial data, it is very critical to detected signal to be unstable. So we do not directly detect
determine where to sample the data information. The ideal time RXD signal, but detect the synchronization signal
for sampling is at the middle point of each serial data bit. In RXD_SYNC.
this design, the receive clock frequency is designed to be 16
times the baud rate, therefore, each data width received by R_CENTER Status: For asynchronous serial signal, in
UART is 16 times the receive clock cycle. order to detect the correct signal each time, and minimize the
total error in the later data bits detection. Obviously, it is the
B. Receiver Module most ideal to detect at the middle of each bit. In this state, the
task is to find the midpoint of each bit through the start bit. The
During the UART reception, the serial data and the method is by counting the number of bclkr (the receiving clock
receiving clock are asynchronous, so it is very important to frequency generated by the baud rate generator) (RCNT16 is

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the counter of bclkr). In addition, the start bit detected in the XMIT_CMD. XMIT_CMD_P is a processed signal of
R_START may not be a really start bit, it may be an occasional XMIT_CMD, which is a short pulse signal. Since XMIT_CMD
interference sharp pulse (negative pulse). This interference is an external signal, outside FPGA, its pulse width is unable to
pulse cycle is very short. Therefore, the signal that maintains be limited. If XMIT_CMD is valid, it is still valid after sending
logic 0 over 1 / 4 bit time must be a start bit. one UART data frame. Then the UART transmitter will think
by mistake that a new data transmit command has arrived, and
R_WAIT Status: When the state machine is in this state, once again start the frame transmit. Obviously the frame
waiting for counting bclkr to 15, then entering into transmit is wrong. Here we limit the pulse width of
R_SAMPLE to sample the data bits at the 16th bclkr. At the XMIT_CMD. XMIT_CMD_P is its processed signal. When
same time determining whether the collected data bit length XMIT_CMD_P = '1 ', the state machine transferred to
has reached the data frame length (FRAMELEN). If reaches, it X_START, get ready to send a start bit.
means the stop bits arrives. The FRAMELEN is modifiable in
the design (using the Generic). In this design it is 8, which X_START Status: In this state, sends a logic 0 signal to the
corresponds to the 8-bit data format of UART. TXD for one bit time width, the start bit. Then the state
machine transferred to X_WAIT state. XCNT16 is the counter
R_SAMPLE Status: Data bit sampling. After sampling the of bclkt.
state machine transfers to R_WAIT state unconditionally, waits
for the arrival of the next start bit. X_WAIT Status: Similar with the R_WAIT of UART
receive state machine.
R_STOP Status: Stop bit is either 1 or 1.5, or 2. State
machine doesn’t detect RXD in R_STOP, but output frame X_SHIFT Status: In this state, the state machine realizes the
receiving done signal (REC_DONE <= '1 '). After the stop bit, parallel to serial conversion of outgoing data. Then
state machine turns back to R_START state, waiting for the immediately return to X_WAIT state.
next frame start bit.
X_STOP Status: Stop bit transmit state. When the data
frame transmit is completed, the state machine transferred to
C. Transmit Module this state, and sends 16 bclkt cycle logic 1 signal, that is, 1 stop
The function of transmit module is to convert the sending bit. The state machine turns back to X_IDLE state after
8-bit parallel data into serial data, adds start bit at the head of sending the stop bit, and waits for another data frame transmit
the data as well as the parity and stop bits at the end of the command.
data. When the UART transmit module is reset by the reset
signal, the transmit module immediately enters the ready state III. SIMULATION OF MODULES
to send. In this state, the 8-bit parallel data is read into the
register txdbuf [7: 0]. The transmitter only needs to output 1 bit The simulation software is Quartus II. And the selected
every 16 bclkt (the transmitting clock frequency generated by device is Altera’s Cyclone II FPGA: EP2C5F256C6.
the baud rate generator) cycles. The order follows 1 start bit, 8
data bits, 1 parity bit and 1 stop bit. The parity bit is determined A. Baud Rate Generator Simulation
according to the number of logic 1 in 8 data bits. Then the During simulation, the system clock frequency is set to
parity bit is output. Finally, logic 1 is output as the stop bit. Fig. 32MHz, and baud rate is set to 9600bps. Therefore the
4 shows the transmit module state diagram. receiving sampling clock frequency generated by the baud rate
generator is 153600Hz, which is 16 times of the baud rate.
XCNT16=01111 AND Thus the frequency coefficient of baud rate generator can be
XMIT_CMD_P=0 XMIT_CMD_P=1 calculated, which equals 208. Fig. 5 shows the simulation
X_IDLE
result of baud rate generator. The simulation report shows that
this module uses 42 logic elements （ <1% ） , 33 registers
RXD_SYNC=1 X_START
X_STOP (2%), and meets timing requirement.
XCNT16=01110 AND
XCNT16=01111
XBITCNT=FRAMELEN

XCNT16=01110 AND X_WAIT

X_SHIFT
XBITCNT/ =FRAMELEN

Figure 4. Transmit Module State Diagram

Figure 5. Simulation Result of Baud Rate Generator
This state machine has 5 states: X_IDLE (free), X_START
(start bit), X_WAIT (shift to wait), X_SHIFT (shift), X_STOP B. Receiver Simulation
(stop bit). During receiver simulation, the receiving sampling clock
X_IDLE Status: When the UART is reset, the state frequency generated by the baud rate generator is set to 153600
machine will be in this state. In this state, the UART Hz, UART receiving baud rate is set to 9600bps. The input
transmitter has been waiting a data frame sending command sequence is: 00110110001, including the start bit 0, parity bit 0
and 1 stop bit. The received data is stored into the register rbuf.

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Fig. 6 shows the receiver module simulation diagram. The
figure shows that the data in rbuf from high to low is
00110110, which is just the part of data bits of UART frame.

Figure 8. RTL of Top File

Figure 6. Receiver Simulation Diagram

IV. CONCLUSION
C. Transmitter Simulation
This design uses VHDL as design language to achieve the
During transmitter simulation, the sending clock frequency
modules of UART. Using Quartus II software, Altera's
generated by the baud rate generator is set to 153600 Hz, and
Cyclone series FPGA chip EP2C5F256C6 to complete
UART transmitting baud rate is set to 9600bps. Fig. 7 shows
simulation and test. The results are stable and reliable. The
the transmitter module simulation diagram. The simulation
design has great flexibility, high integration, with some
report shows that this module uses 78 logic elements（<1%, reference value. Especially in the field of electronic design,
13 pins (4%), and meets timing requirement. where SOC technology has recently become increasingly
mature, this design shows great significance.

REFERENCES
[1] Zou,Jie Yang,Jianning。Design and Realization of UART Controller
Bas ed on FPGA
[2] Liakot Ali ， Roslina Sidek ， Ishak Aris ， Alauddin Mohd. Ali ，
Bambang Sunaryo Suparjo. Design of a micro - UART for SoC
application [J].In: Computers and Electrical Engineering 30 (2004) 257–
268.
Figure 7 Transmitter Simulation Diagram
[3] HU Hua, BAI Feng-e. Design and Simulation of UART Serial
Communication Module Based on Verilog -HDL[J]. J ISUANJ I YU
D. RTL of Top File XIANDA IHUA 2008 Vol. 8
Fig. 8 shows the RTL of UART Top File. It includes the [4] Frank Durda Serial and UART Tutorial. [email protected]
baud rate generator, receiver, and transmitter modules.

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