IEEE PHOTONICS JOURNAL, VOL. 15, NO.

5, OCTOBER 2023 7101406

Design and Analysis of a Nanosecond Burst-Mode

CDR Using MATLAB/Simulink and
Opti-System Co-Simulation
Heng Zhang , Yuandong Li , Wenhe Yin , Yuan Du , Senior Member, IEEE, and Li Du , Member, IEEE

Abstract—Optical packet switching (OPS) networks are promis- have emerged as a promising solution due to their high band-
ing to accommodate the growing traffic and reduce power con- width capacity and elimination of electrical-optical conversions
sumption in data center communications. OPS networks with [7], [8], [9]. Given that many applications in data centers produce
nanosecond switching time require nanosecond clock and data
recovery (CDR) circuits. The nanosecond CDR can be achieved by short traffic packets, OPS networks with nanosecond configura-
utilizing a global frequency-synchronized reference clock for both tion time are required, which also necessitates the development
transmitters (TX) and receivers (RX) and adopting a phase com- of CDR with nanosecond locking time [10]. Existing burst-mode
pensation scheme, which leads to predictably managed frequency CDR circuits, such as all-digital CDR [11], [12], gated VCO
and phase. However, the CDR still needs to be comprehensively
CDR [13], and over-sampling CDR [14], [15], [16], either lack
evaluated considering various interferes. We add more analysis
by developing a novel optoelectronic co-simulation system that practical integration in OPS transceivers or can only achieve
combines the software Opti-system and MATLAB/Simulink. We microsecond-level data recovery [17], [18]. Therefore, there is
set up a simple OPS network equipped with the CDR architecture an urgent need to develop efficient nanosecond CDRs to meet
using the simulation system. The feasibility of the CDR mechanism the demands of nanosecond OPS networks.
is validated, then various interferes are characterized to evaluate
For packet-based optical switching networks, the variability
the CDR’s stability, including the location variation of reference
clock source, channel jitters, and carrier power variations. in clock frequency and phase from packet to packet contributes
to the lengthy locking time of CDR circuits. To address this
Index Terms—Data center networks, optical packet switching issue, references [19], [20], [21] proposed a sub-nanosecond
network, clock and data recovery, MATLAB/Simulink, opti-
system. CDR architecture specifically designed for data center OPS net-
works by taking a network-level perspective. Briefly, frequency-
synchronized reference clocks are used for both transmitters
I. INTRODUCTION (TX) and receivers (RX) in the OPS network, thereby requiring
ATA centers are being rapidly deployed in various orga- the determination of only the phases in the RX. By leveraging
D nizations, including companies, institutions, and govern-
ment offices. These centers host a growing number of appli-
the observation that the phase offsets between specific pairs of
transceivers remains relatively constant in a stable environment,
cations like scientific computing, deep learning, and financial the group first measures the phase in the RX and then applies
analysis, resulting in increased demand for bandwidth in data phase compensation in the TX. This approach aligns the phases
center communication networks [1], [2], [3]. Current data center in RX, thereby accelerating the locking process. The proposed
networks are dominated by multi-tier electrical switch networks. CDR architecture demonstrated impressive performance in
However, the bandwidth limitations of electrical processing 25.6 Gbps burst-mode data transmission, achieving a locking
chips and the power consumption associated with frequent time of 625 ps. However, various interferences can introduce
electrical-optical conversions pose challenges [4], [5], [6]. To noise into phase offsets, potentially leading to the failure of
overcome these issues, optical packet switch (OPS) networks the phase compensation process. The paper [20] thoroughly
investigated the impact of temperature variation on phase offsets,
Manuscript received 7 July 2023; accepted 19 August 2023. Date of publi- considering it as the primary concern. Nonetheless, it is crucial
cation 23 August 2023; date of current version 4 September 2023. This work to further characterize the impacts of other interferes, such as
was supported in part by the National Key Research and Development Program reference clock variations, channel jitters, and carrier power
of China under Grant 2021YFA0717700 and in part by the National NSF of
China under Grants 62211530492, 62141411, 62004096, and 62004097. (Cor- variations.
responding authors: Yuan Du; Li Du.) To provide more insights into the nanosecond CDR, we
The authors are with the School of Electronic Science and Engineer- design and analyze a 25.6 Gbps OPS network equipped with
ing, Nanjing University, Nanjing 210023, China (e-mail: [email protected];
[email protected]). the proposed CDR architecture by developing a novel opto-
This article has supplementary downloadable material available at http://doi. electronic co-simulation system. The overall structure of our
org/10.1109/JPHOT.2023.3307687, provided by the authors. simulation is depicted in Fig. 1. Two software tools are used
This article has supplementary downloadable material available at
https://doi.org/10.1109/JPHOT.2023.3307687, provided by the authors. in the simulation: Opti-System for optical-related simulations
Digital Object Identifier 10.1109/JPHOT.2023.3307687 and MATLAB/Simulink for electrical-related simulations. In

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
7101406 IEEE PHOTONICS JOURNAL, VOL. 15, NO. 5, OCTOBER 2023

Fig. 2. Generation of four-phase 12.8G clock based on the 6-bit PI code.

TABLE I
REFERENCE CLOCKS SELECTION BASED ON MSB_2BIT

Fig. 1. Block diagram of the entire simulation model. The green part is
modeled in Opti-System and the blue part is modeled in MATLAB/Simulink.

MATLAB/Simulink, we model one TX node and one RX node

for the OPS network. The TX and RX are interconnected by TABLE II
an optical channel, which is modeled using Opti-System. Two PHASE SELECTION BASED ON LSB_4BIT
optical carriers are used and switched alternately to mimic
the function of packet switching. We successfully validated
the feasibility of the modeled nanosecond OPS network us-
ing the simulation test bench. We conducted an investigation
into the influence of reference clock variations on the overall
system performance. Additionally, we assessed the stability of
the nanosecond OPS network under channel jitters and optical
carrier power fluctuations. It is worth noting that the simulation
system proposed in this paper can also be utilized to validate
other electrical-optical codesigned modules.
two optical carriers. These phase offsets, represented as 6-bit
II. DETAILS OF MODELED OPS NETWORK PI codes, are then transmitted back to the transmitter (TX).
A. Overview of the Simulation Model Subsequently, the TX performs phase compensations for the
corresponding wavelengths based on each packet, aligning the
The overall structure of the simulated 25.6 Gbps OPS network
data delay in the RX for fast CDR locking.
is illustrated in Fig. 1. Inside the software Opti-System, an 800 M
optical reference clock is generated and transmitted to TX and
RX through two optical fibers. In MATLAB/Simulink, two B. TX Node Model
phase lock loops (PLLs) are modeled to multiply the 800 M TX transmits data at a bandwidth of 25.6G and has the capabil-
clock to 12.8G separately in TX and RX. This ensures frequency ity to adjust the phases of the reference clock with a resolution
synchronization of reference clocks in both the TX and RX. The of 1/64 × 2π. By employing proper phase compensation, the
details of PLL are shown in Fig. S5 (supplementary materials). phases of the two wavelengths can be aligned at RX. The details
The 12.8G reference clock is adjusted with appropriate phase of the phase interpolators are depicted in Fig. 2. The 12.8G
shifts to generate the required single-ended 25.6G clock. Further reference clock is fed into 8 identical delay modules, resulting
details on this process will be explained in Section II-B. TX then in 8 reference clocks with phase shifts of 45o , 90o , 135o , 180o ,
sends data at the 25.6G reference clock. Two optical carriers are 225o , 270o , 315o , and 360o . Assuming the PI codes of the two
utilized and switched by an optical switch at a fixed switching optical carriers are already sent from the RX. The MSB 2bit of
time (100ns). The optical signals are transmitted in an optical the 6-bit digit is utilized to select 2 clocks from the 8 reference
fiber modeled in Opti-system. RX module includes modified a clocks according to the correspondence specified in Table I.
Bang-Bang phase detector (BBPD) and a finite state machine These selected clocks are labeled as clock_s1 and clock_s3. For
(FSM) for phase determination and a PLL-based CDR for clock instance, if the MSB_2bit is ‘00’, clocks with phase values of
recovery and jitter tracking. 0o and 180o are chosen. Subsequently, clock_s1 and clock_s3
To achieve a short locking time of PLL-based CDR, the serve as differential reference clocks. The LSB_4bit is utilized
phases of the two wavelengths need to be aligned in RX. In to simultaneously delay clock_s1 and clock_s3 based on preset
our simulation, RX initially measures the phase offsets for the phase shift values, as illustrated in Table II. The delayed clocks
ZHANG et al.: DESIGN AND ANALYSIS OF A NANOSECOND BURST-MODE CDR USING MATLAB/SIMULINK 7101406

Fig. 4. Details in phase determination in RX.

Fig. 3. (a) Overview of TX. (b) Waveforms in generating 25.6 clock.

are further labeled as clock_1 and clock_3. Clock_1 and clock_3

are both delayed by another 90o to obtain clock_2 and clock_4.
Clock_1, clock_2, clock_3, and clock_4 are combined to
generate a 25.6G clock, as depicted in Fig. 3(a). Two D flip-flops
are utilized, where clock_1 and clock_3 serve as the trigger
clock, while clock_4 and clock_2 serve as the reset clock.
Consequently, clock signals Q1 and Q2 are obtained, as shown
in Fig. 3(b). Q1 and Q2 are then integrated by an OR circuit to
produce the 25.6G reference clock, which is used to send data.
The 25.6G reference clock possesses the desired phase shift.
In the simulation, we use repeated 16-bit sequences
(0000,1111,0110,0101) to serve as the transmission data. This
sequence is repeated 128 times to form a data packet of 2048
bits. Given that the transmission rate is set as 25.6 Gbps, it takes Fig. 5. (a) Waveforms in the BBPD sampling process, (b) the circuit details
of phase determination process.
80 ns to transmit a single data packet. An inter-packet gap of
20 ns is set to allow for tasks such as optical carrier tuning and
phase compensation.
logic modules, which are sampled by clock_4 (red circles and
arrows in Fig. 5(a)). If S1 XNOR S2 = 1, and S2 XNOR S3 =
C. RX Node Model
0, indicating that the clock is leading the data, then total_lead
RX has a BBPD and FSM for phase determination and a = total_lead+1. On the contrary, If S1 XNOR S2 = 0, and
PLL-based CDR for clock recovery. The phase determination S2 XNOR S3 = 1, which indicates that the clock is lagging
mechanism in RX is shown in Fig. 4. Optical signals from the behind the data, then total_lag = total_lag+1. A similar process
channel are distributed to 4 D flip-flops and sampled by clock_1, happens in S3, S4, and S1, which are sampled by clock_2 (blue
clock_2, clock_3, and clock_4. These four clocks are generated circles and arrows).
in a similar manner as in TX. Upon the 4-phase clock, specific The decision regarding the relative timing of the clock and
logic is designed to determine whether the clock is leading or data signals is made every 64 bits of data by comparing the total
lagging the data. As shown in Fig. 5(a), clock_1, clock_2, and number of leads and lags, as depicted in Fig. 5(b). Within each
clock_3 are first used to sample the data to obtain signals S1, S2, 64-bit data segment, these lead and lag judgments are made
and S3. S1 and S2, S2 and S3 are then passed through two XNOR 32 times, which are added by two Adders. If, after these 32
7101406 IEEE PHOTONICS JOURNAL, VOL. 15, NO. 5, OCTOBER 2023

Fig. 6. Pseudocode of the FSM.

iterations, the total number of leads is equal to the total number

of lags, the PI code remains unchanged. If the total number of
leads is greater than the total number of lags, the PI code is Fig. 7. (a) Signals of first two data packets, (b) lead votes, (c) lag votes, and
decremented by 1. Conversely, if the total number of leads is (d) PI code altering.
less than the total number of lags, the PI code is incremented by
1. Subsequently, the updated PI codes are used to generate new
sets of four-phase clocks. The Adders are reset to 0 and the lead insertion loss of 15 dB. A trans-conductance amplifier (TIA)
or lag decisions are made again. The pseudocode of the FSM is with a gain of 40 dB converts the photocurrent into voltage.
presented in Fig. 6. Finally, a limiting amplifier (LA) with a gain of 30 dB amplifies
6-bit PI codes are used for precise phase control, resulting in the voltage signal to a maximum of 1V and a minimum of
a phase shifting precision of 1/64 × 2π. The range of phase 0 V.
adjustment during a single packet is 2 × 32 × 1/64 × 2π
= 2π, covering all possible conditions. Finally, the stable PI III. SIMULATION RESULTS AND DISCUSSIONS
codes obtained through this iterative process are sent back to A. A Typical Transmission Process
the transmitter (TX) for phase compensation, ensuring accurate
Repeated packets were utilized to validate the CDR. The
phase alignment for the two wavelengths.
initial two packets in each cycle were employed to measure the
phase delays of the optical carriers, and the obtained phase shifts
D. Optical Fiber Channel (PI codes) were sent back to the TX. Fig. 7 illustrates a typical
The optical channel is modeled in Opti-system. As shown phase determination process. Fig. 7(a) displays the RX signals
in Fig. S4 (supplementary materials), the data packet generated of the first two data packets. By employing the BBPD and FSM,
by the TX in Simulink is converted into NRZ electronic pulses the initial lead vote is observed to be 28, while the initial lag
by an NRZ pulse generator in Opti-System. Two continuous vote is 4 (see Fig. 7(b) and (c)). Based on these vote results, PI
waves (CW) with wavelengths of 1550 nm and 1450 nm are code is decremented by 1 and the reference clock is delayed by
generated using the laser modules to serve as optical carriers. 1/64 × 2π. Then the phase detection process is repeated. After
These optical carriers are then routed through an optical switch, 5 decisions, the lag vote and lead vote become equal, indicating
which alternates between the two carriers every 100 ns. The the attainment of a stable PI code (see Fig. 7(d)). It should be
powers of the two CW laser modules vary in the transmission noted that slight fluctuations (±1/64 × 2π) may occur after the
process (see Fig. S6 in supplementary materials). The modulated lag votes and lead votes reach equal. However, these fluctuations
optical carrier is transmitted through an optical fiber modeled resemble the CDR locking process of practical PI CDR circuits
in Opti-system. The fiber parameters, such as length (1 km), that are implemented by FPGAs and do not impact the data
reference wavelength (1500 nm), attenuation (0.2 dB/km), group recovery process.
velocity dispersion (17 ps/nm/km), and effective area (80 μm2 ), During the gap of the subsequent 99998 packets, TX adjusts
are set to mimic Corning SMF-28 optical fiber characteristics. To the phases of the reference clock periodically to compensate the
represent temperature-induced phase variation, an 80 ps delay phase offsets, allowing PLL-based CDR to rapidly lock onto
module is included. A photodetector module with a sensitivity the correct phases of data packets for both wavelengths. The
of 1 A/W converts the optical signal back into an electrical PI codes are updated every 1000000 packets (100 ms). The bit
signal. A low-pass Gaussian filter is applied to eliminate high- error ratio (BER) is calculated after a 100-second transmission
frequency noise, with a cutoff frequency set at 30 GHz and an test using a BER module modeled in MATLAB/Simulink (see
ZHANG et al.: DESIGN AND ANALYSIS OF A NANOSECOND BURST-MODE CDR USING MATLAB/SIMULINK 7101406

Fig. 8. Eye diagram of the received electrical signal with deterministic jitters.

Fig. S1). The BER module compares the recovered data with
preset local data. With the phase compensation process, the re-
ceived data is completely accurate, except for the first two pack-
ets, demonstrating an instant phase locking for the subsequent Fig. 9. Eye diagram of the received electrical signal with random jitters of
packets. different RMS values.

B. Transceiver Performance Under Interferes

Temperature variations are a significant factor affecting phase
delays, as extensively studied in [20]. However, other parameters
such as reference clock synchronization, channel jitters, and
optical carrier power variations also impact the phases. To assess
the stability of the OPS network with different reference clock
source locations, we characterized the distribution of the 800 M
optical source. By introducing two optical fiber modules with
varying lengths, we designed five cases to examine different
scenarios (see Fig. S7 in supplementary materials). The PI
codes varied among the cases, indicating changes in detected
phase offsets due to the different distances traveled by the
Fig. 10. Relationship between JRMS and BER.
optical reference clock. After performing corresponding phase
compensation in the first two data packets, the recorded BERs
for subsequent data packets were consistently 0 across all cases. influence of optical carrier power variations, the optical carrier
This implies that the phase compensation CDR is insensitive to power is first set as 0 dBm. Then after transmitting the first
location variations of optical reference clock source. 500000 packets, the powers of both optical carriers are switched
We further introduced deterministic jitters into the channel. to 2 dbm to send the following packets (Fig. S6 in supplementary
Sinusoidal jitters with peak-to-peak amplitudes (SJpkpk ) of materials). The eye diagram of the optical signals with zero
0.1UI, 0.3UI, and 0.5UI were separately added at a frequency of jitters added is shown in Fig. 11(a). Fig. 11(b) shows the two
1MHz. The eye diagram of the received data is shown in Fig. 8. signals after passing through LA. Signals of 0 dbm suffer from
The PI codes produced by the FSM remained unchanged for an obvious reduction in duty cycle, which shrinks the data
the three deterministic jitters. This suggests that channel deter- sampling interval. But the additional phase offset is not observed
ministic jitter of up to 0.5UI SJpkpk has a negligible influence in Fig. 11(b). BER results are all tested to be 0.
on the phase variation. The BER results after 1000 cycles of We further evaluate the performance of the CDR under the
transmission tests showed a value of 0. simultaneous influence of channel jitters and carrier power
Next, we introduced random jitters into the system with differ- variations. As shown in Fig. 11(c), random jitter of 0.1UI
ent root mean square (JRMS ) values: 0UI, 0.05UI, 0.1UI, 0.15UI, RMS was added into the channel, and it can be seen that the
0.20UI, and 0.25UI. The resulting eye diagrams are displayed optical signals suffered from obvious disturbances. After the
in Fig. 9. The BER values, as shown in Fig. 10, demonstrated signals pass through LA, a narrow eye diagram is observed from
that when the RMS of random jitter was below 0.1UI, the Fig. 11(d). The BER of the two carriers (0 dBm and 2 dBm) with
recorded remained at 0. However, as the JRMS exceeded 0.1UI, the same random jitter is recorded by the BER module, which
the BER increased exponentially with the RMS amplitude. The is 6.2 × 10−10 and 2.7 × 10−12 respectively. The BER can be
standard deviations were calculated from fifty sets of repeated further decreased by inserting error-correcting code into the data
experiments. packets.

C. Influence of Carrier Power Variation IV. CONCLUSION

In the real data center environment, the carrier power may In this study, we have presented a novel optoelectronic
suffer from variations because of the mismatch of different light co-simulation method that combines Opti-system for optical
sources and semiconductor optical amplifiers. To evaluate the simulations and MATLAB/Simulink for electrical simulations.
7101406 IEEE PHOTONICS JOURNAL, VOL. 15, NO. 5, OCTOBER 2023

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