UNIT-01: Explain The Architecture of A Basic Computer
UNIT-01: Explain The Architecture of A Basic Computer
● * A comma is used to separate two or more operations that are executed at the same
time.
● Eg: R2 R1, R1 R2 t t+1 /n Load Control Circuit R2 R1 Clock p (a) Block Diagram Clock
Load (b) Timing Diagram
● Figure 5:
● Transfer from R1 to R2 when p =1
● The above statement denotes an operation that exchanges the content of two registers
during one common clock pulse.
Discuss about Memory Reference Instructions.
1. Memory Reference Instructions In Memory reference instruction:
2. First 12 bits(0-11) specify an address.
3. Next 3 bits specify operation code (opcode) and can range from 000 to 110.
4.Left most bit specify the addressing mode I I = 0 for direct address I = 1 for indirect
address
5. The address field is denoted by three x’s (in hexadecimal notation) and is equivalent
to 12-bit address.
6.When I = 0, the last four bits of an instruction have a hexadecimal digit equivalent from
0 to 6 since the last bit is zero (0).
7. When I = 1 the last four bits of an instruction have a hexadecimal digit equivalent from
8 to E since the last bit is one
Figu
re 21: Memory - reference instruction format
Computer Instructions for Memory
What is a bus? What are different types of buses used in
computers? Discuss their uses.
A bus is a communication system within a computer or between computers
that transfers data between different components. The purpose of buses is to
reduce the number of "pathways" needed forcommunication between the
components, by carrying out all communications over a single data channel.
Types of Computer Bus
1. Address Bus
2. Data Bus
3. Control Bus
1. Address Bus
● A collection of wires used to identify particular location in main memory is called
Address Bus. Or in other words, the information used to describe the memory locations
● The address bus transports memory addresses which the processor wants to access in
● The size of address bus determines how many unique memory locations can be
addressed.
● Example:
memory.
memory
memory.
2. Data Bus
● A collection of wires through which data is transmitted from one part of a computer to
● Data Bus can be thought of as a highway on which data travels within a computer.
● The main objective of data bus is transfer of the data between microprocessor to input/
● The data bus transfers instructions coming from or going to the processor.
● The data bus is bidirectional because the data can flow in either direction from CPU to
● The size (width) of bus determines how much data can be transmitted at one time.
● Example:
Control Bus
● The connections that carry control information between the CPU and other devices
● The main objective of control bus is all signals controller carried from processor to other
hardware device.
● The control bus transports orders and synchonisation signal coming from the control
● The Control bus is bidirectional because the data can flow in either direction from CPU
● Example:
Data bus:
A data bus is a communication system that transfers data between components of
a computer, or between computers. It has many uses, including:
Transferring data
A data bus carries data between the CPU and memory, and between the
CPU and I/O devices. It allows the CPU to read from or write to memory and
I/O device
Draw the schematic diagram and discuss the working of arithmetic
logic shift unit.
Inputs Ai and Bi are applied to both the arithmetic and logic units.
A particular microoperation is selected with inputs S1 and S0. A 4 x 1 multiplexer at
the output chooses between an arithmetic output in Di and a logic output in Ei.
The data in the multiplexer are selected with inputs S3 and S2
.The other two data inputs to the multiplexer receive inputs Ai-1 for the shift-right
operation and Ai+1 for the shift-left operation.
The circuit whose one stage is specified in the above figure provides eight arithmetic
microoperation, four logic microoperations, and two shift microoperations.
Each operation is selected with the five variables S3, S2, S1, S0 and Cin The input
carry Cin is used for arithmetic operations only.
The first eight are arithmetic microoperations, which are selected with S3S2 = 00.
The next four are logic microoperations, which are selected with S3S2 = 01.
The input carry has no effect during the logic microoperations and is marked with
don't-care x.
The last two operations are shift microoperations and are selected with S3S2 = 10
for shift right microoperation and S3S2=and 11 for shift left microoperation.
The other three inputs have no effect on the shift.
Table 10: Function Table for Arithmetic Logic Shift Unit
The operation code specifies the operation to be performed. The mode field is used to locate
the operands needed for the operation. There may or may not be an address field in the
instruction. If there is an address field, it may designate a memory address or a processor
register. Moreover, as discussed in the preceding section, the instruction may have more
than one address field, and each address field may be associated with its own particular
addressing mode. Although most addressing modes modify the address field of the
instruction, there are two modes that need no address field at all. These are the implied
and immediate modes.
1. Implied Mode: In this mode the operands are specified implicitly in the definition of the
instruction.
For example, the instruction “complement accumulator” is an implied-mode instruction
because the operand in the accumulator register is implied in the definition of the
instruction. In fact, all register reference instructions that use an accumulator are implied-
mode instructions.Example: Zero-address instructions in a stack-organized computer are
implied-mode instructions since the operands are implied to be on top of the stack. CMA,
CME, CLE, CLA
2. Immediate Mode: In this mode the operand is specified in the address part of the
instruction itself. In other words, an immediate-mode instruction has an operand field
rather than an address field. Immediate-mode instructions are useful for initializing
registers to a constant value. LD
3. Register Mode: In this mode the operands are in registers that reside within the CPU. The
particular register is selected from a register field in the instruction. A k-bit field can
specify any one of 2k registers. LD R
4. Register Indirect Mode: In this mode the instruction specifies a register in the CPU
whose contents give the address of the operand in memory. In other words, the selected
register contains the address of the operand rather than the operand itself. Before using a
register indirect mode instruction, the programmer must ensure that the memory address
for the operand is placed in the processor register with a previous instruction. A reference
to the register is then equivalent to specifying a memory address. The advantage of a
register indirect mode instruction is that the address field of the instruction sues fewer
bits to select a register than would have been required to specify a memory address
directly. LD (R) OR LD R
5. Auto increment or Auto decrement Mode: This is similar to the register indirect mode
except that the register value is incremented or decremented after (or before) its value is
used to access memory. When the address stored in the register refers to a table of data in
memory, it is necessary to increment or decrement the register after every access to the
table. LD (R) + Auto increment LD (R) - Auto decrement
6. Direct Address Mode: In this mode the effective address is equal to the address part of
the instruction. The operand resides in memory. In a branch-type instruction the address
field specifies the actual branch address. LD 10
7. Indirect Address Mode: In this mode the address field of the instruction gives the
address where the effective address is stored in memory. Control fetches the instruction
from memory and uses its address part to access memory again to read the effective
address. LD (10)
8. Relative Address Mode: In this mode the content of the program counter is added to the
address part of the instruction in order to obtain the effective address. The address part of
the instruction is usually a signed number (in 2’s complement representation) which can
be either positive or negative. When this number is added to the content of the program
counter, the result produces an effective address whose position in memory is relative to
the address of the next instruction. LD
9. Indexed Addressing Mode: In this mode the content of an index register is added to the
address part of the instruction to obtain the effective address. The index register is a
special CPU register that contains an index value. The address field of the instruction
defines the beginning address of a data array in memory. LD 5(IR)
10. Base Register Addressing Mode: In this mode the content of a base register is added to
the address part of the instruction to obtain the effective address. This is similar to the
indexed addressing mode except that the register is now called a base register instead of
an index register. The difference between the two modes is in the way they are used
rather than in the way that they are computed. An index register is assumed to hold an
index number that is relative to the address part of the instruction. A base register is
assumed to hold a base address and the address field of the instruction gives a
displacement relative to this base address. The base register addressing mode is used in
computers to facilitate the relocation of programs in memory. When programs and data
are moved from one segment of memory to another, as required in multiprogramming
systems, the address values of the base register requires updating to reflect the beginning
of a new memory segment. LD 5(BR)
UNIT _03
Describe the control unit organization with a separate Encoder and
Decoder functions in a hardwired control.
Explain about Input-output interface.
Explain data types used in data representations with one example for
each
Explain the Booth’s algorithm for multiplication of decimal numbers.
● As the platter spins, the read/write head senses the magnetic field of
the regions it passes over.
● Changes in the magnetic field induce a small electric current in the
head (using electromagnetic induction).
● This current is converted into binary data (0s and 1s) and processed
by the hard disk controller.
● The controller translates the binary data into meaningful information
for the computer.
What is a cache memory? What is its use in computers?
Already there in set -01
In a certain system the main memory access time is 100 ns. The
cache is 10 time faster than the main memory and uses the write
though protocol. If the hit ratio for read request is 0.92 and 85% of
the memory requests generated by the CPU are for read, the
remaining being for write; then what is the average time
consideration for both read and write requests?
Given:
The data path refers to the hardware components that carry the data, like registers,
buses, and ALUs (Arithmetic Logic Units), which move data between different
stages of execution in a pipeline. The data path allows the flow of information as
the instructions are processed through various stages, such as fetching, decoding,
executing, memory access, and writing back.
The control path manages the flow of data and the sequence of operations by
directing the various stages in the pipeline. It involves control signals that
determine when and how different parts of the data path are used, ensuring
synchronization between the stages of the pipeline.