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COA QUESTIONS

UNIT 1

1. Evaluate the arithmetic statement X using a general register center with three-address, two-
address, and one-address instruction formats. Write a program to evaluate the expression:
X=(A+B)×(C+D)X = (A + B) \times (C + D).

2. Define the term Computer architecture and Computer organization.

3. What is meant by bus arbitration? List different types of bus arbitration.

4. i. Draw a diagram of a bus system using MUX, which has four registers of size 4 bits each.
ii. Evaluate the arithmetic statement:
X=A+B×[C×D+E×(F+G)]X = A + B \times [C \times D + E \times (F + G)]
using a stack-organized computer with zero-address operation instructions.

5. a. An instruction is stored at location 400 with its address field at location 401. The address
field has the value 500. A processor register R1 contains the number 200. Evaluate the
effective address if the addressing mode of the instruction is:
i) Direct
ii) Immediate
iii) Relative
iv) Register indirect
v) Index with R1 as index register

6. b. What do you mean by processor organization? Explain various types of processor

organization.

7. a. List and briefly define the main structural components of a computer.

8. c. Represent the following conditional control statements by two register transfer statements
with control functions:
If P=1P = 1, then R1→R2R1 \rightarrow R2; else if Q=1Q = 1, then R1→R3R1 \rightarrow R3.

9. a. A digital computer has a common bus system for 8 registers of 16 bits each. The bus is
constructed using multiplexers.
i) How many select inputs are there in each multiplexer?
ii) What is the size of multiplexers needed?
iii) How many multiplexers are there in the bus?

10. a. Draw a diagram of a Bus system in which it uses 3-state buffers and a decoder instead of
the multiplexers.

11. b. Explain in detail multiple bus organization with the help of a diagram.

12. a. Define the term Computer Architecture.

b. Draw the basic functional units of a computer.
 13. a. Convert the following arithmetic expressions from infix to postfix:
i) A×B+C×D+E×FA \times B + C \times D + E \times F
ii) A×[B+C×CD+E]/F×(G+H)A \times [B + C \times CD + E] / F \times (G + H)

14. a. Describe in detail the different kinds of addressing modes with an example.
b. Discuss stack Organization. Explain the following in detail:
i) Register stack
ii) Memory stack

15. b. How memory read and write operations are performed in a computer system?

16. a. Explain the functional units of a computer system in detail.

17. a. Explain about stack organization used in processors. What do you understand by a register
stack?

18. b. What is an effective address? How is it calculated in different types of addressing modes?
Explain.

19. a. What are the different types of Buses used in computer architecture? Name the different
types of multipliers.

20. a. What is meant by the term BUS arbitration? Why is it needed? How can bus arbitration be
implemented in Daisy chaining scheme?

21. a. What do you mean by processor organization? Explain various types of processor
organization with suitable examples.

22. b. Differentiate between Memory stack and register stack.

23. What is bus arbitration?

UNIT 2

1. a. Draw the flow chart of Booth’s Algorithm for multiplication and show the multiplication
process using Booth’s Algorithm for (−7)×(+3)(-7) \times (+3).

2. a. What is a microprogram sequencer? With block diagram, explain the working of a

microprogram sequencer.

3. b. Draw a flowchart for adding and subtracting two fixed-point binary numbers where
negative numbers are signed 1’s complement representation.

4. c. Discuss biasing with reference to floating point representation.

5. d. What is the restoring method in division algorithm?

6. Explain in detail the principle of carry look-ahead adder and design a 4-bit CLA adder.

7. a. Show the systemic multiplication process of 20×(−19)20 \times (-19) using Booth’s
algorithm.

8. b. Explain IEEE standard for floating point representation. Represent the number
(−1460.125)10(-1460.125)_{10} in single precision and double precision format.
9. d. Design a 4-bit combinational increment circuit using four full adder circuits.

10. g. Register A holds the binary value 10011101. What is the register value after arithmetic
shift right? Starting from the initial number 10011101, determine the register value after
arithmetic shift left, and state whether there is an overflow.

11. c. Explain the 2-bit by 2-bit Array multiplier. Draw the flowchart for divide operation of two
numbers in signed magnitude form.

12. a. A binary floating-point number has seven bits for a biased exponent. The constant used for
the bias is 64.
i) List the biased representation of all exponents from -64 to +63.
ii) Show that after the addition of two biased exponents, it is necessary to subtract 64 in
order to have a biased exponent’s sum.
iii) Show that after the subtraction of two biased exponents, it is necessary to add 64 in order
to have a biased exponent’s difference.

13. Show the multiplication process using Booth algorithm when the following binary numbers,
(+13)×(−15)(+13) \times (-15) are multiplied.

14. c. Perform the 2’s complement subtraction of smaller number 101101101101 from larger
number 111001111001.

15. d. What is the role of Multiplexer and Decoder?

16. b. Design a 4-bit Carry-Look ahead Adder and demonstrate its operation with an example.

17. a. Represent the following decimal number in IEEE standard floating-point format in a single
precision method (32-bit) representation method:
i) (65.175)10(65.175)_{10}
ii) (−307.1875)10(-307.1875)_{10}

18. b. Using Booth algorithm, perform the multiplication on the following 6-bit unsigned integer
10110011×1101010110110011 \times 11010101.

19. b. Explain IEEE-754 standard for floating point representation. Express

(314.175)10(314.175)_{10} in all the IEEE-754 models.

20. a. Describe the derivation procedure of look ahead carry adder by an example with the help
of block diagram.

21. b. Show the systematic multiplication process of (−15)×(−16)(-15) \times (-16) using Booth’s
Algorithm.

22. b. Show the multiplication process using Booth’s algorithm when the following numbers are
multiplied:
(−12)×(−18)(-12) \times (-18).

23. a. Explain in detail the principle of carry look ahead adder and design a 4-bit CLA adder.

24. b. Represent the following decimal number in IEEE standard floating-point format in a single
precision method (32-bit) representation method.
i) (85.125)10(85.125)_{10}
ii) (−307.1875)10(-307.1875)_{10}
UNIT 3

1. Perform the division process 001111÷0011001111 \div 0011 (use a dividend of bgsbgs).

2. e. Define micro operation and micro code.

3. f. Write short notes on RISC.

4. c. Draw the flowchart for instruction cycle with neat diagram and explain.

5. a. What is a micro program sequencer? With block diagram, explain the working of micro
program sequencer.

6. b. Differentiate between hardwired and microprogrammed control unit. Explain each

component of the hardwired control unit organization.

7. b. Differentiate between horizontal and vertical microprogramming.

8. a. Write a program to evaluate arithmetic expression using stack organized computer with 0-
address instructions:
X=(A−B)×(((C−D×E)/F)/G)X = (A - B) \times (((C - D \times E) / F) / G).

9. b. List the differences between hardwired and microprogrammed control in tabular format.
Write the sequence of control steps for the following instruction for single bus architecture:
R1→R2×R3R1 \rightarrow R2 \times R3.

10. Write the differences between RISC and CISC.

11. f. What are the types of microinstructions available?

12. i. Draw the timing diagram for an instruction and explain.

ii. Give a note on subroutine.

13. What is parallelism and pipelining in computer architecture? Explain in detail.

14. Explain the organization of Microprogrammed control unit in detail.

15. a. List the steps involved in an instruction cycle.

16. e. Define instruction cycle.

17. c. Explain the concept of pipelining and also explain types of pipelining.

18. a. Write a program to evaluate the arithmetic statement:

P=((X−Y+Z)×(AB))/(CD×E)P = ((X − Y + Z) \times (A^B)) / (C^D \times E)
By using:
i) Two address instructions
ii) One address instructions
iii) Zero address instructions

19. b. What are the differences between hardwired and micro-programmed control unit? What
are the different phases of an instruction cycle?

20. c. What is pipelining? What are the different stages of pipelining? Explain in detail.

21. a. Explain the different cycles of an instruction execution.

 22. b. Differentiate between hardwired

and microprogrammed control unit. Explain each component of hardwired control unit organization.

UNIT 4

1. What is the difference between RAM and DRAM?

2. A two-way set associative memory uses blocks of 4 words. Cache can accommodate a total
of 128K×3128K \times 3 words from memory. The main memory size is ...

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UNIT 4

3. What is associative memory? Explain with the help of a block diagram. Also, mention the
situations in which associative memory can be effectively utilized.

4. A Computer uses a memory unit with 256×32256 \times 32 bits. A binary instruction code is
stored in one word of memory. The instruction has four parts: an index bit, an operation
code, a register code part (to specify one of 64 registers), and an address part.
i) How many bits are there in the operation code, the register code part, and the address
part?
ii) Draw the instruction word format and indicate the number of bits in each part.
iii) How many bits are there in the data and address inputs of the memory?

5. Define hit ratio.

6. What do you mean by page fault?

7. Discuss 2D RAM and 2.5D RAM with suitable diagrams.

8. a. Calculate the page fault for a given string with the help of the LRU & FIFO page
replacement algorithms. Size of frames = 4 and string:
1,2,3,4,2,1,5,6,2,1,2,3,7,6,3,2,1,2,3,61, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6.

9. b. A computer uses RAM chips of 1024×11024 \times 1 capacity.

i) How many chips are needed & how should their address lines be connected to provide a
memory capacity of 1024×81024 \times 8?
ii) How many chips are needed to provide a memory capacity of 16 KB?

10. What is the difference between RAM and DRAM?

11. h. What is an Associative memory? What are its advantages and disadvantages?

12.

6. Difference between RAM and DRAM.

13. TYPES OF INSTRUCTION FORMATS.

14. d. A digital computer has a memory unit of 64K×1664K \times 16 and a cache memory of 1K
words. The cache uses direct mapping with a block size of four words.
i) How many bits are there in the tag, index, block, and word fields of the address format?
ii) How many bits are there in each word of cache, and how are they divided into functions?
Include a valid bit.
iii) How many blocks can the cache accommodate?

15. e. Explain with neat diagrams the address selection for control memory.

16. a. The logical address space in a computer system consists of 128 segments. Each segment
can have up to 32 pages of 4K words each. Physical memory consists of 4K blocks of 4K
words each. Formulate the logical and physical address formats.

17. b. How is the Virtual address mapped into physical address? What are the different methods
of writing into cache?

18. g. What is SRAM and DRAM?

19. h. What is the difference between 2D and 2.5D memory organization?

20. What do you mean by virtual memory and how does paging help in implementing virtual
memory?

21. a. Discuss the different mapping techniques, relative merits, and demerits.

22. d. Discuss in cache memories and their differences.

23. h. RAM chip 4096×84096 \times 8 bits has two enable lines. How many pins are needed for
the integrated circuit package? Draw a block diagram and label all inputs and outputs of the
RAM. What is the main feature of random-access memory?

24. c. Define bus and memory transfer.

25. d. Define HIT and MISS ratio in memory with an example.

26. f. Differentiate between RISC and CISC.

27. g. List the differences between static RAM and dynamic RAM.

28. h. Define Virtual memory.

29. d. Consider a cache consisting of 256 blocks of 16 words each for a total of 4096 words.
Assume that the main memory is addressable by a 16-bit address and consists of 4K blocks.
How many bits are there in each of the TAG, SET, WORD fields for 2-way set associative
technique?

30. a. Discuss the Memory Hierarchy in a computer system with regard to Speed, Size, and Cost.

31. b. Write short notes on magnetic disk, magnetic tape, and optical disk.

32. d. Give classification of memory based on the method of access. Also, discuss the
construction and working of magnetic disk and various components of disk access time.

33. a. Consider a cache (M1) and memory (M2) hierarchy with the following characteristics:
M1: 16K words, 50 ns access time
M2: 1M words, 400 ns access time
 Assume 8-word cache blocks and set size 256 words with set associative mapping.
i) Show and explain the mapping between M2 and M1.
ii) Calculate the effective memory access time with cache hit ratio = 0.95.

34. b. Explain the direct mapping technique. Consider a digital computer with a memory unit of
64K×1664K \times 16 and cache memory of 1K words. The cache uses direct mapping with a
block size of four words.
i) How many bits are there in the tag, block, and word fields of the address format?
ii) How many blocks can the cache accommodate?

UNIT 5

1. What do you understand by Locality of Reference?

2. (a) Write short notes on:

i) Instruction pipeline.
ii) DMA-based data transfer.

3. (b) Explain the difference between vectored and non-vectored interrupt. Explain with
examples of each.

4. (a) Draw the block diagram of a DMA controller. Why are the read and write control lines in a
DMA controller bidirectional?

5. (b) Explain all the phases of an instruction cycle.

6. Explain the term cycle stealing.

7. j. What do you mean by a vector interrupt? Explain.

8. e. Draw and explain the block diagram of a typical DMA controller.

9. a. What do you mean by asynchronous data transfer? Explain strobe control and
handshaking mechanism.

10. b. Discuss the different modes of data transfer.

11. What do you understand by Locality of Reference?

12. What is the transfer rate of an eight-track magnetic tape whose speed is 120 inches per
second and whose density is 1600 bits per inch?

13. (b) Explain destination-initiated transfer using the handshaking method.

14. (a) Explain how the computer buses can be used to communicate with memory and I/O.
Also, draw the block diagram for CPU-IOP communication.

15. (b) What are the different methods of asynchronous data transfer? Explain in detail.

16. What is FO control method?

17. e. What is DMA? Describe how DMA is used to transfer data from peripherals.

18. a. Write down the difference between isolated I/O and memory-mapped I/O. Also, discuss
the advantages and disadvantages of isolated I/O and memory-mapped I/O.
19. b. i) Discuss the design of a typical input or output interface.
ii) What are interrupts? How are they handled?

20. (i) List down the functions performed by an Input/Output unit.

21. (j) Why does DMA get priority over the CPU when both request memory transfer?

22. (e) Define interrupt. Also, discuss different types of interrupt.

23. (a) With a neat schematic diagram, explain about DMA controller and its mode of data
transfer.

24. (b) Discuss the design of a typical input or output interface.

25. How does the control unit of a computer work?

26. Write a short note on locality of reference.

27. f. Define 2.5D memory organization.

28. g. In what way do synchronous and asynchronous serial modes of data transfer differ?

29. e. What are the basic differences between interrupt-initiated I/O and programmed I/O?
Explain in detail.

30. a. What do you mean by asynchronous data transfer? Explain strobe control and
handshaking mechanism.

31. b. Explain the various modes of data transfer and discuss the direct memory access mode in
detail. Also, explain how DMA is superior to other modes.