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VERILOG
INTRODUCTION
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History and Evolution of
Verilog
Gateway Design Automation introduced Verilog
1984 (Prabhu Goel and Phil Moorby)

Cadence Design Systems purchased Gateway

1989
Design Automation to
1990

1995 IEEE Standardized Verilog (IEEE 1364 -1995)

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Verilog
New features added and fixed problems with Verilog1995
2001 (IEEE 1364-2001 )

Minor Corrections and few new features added

(IEEE 1364-2005 )
2005

Super Subset of Verilog 2005 called System Verilog

2009
New features added to aid verification and modelling.
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Features
 Verilog is case sensitive.

 Most of the syntax is adopted from C language.

 Extension used by verilog files is “.v”

 Verilog can be used to model a digital circuit at Behaviour, Data Flow, Gate, Switch
and Structural level.

 Verilog supports additional features like Timing Checks,

User Defined Primitive(UDP) and Programming Language Interface(PLI).
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Comments
 There are two ways to provide comment
 Single Line Comment

Begins with double slashes (//)

 Block Comment

Comments are enclosed between /* and */

Examples
// This is a single line comment

/* This is block comment Statement 1

Statement 2
*/
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Identifiers

 Identifiers are name given to objects that can be referred in a design.

 An identifier can contain alphabets(a-z, A-Z), digits(0-1) and

special characters( _ , $).

 An identifier must begin with alphabet or underscore(_).

 Identifiers are case sensitive.

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Keywords
 In verilog few identifiers are reserved to define language constructs, they are
called as keywords.

 All keywords are in lower case.

Examples
• module
• always
• wire
• reg
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Number Specifications
 There are two types of number specifications
 Sized Numbers
 Unsized Numbers

 Size Numbers
Syntax : <size>’ <base> <number>
size: decimal value specifying number of bits to represent number.
base: base represents the format of the number. It can be
decimal (d or D) hexadecimal (h or H)
octal (o or O) binary (b or B)

number: specifying number is chosen base format.

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Number Specifications

 Unsized Numbers
 Numbers are written without size specification.
 Default number of bits depends upon the machine and simulator,
must be at least 32.
 Decimal is the default base format if not specified.

 Negative Numbers
 To represent a negative number, add minus sign(“-”) before the size
specification.
 Negative numbers are stored in 2’s Complement.
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Number Specifications
Examples
156 // Decimal number
‘hab3 // Hexadecimal number
‘o54 // Octal Number
5’b10110 // 5-bit binary number
12’h7f3 // 12-bit hexadecimal number
-4’d4 // 2’s complement of 4
-3’b010 // 2’s complement of 2
9’o342 // 9-bit octal number
8’h-af // Invalid syntax
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Number Specifications
 X or Z values
 X is used to represent unknown values.
 Z is used to represent high impedance.
 If the MSB bit of the number is x or z, then x or z is padded respectively to fill
the remaining most significant bits.
 If the MSB bit of the number is 1 or 0, then 0 is padded to fill the remaining most
significant bits.
 _ or ?
 _ is allowed anywhere in a number except at first character.
 _ are used to improve readability. Ignored by the compiler.
 ? is an alternative for z in verilog.
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Number Specifications
Examples
12’h14x // 12 bit hex number with 4 LSB bits X
11‘oz32 // 11 bit octal number with 5 MSB bits Z
5’b110 // 5 bit binary number with 2 MSB bits 0

16’b1011_0100_1100_1010
// 16 bit binary number with _ to improve readability.

10’h9?? // 10 bit hex number with 8 LSB bits Z

//Result is truncated to fit in 10 bits by ignoring MSB bits
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Module

 Module is the name given to a design unit in Verilog.

 Modules are used to provide a common functionality that can be used in others
design units.

 A module can be used as a component in other modules.

 Ports of the modules are used to communicate with other modules.

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Module
Syntax:
module module_name (port_list);
<port directions> port_names;
//Local declaration
//functionality of module endmodule //
no semicolon

Port_list : specify all ports used to communicate with the module

Port_direction : specify the direction of data flow.

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Module

 Verilog allows three types of ports

• input: Value can be read but cannot be assigned.

• output: Value can be assigned and can be read internally.

• inout: Bi-directional port, value is read or assigned depending upon the

control pin.
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Module
Example: Scalar Port

module xor_gate (a, b, c); // ”,” is used to separate

// port entries

input a, b ; output c; // Direction of each port

//Local declaration
//functionality of module

endmodule // no semicolon
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Module
Example: Vector Port

module fulladder (a, b, c, sum, carry);

//ports with same size are written together

input [3:0] a, b ; // [MSB : LSB]

input c;
output [3:0] sum;
output carry;
//Local declaration
//functionality of module
endmodule // no semicolon
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Module
Example: Vector Port - ANCI C Style

module fulladder ( input [3:0] a, b,

input c,
output [3:0] sum,
output carry);
//Local declaration
//functionality of module
endmodule // no semicolon
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Module
 The functionality of the module can be defined at four different levels of
abstraction

 Behavioral : In terms of algorithm without concern for hardware.

 Data Flow : In terms of how data flows between registers.

 Gate : In terms of Logic gates and their connections.

 Switch : In terms of switches and their connections.

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Data Types
 Verilog supports following data type
 Value Set
 Nets

 Registers

 Vectors

 Integer

 Real

 Time

 Arrays

 Parameters

 Strings
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Data Types
Value Set
 Verilog supports four basic values to model functionality of ahardware.

0 – Logic Zero 1 – Logic one

X – Unknown Logic Value
Z – High Impedance

Value X and Z are case insensitive

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Data Types
Nets
 Nets are used to represent connection between elements.
 A net should be continuously driven by some hardware.
 If there is no driver, the value of a net is Z.
 wire is most commonly use net type.
 Other net data types are wand, wor, tri etc.

Syntax: <net_type>[MSB: LSB] net_name; Default Value: Z

Examples: wire temp1; //1- bit net

wire [3:0] //4- bit net
temp2;
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Data Types
Registers
 Registers represent storage elements.
 It maintains value until a new value is assigned.
 Registers don’t require a constant driver
 Can be assigned only inside always or initial statements.
 It is used to store unsigned quantities.
Syntax: reg [MSB: LSB] reg_name; Default Value: X

Examples: reg temp1; //1-bit unsigned register

reg [3:0] temp2; //4-bit unsigned register
reg signed [11:0] temp3; //12-bit signed
register
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Data Types
Vectors
 Vector is used to represent a group of bits.
 Nets or reg data types can be declared as vectors.
Examples: wire temp1; //Scalar net
wire [0:7] temp2; //8 bit vector net
reg [3:0] temp3; //4 bit vector reg
Selecting part of a Vector

temp2[5]; //Selecting 5th bit of temp2

temp2[3:6]; //Selecting 3rd to 6th bit oftemp2
temp3[2:1]; //Selecting 2nd to 1st bit oftemp3
temp3[0:2]; //Invalid because order is different w.r.t declaration
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Data Types
Integer
 A type of register used to store integer values.
 The default size depends upon host-machine but should be at least 32 bits.
 It is used to store signed quantities.

Syntax: integer variable_name; Default Value: X

Examples:
integer int1, int2; // signed int1, int2
integer [3:0] int3; // Invalid syntax size not allowed
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Data Types
Time
 A type of register used to store simulation time.
 The size depends upon implementation but should be at least 64 bits.
 $time is system function which returns current simulation time.

Syntax: time variable_name; Default Value: X

Examples:
time a, b; //to be used inside initial or
a=$time; //always statement
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Data Types
Real
 A type of register used to store real values.
 Values can be stored in decimal or scientific notation.

Syntax: real variable_name; Default Value: 0

Examples:
real a, b; //Assigned inside initial or always block

a=3.14; //Decimal
b=5e12; //Scientific (5 x (10^12))
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Data Types
Arrays
 Arrays can be used to store same type of data together.

Syntax: <data_type> array_name <array_size>;

Declaration: integer num [0:15]; //1-D array

reg [7:0] data [31:0];
wire temp [1:10] [0:5]; //2-D array
reg [3:0] mem [0:7] [0:7];

Accessing: num [3]; //integer at location 3

data [12]; // 8-bit data at location 12
data [10] [2]; // 2nd bit of data at location10
mem [3] [2]; //data at 3rd row 2nd column
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Data Types
Parameters
 Constants are defined with keyword parameter.
 Parameter value for each module instance can be overridden at compile time.

Examples: parameter port_size = 8;

parameter [3:0] init = 4’b1010; //sized parameter
Local Parameters
 These are parameters whose value cannot be modified

Examples: localparam [1:0] idle=2’b00, state1=2’b01,

state2=2’b10, state3=2’b11;
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Data Types
Strings
 reg data type is used to store string data.
 Each character requires 8 bits for its storage.
 If reg size is more than size of string, zeros are padded on left of the string.
 If reg size is less, the leftmost bits of string are truncated.

Example:reg [5*8:1] value;

value = “hello”; //Inside initial or always blocks

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Port Data Type
Module Internal
net net
register or
net net
register or
net net

 output port can be of type register or net (Internally) and net(Externally).

 input port must be of type net (Internally) and can be register or net (Externally).
 inout port must be of type net both Internally as well as Externally.
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Port Data Type
Syntax: <port_direction> <port_data_type> port_name;

• Port_data_type can be register or net. It is wire by default.

Examples: input a; output b; output reg c;

output reg [3:0] d; output integer e; inout //wire by default
f; // output of type reg
input wire g; input [31:0] h; input
integer i; // output of type integer

// input of type wire

// vector input
// Invalid
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Continuous Assignment
 Continuous assignment are used to assign values to a net.
Syntax:
assign target = expression;
 This assignments are always active, i.e. any change on RHS side leads to

assignment of the target.

 An expression can be made up of a net, register or a function call.
 Target has to be of type net.

Examples: input a, b; //by default all ports

output c; //are of type net
assign c= a & b;
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Module Instance
 A module can be used as building block in other modules.

 An instance of a module is used to interact with a given module.

 Each module instance is independent, concurrent copy of a module.

Syntax: module_name instance_name(port_connection);

 Instance name used within a module should be unique.

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Module Instance
Example:

A0 A Sum
S
temp
A1 A S B Adder Carry
1 Adder D temp2 D
A2 B C

A3 C
my_design
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Positional Port Connection

module my_design (A0, A1, A2, A3, Sum, Carry); input A0, A1, A2, A3 ;
output Sum, Carry; wire temp1, temp2;

// module adder (A, B, C, S, D);

adder u0 (A1, A2, A3, temp1, temp2);
// A 1 A , A 2 B , A 3 C , temp1S, t e m p 2 D
adder u1 (A0, temp1, temp2, Sum, Carry);
//Order is important
endmodule
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Named Port Connection

module my_design(A0, A1, A2, A3, Sum, Carry); input A0, A1, A2, A3 ;
output Sum, Carry; wire temp1, temp2;
// module adder (A, B, C, S, D);
adder u0 (.A(A1), .B(A2), .C(A3), .S(temp1), .D(temp2)); //.formal ( Actual )
adder u1 (.A(A0) , .B(temp1), .C(temp2), .S(Sum), .D(Carry));

// Order is not important

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Primitives
 Verilog provides basic logic gates in terms of primitives.

 Primitives are instantiated like module.

 Since they are predefined in Verilog, they don’t require module definition.

 It is not compulsory to provide instance name to a primitive.

 There are three class of basic logic gates that verilog provides
and/or gates
 buf/not gates
 bufif/notif gates
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Primitives
 and/or gates
 They have one scalar output and multiple scalar inputs.
 The first port is output, other ports are input.
 The following and/or gates are available in verilog

and nand or nor xor xnor

 buf/not gates
 They have one scalar input and one or more scalar outputs.
 The last port is input, other ports are output.
 The following buf/not gates are available in verilog.

buf not
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Primitives
 bufif/notif gates
 These are buf/not gates with control input.
 The last port is control input, middle port is input and first port is output.
 The following bufif/notif gates are available in verilog
bufif1 bufif0 notif1 notif0
Examples:
and a1(out, ip1, ip2);
xor x1(out,ip1,ip2);
or o1(out, ip1, ip2, ip3);
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Primitives
More Examples:

buf (out1, out2, ip); not n1 (out1, ip); bufif1 b1(out, ip, ctrl); notif0 n2 (out, ip , ctrl);

// and primitive for vector ports

and u0 (out[0], ip1[0], ip2[0]);
and u1 (out[1], ip1[1], ip2[1]);
and u2 (out[2], ip1[2], ip2[2]);
and u3 (out[3], ip1[3], ip2[3]);

// Alternative solution
and u [0:3] (out, ip1, ip2);
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Operators
 Operators in verilog can be classified as following:

 On basis of number of operands

 Unary(One Operand)  Ternary(Three Operand)
 Binary(Two Operand)  Any Number

 On basis of functionality
 Arithmetic  Reduction
 Logical  Shift

 Relational  Concatenation

 Equality  Replication

 Bitwise  Conditional
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Arithmetic Operators
 Arithmetic operators are binary operators.
 Verilog provides following arithmetic operations
 + (Addition)

- (Subtraction)


 * (Multiplication)

 / (Division)

 % (Modulus)

 ** (Exponent)

 If any operand has X or Z value then result of entire expression would

be X.
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Arithmetic Operators
Examples:

A=4’b0010; B=4’b1101; C=4’b10x1; // vector reg/wire type

D=3; E=5; F=2; G=5; // integer type
A+B // evaluates to 4’b1111

A – B; // evaluates to 4’b0101
B – A; // evaluates to 4’b1011
A * B; // evaluates to 8’b00011010
D + E; // evaluates to 4’b1000
E / D; // evaluates to 1, i.e. truncates fractional part
E ** F; // evaluates to 25
E % G; // evaluates to 0 result takes sign of 1st operand
E % D; // evaluates to 2
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Logical Operators
 Logical operators are binary operators.
 Verilog provides following logical operations
 ! (Logical not)
 && (Logical and)

 || (Logical or)

 It returns single bit 1, 0 or X.

 If operand is non zero, it is equivalent to logic 1.
 If operand is zero, it is equivalent to logic 0.
 If operand is neither zero/non zero, it is equivalent to X.
It is normally treated as false condition by simulators.
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Relational Operators
 Relational operators are binary operators.
 Verilog provides following equality operations
> (greater than)


 < (less than)

 >= (greater than equal to)

 <= (less than equal to)

 It returns logic 1 if expression is true.

 It returns logic 0 if expression is false.
 It returns x if any operand contains X or Z.
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Equality Operators
 Equality operators are binary operators.
 Verilog provides following relation operations
 == (equality)

!= (inequality)


 === (case equality)

 !== (case inequality)

 Logical equality (==, !=) returns 0,1 or X.

 Case equality (===, !==) returns 0 or 1.
 Logical equality returns X if either operands has X or Z data.
 Case equality compares all bits including X and Z.
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Examples

A=4’b1010; B=4’b10x0; C=4’b10x0; D=4’b1100;

E =4’b0000; F=4’b1101;

A && D; // Returns 1
A || E; // Returns 1
(D==4’b1100) && (A==4’b1011); // Returns 0
F >= A; // Returns 1
D > B; // Returns X
B==C; // Returns X
D==E; // Returns 0
A!=F; // Returns 1
B===C; // Returns 1
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Bitwise Operators
 Verilog provides following bitwise operations
~ (bitwise negation)
 & (bitwise and)

 | (bitwise or)

 ^ (bitwise xor)

 ^~ or ~^ (bitwise xnor)

 It performs bit-by-bit operation on two operands.

 If one operand is shorter than other, zeros are padded to match the
length of larger operand.
 Return size is equal to that of larger operand.
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Reduction Operators
 Reduction operators are unary operators.
 Verilog provides following logical operations
& (reduction and)


 ~& (reduction nand)

 | (reduction or)

 ~| (reduction nor)

 ^ (reduction xor)

 ^~ or ~^ (reduction xnor)

 Reduction operators performs bitwise operation on a single vector.

 Reduction operators returns 1 bit result.
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Shift Operators
 Shift operators are binary operators.
 Verilog provides following shift operations
>> (right shift)


 << (left shift)

 >>> (arithmetic right shift)

 <<< (arithmetic left shift )

 Arithmetic shift works with signed data only. Arithmetic right shift pads
MSB bits.
 Arithmetic left shift works same as logical left shift.
 Shift by 1’bx or 1’bz result in X.
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Examples
reg [3:0] A=4’b0101, B=4’b1011, C=4’b1101;
reg signed [5:0] D =6’b101101;

A & B; // Returns 0001

A | C; // Returns 1101
& A; // Returns 0
^ B; // Returns 1
D >> 2; // Returns 001011
B << 3; // Returns 1000
C >>> 2; // Returns 0011
D >>> 3; // Returns 111101
A << 1’bx // Returns XXXX
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Concatenation Operators
 Concatenation operators can accept any number of operands.
 This operation provides mechanism to append multiple operands.

Syntax: {operand1, operand2, …, operandn};

Examples:
A=2’b01; // reg or wire data
B=3’b110;
C=2’b10;
{A, C}; //Result is 4’b0110
{B, A, C}; // Result is 7’b1100110
{A, 4’b0011, B[2], C}; // Result is 9’b010011110
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Replication Operators
 Replication operator are used to replicate an operand specified number of times.

Syntax: { replicate_times {operand} };

Examples:
A=2’b01; B=1’b1; // reg or wire data

{3 { A } }; //Result is 6’b010101
{B , {2{A}}, {2{3’B101}} }; // Result is 11’b1_01_01_101_101
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Conditional Operators
 Conditional operators are ternary operators.

Syntax: condition? true_expression : false_expession;

 If condition evaluates to true, then true_expression is returned else

false_expression is returned.
 Nesting of conditional operator is also allowed.

Example:
assign y1 = sel ? a : b;
assign y2 = (sel==2) ? in1 : in0 ;
assign y3 = sel1 ? (sel2? a : b) : (sel2? c : d); //Nested
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Stimulus (Test Bench)

 Test Benches are used to generate inputs and check response
of Design Under Test (DUT).

Test Bench
A A0
B A1
C A2
D
my_design
A3
E Sum
F Carry
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Test Bench
module tb ;
reg A, B, C, D;
wire E, F;
my_design U0(A, B, C, D, E, F); //Module Instance

initial begin // Provide values in initial block

A=1; B=0; C=0; D=1; #10 A=0;
#10 B=1; D=0; // Provide value after 10 time units
end
endmodule
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VERILOG LOOPS
AND
DELAYS
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Loops
 Verilog provides four type of loop statements
 while
 for

 repeat

 forever

 These loops can appear only inside always or initial block.

 Loop may contain delay statements.

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while
 while loop executes until the while expression is not true.

Syntax : while (<expression>)

begin statements; end

Example : integer count=0; Result

count=7
initial
while (count != 7)
#1 count= count + 1;
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for
 for loop executes till the condition is true.

Syntax for (initialization; condition check; updating )

begin statements;
end

Example integer count=0, i; Result

count=8
initial
for (i=0; i<=7; i= i + 1)
#1 count= count + 1;
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repeat
 Repeat loop executes the loop a fixed number of times

Syntax repeat (<no of times>)

begin statements;
end

Example integer count=0; Result

count=10
initial
repeat(10)
#1 count= count + 1;
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forever
 forever is an infinite loop that executes without any condition

Syntax forever begin

statements;
end

Example reg clock=0;

initial
forever #5 clock= ~clock;
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Block Statements

 Block statements are used to group multiple statements together.

 There are two type of Block Statements

 Sequential Blocks
 Parallel Blocks

 Sequential Blocks:
o begin and end keywords are used to group statements.
o Statements are executed in the order they are specified.
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Block Statements
 Parallel Blocks:
o fork and join keywords are used to group statements.
o Ordering of statements is controlled by delay or event control
assigned to each statement.

 Sequential blocks can be used for synthesis and simulation.

 Parallel blocks can only be used for simulation.

 Nesting of Block statements is allowed.

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Block Statements
• Example: Sequential Block

integer a=0, b=0, c=0, d=0, e=0;

initial
// Sequential block
begin
a=5; // a=5 occurs at time 0
#3 b=7; // b=7 occurs at time 3
#5 c=4; // c=4 occurs at time 8
#8 d=10; // d=10 occurs at time 16
#2 e=9; // e=9 occurs at time 18
end
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Block Statements
• Example: Parallel Block

integer a=0, b=0, c=0, d=0, e=0;

initial
fork // Parallel block
a=5; // a=5 occurs at time 0
#3 b=7; // e=9 occurs at time 2
#5 c=4; // b=7 occurs at time 3
#8 d=10; // c=4 occurs at time 5
#2 e=9; // d=10 occurs at time 8
join
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Nested Block Statements
Example1
integer a=0, b=0, c=0, d=0, e=0;
initial //sequential Block
begin a=5; // a=5 occurs at time 0
#5 b=7; // b=7 occurs at time 5
#6 c=4; // c=4 occurs at time 11
fork #1 a=9; // a=9 occurs at time 12
#4 d=3; // d=3 occurs at time 15
#5 c=8; // c=8 occurs at time 16
join //Parallel Block
#8 d=10; // d=10 occurs at time 24
#2 e=9; // e=9 occurs at time 26
end
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Example2
integer a=0, b=0, c=0, d=0, e=0;
initial
fork //Parallel Block
a=2; // a=2 occurs at time 0
#6 b=7; // a=9 occurs at time 1
#3 c=4; // e=9 occurs at time 2
begin //Sequential Block // c=4 occurs at time 3
#1 a=9; // d=3 occurs at time 5
#4 d=3; // b=7 occurs at time 6
#5 c=1; end // d=10 occurs at time 9
#9 d=10; // c=1 occurs at time 10
#2 e=9;
join
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Named Block
 Verilog allows giving names to block statements. These block are
called named blocks.

 Local variables can be declared for named blocks.

 Variables in a named block can be accessed by using hierarchical name

referencing.

 It is possible to stop execution (disable) of named blocks from

within the same block or different block.
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Named Block
Declaration example:
initial
begin : block1
integer count; //count variable local to block1
statements;
end
initial
begin : block2
reg a; // a variable local to block2
statements;
end
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Named Block
Example1:
initial
begin : block1
integer count; //count variable local to block1
count=0;
forever
begin
#5 count = count + 1;
if (count==8) disable block1;
end
end
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Named Block
Example2:

integer count=0, a=0, b=0;

initial
initial begin
begin : block1 a=3;
b=2; #5 a=7;
forever #4 a=2;
begin #2 disable block1;
#1 count = count + 1; #3 a=9;
end end
end
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Named Block
Example3:

integer count=0, a=0, b=0;

initial initial
begin begin
b=2; a=3;
forever #5 a=7;
begin : block1 #4 a=2;
#1 count = count + 1;
end
end
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Named Block
Example4:

integer count=0, a=0, b=0;

initial initial
begin begin
b=2; a=3;
begin: block1 #5 a=7;
forever #1 count = count +1; #4 a=2;
end #2 #2 disable block1;
b=4; #3 a=9;
end end
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Named Block
Example5:

integer count=0, a=0, b=0;

initial
initial
begin
begin : block2
a=3;
b=2;
#5 a=7;
begin: block1
#4 a=2;
forever #1 count = count +1;
#2 disable
end
block2.block1;
end
#3 a=9;
end
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Continuous Assignment Delays

 Continuous assignment delays are used to delay assignment
of net by specified time.

 There are three ways for assigning delay in Continuous assignment

 Regular Assignment Delay
 Implicit Continuous Assignment Delay

 Net Declaration Delay

 Regular Assignment Delay

wire c;
assign #10 c = a & b;
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Continuous Assignment Delays

 Implicit Continuous Assignment Delay

wire #10 c = a & b;

 Net Declaration Delay

wire #10 c; assign c = a&b;

 All three ways of assigning delay gives same result.

 These delays are inertial in nature and are used to model a digital circuit.
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Procedural Timing Controls

 The time at which the Procedural Statements has to be executed
can be controlled with help of Procedural Timing control.

 There are three type of Procedural Timing Controls

 Delay based Timing control
 Event based timing control

 Level Sensitive Timing control

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Delay Based Timing Control

 There are three type of Delay based Timing Controls

 Regular delay control
 Intra assignment delay control

 Zero Delay control

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Regular Delay Control

 In Regular delay control, the execution of statement is delayed
by a specified time.

 First delay is performed and then register is updated with the value
at current time.

 Any event on the sensitivity list is ignored till the all the delays
are executed.

 Both Blocking and Non-Blocking shows the similar behavior with

regular delay.
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Regular Delay Control

Declaration example:
parameter m=5;
integer a=0, b=0, count=0;
initial
begin
a=0;
#10 a=5;
#m b=2; //Delay specified by parameter
#b count= count + 1;
#(4:5:8) b=4; //Min, Typ and Max delay
end
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Regular Delay Control
Example1:module delay(input signed [31:0] a, output
integer b);
always @ (a)
#3 b=a; Race Condition
endmodule
a 2 5 2 7 8 1 6 9

b 5 7 8 1 9

0 2 3 6 7 9 12 15 16 19 21 22
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Regular Delay Control
Example2:module delay(input signed [31:0] a, output
integer b);
always @ (a)
#3 b<=a;
endmodule
a 2 5 2 7 8 1 6 9

b 5 7 8 1 9

0 2 3 6 7 9 12 15 16 19 21 22
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Intra Assignment Delay Control

 In Intra assignment delay control, the assignment of statement is

delayed by a specified time.

 Current values are read and are assigned to the register after specified
delay.

 Any event on the sensitivity list is ignored till the all the delays are
executed for blocking statement.

 Blocking and Non-Blocking does not show same behavior with this type
of delay.
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Intra Assignment Delay Control

Declaration example:
integer x=0, y=0;
initial
begin
x=2;
y=#4 x;
//intra Assignment Delay
// For blocking assignment it is equivalent to
// temp=x;
// #4 y=temp;
end
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Intra Assignment Delay Control

Example1:module delay(input signed [31:0] a, output
integer b);
always @ (a)
b= #3 a;
endmodule
a 2 5 2 7 8 1 6 9

b 2 8 1 6

0 2 3 6 7 12 15 16 19 21 22
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Intra Assignment Delay Control

Example2:module delay(input signed [31:0] a, output
integer b);
always @ (a) Transport
b<= #3 a; Delay
a endmodule
2 5 2 7 8 1 6 9

b 2 5 2 7 8 1 6 9

0 2 3 6 7 12 16 19 21
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Zero Delay Control

 Procedural statements in multiple always/initial block are
evaluated at same time.

 In such a case the order of execution of the statement is non-

deterministic.

 Zero delay is a method to ensure that a statement is

executed at the last.

 If there are multiple zero delay statements then order

between then is non-deterministic.
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Zero Delay Control

Example:
integer x, y;
initial
begin
x=0; y=0;
end
initial
begin
#0 x=1; y=2; //#0 ensures this executes at last
end
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Event Based Timing Control

 Change in value of a variable is called a event.

 Events can be used to trigger execution of statements or

block of statements.

 There are three types of Event based Timing Control

 Regular Event control
 Named Event control

 Event OR control
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Regular Event Control

 @ is used to specify event
 control.
Statements are executed if variable changes or posedge (positive
transition) or negedge (negative transition ) occur on a variable.
@ (clk) q=d; //executed whenever clk changes

@ (posedge clk) q=d; //executed whenever positive transition occurs on clk

//Delays execution till posedge occurs on clock
@ (negedge clk) q=d; //executed whenever negative transition occurs on clk

q= @(posedge clk) d; //value is read immediately and assigned after

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Named Event Control

 Named event allows user to declare event and trigger that event.
integer a=0, count=0;
event myevent;
initial
begin always @ (myevent)
a=4; begin
#3 ->myevent; count= count + 1;
// -> is used to trigger event myevent end
#2 count=6;
#4 ->myevent;
end
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Event OR Control
 In may be a requirement that transition on one or more variable may
trigger execution of statement or block of statements.

 This is expressed as OR of events also know as sensitivity list.

 Sensitivity list can also be specified with help of , instead of

always @ (posedge clk, posedge

always@(d or en)
rst)
begin
begin
if (en) q=d;
if (rst) q<=0;
end
else q<=d;
end
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Level sensitive Timing Control

 Level sensitive control waits for a condition to be true before a statement
or block of statements is executed.
 wait keyword is used to provide level sensitive control.

integer count=0;

always
wait (Enable)
#5 count= count + 1;
 Enable is monitored continuously, if it is 0 then statement is not
executed. If it is 1 then count is incremented by 1 after 5 time units.
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Conditional Statement
 Conditional statements are used to perform some task based on
certain condition.

 if and else keywords are used for conditional statements.

Syntax1: if(<Expression>) begin true_statements; end

 Expression is considered as true if it evaluates to a non-zero value.

 Expression is considered as false if it evaluates to a zero or

ambiguous(X) value.
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Conditional Statement
• Syntax2: True or False
if (<Expression>) begin true_statements; end
else
begin false_statements; end

begin and end are optional if there is only one statement.

If expression evaluates to true, true_statements are executed else

false_statements are executed
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Conditional Statement
Syntax3: Nested if-else

if (<Expression1>) begin true_statements1; end

else if (<Expression2>) begin true_statements2; end

else if (<Expression3>) begin true_statements3; end

else begin default_statements end;

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Conditional Statement

Example: Xor Gate

always @ (a, b)
begin
if (a==b)
c=0;
else
c=1;
end
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Multiway Branching
 Verilog provides case statement which tests whether
expression matches one of the multiple alternatives.
Syntax: case (<expression>)
alternative1 : begin statements1; end
alternative2 : begin statements2; end
alternative3 : begin statements3; end
……
default : begin default statements; end
endcase

 The expression is compared to the alternatives in the order

they are written.
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Multiway Branching
 Statements corresponding to first alternative that matches the
expression are executed.

 Incase no match is found, default statement is executed.

 default statement is optional. Default statement can written in any

where, it is always the last alternative expression is compared to.

 Nesting of case statements is allowed.

 begin and end keyword is optional if there is only one

statement to be executed for given alternative.
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Multiway Branching
Example1: Multiplexer
always @ (*) //all RHS variable covered in sensitivity list
case(sel)
2’b00: out=a;
2’b01: out=b;
2’b10: out=c;
2’b11: out=d;
default: $display(“Invalid selection”);
endcase
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Multiway Branching
Example2
always @ (*) //all RHS variable covered in
sensitivity list
case(sel)
2’b00: out=a;
2’b01: out=b;
default: $display(“Invalid selection”);
2’b01: out=c;
2’b11: out=d;
endcase
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Multiway Branching
Example3 always @ (*)
case(sel)
2’b00: out=a; 2’b01: out=b;
2’b10: out=c; 2’b11: out=d;
2’b0x, 2’bx0, 2’b1x, 2’bx1, 2’bzx, 2’bxz,
2’bxx:
begin out=0; $display(“sel contains X”); end
2’b0z, 2’bz0, 2’b1z, 2’bz1, 2’bzz:
begin out=0; $display(“sel contains Z”); end
default: $display(“unspecified input”);
endcase
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case, casez, casex

 case: In a normal case statement, valid inputs are 0, 1, X and Z. The
expression and alternatives are compared bit wise bit including X and Z.

 casez: In casez, valid inputs are 0, 1 and X. It treats Z or ? present in

expression or alternatives as don’t cares.

 casex: In casex, valid inputs are 0 and 1. It treats X, Z or ? present in

expression or alternatives as don’t cares.
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casez
Example: casez
always @ (*) //all RHS variable covered in sensitivity list
casez(sel)
2’b0?: out=a;
2’b0x: out=b;
2’b10: out=c;
2’b11: out=d;
default: out=e;
endcase
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casex
Example: casex
always @ (*) //all RHS variable covered in sensitivity list
casex(sel)
2’bx0: out=a;
2’b00: out=b;
2’b1?: out=c;
2’b11: out=d;
default: out=e;
endcase