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Vlsi Lab - I Experiment1

The experiment aims to understand the properties and characteristics of NMOS transistors using Cadence Virtuoso. The procedure involves creating a schematic, connecting components, and performing DC analysis to observe input and output characteristics. The results include various plots illustrating the relationship between drain current and gate/source voltages.

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talaganineeraj
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16 views4 pages

Vlsi Lab - I Experiment1

The experiment aims to understand the properties and characteristics of NMOS transistors using Cadence Virtuoso. The procedure involves creating a schematic, connecting components, and performing DC analysis to observe input and output characteristics. The results include various plots illustrating the relationship between drain current and gate/source voltages.

Uploaded by

talaganineeraj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment: 1

AIM: To understand the properties and characteristics of NMOS.

Tool Used: Cadence Virtuoso

Theory:
NMOS transistors are manufactured using N-type semiconductor materials. The structure of a
transistor consists of a metal gate separated from the semiconductor by an insulating oxide layer.
Its full name, N-Metal-Oxide-Semiconductor, reflects its structure and composition. This
transistor relies on the movement of electrons (carriers in N-type materials) to conduct current.
An NMOS transistor operates in different regions (Cutoff, Triode, and Saturation) based on the
applied Gate-to-Source Voltage (VGS) and Drain-to-Source Voltage (VDS).

Circuit Design:

Figure 1. NMOS Schematic

Procedure:
1. To open Cadence Virtuoso and launch the Schematic Editor Commands.
1. csh
2. source /home/install/cshrc
3. Virtuoso &
2. Create a new schematic cell (e.g., "NMOS_Characteristics").
3. File -> new -> library (give the name of the library) -> Attach to an existing technology.
4. Select the gpdk180, then OK.
5. File -> new -> cellview (give name to cellview) -> OK.
6. From the Library Manager, add:
• NMOS transistor from the selected technology library (gpdk180).
• DC voltage sources (VGS, VDS) (analoglib).
• Ground (GND) (analoglib).
7. Connect the circuit as follows:
• Drain to VDS source.
• Gate to VGS source.
• Source to GND.
8. Save and check for Design Rule Check (DRC) violations.
For Simulation
1. Open Analog Design Environment (ADE-L).
2. Setup DC Analysis:
• Sweep VGS (0V to VDD) at a fixed VDS (for input characteristics).
• Sweep VDS (0V to VDD) at a fixed VGS (for output characteristics).
For parametric Analysis
Open Tool -> parametric Analysis -> Add Variable -> start and stop time -> step size
• Sweep VGS (0V to VDD) for multiple VDS values (for input characteristics).
• Sweep VDS (0V to VDD) for multiple VGS values (for output characteristics).
3. Set up Probes: Measure Drain Current (ID).
4. Run the Simulation.

Output Waveform of NMOS:

Figure 2(a). Plot ID vs. VGS (Input Characteristics).


Figure 2(b). Plot ID vs. VDS (output Characteristics).

Figure 3(a). Plot ID vs. VGS (Input Characteristics for multiple VDS values).
Figure 3(b). ID vs. VDS (Output Characteristics for multiple VGS values).

Result: we Analysed the input and output characteristics of NMOS.

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