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Lab Manual

This lab manual outlines the VLSI Laboratory course for B. Tech (ECE) 4th semester students, detailing practical experiments scheduled from January to June 2025. The first experiment focuses on understanding the properties and characteristics of NMOS transistors using Cadence Virtuoso, including circuit design, simulation procedures, and analysis of input and output characteristics. The manual includes a structured approach to conducting experiments, recording results, and ensuring design compliance.

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talaganineeraj
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10 views6 pages

Lab Manual

This lab manual outlines the VLSI Laboratory course for B. Tech (ECE) 4th semester students, detailing practical experiments scheduled from January to June 2025. The first experiment focuses on understanding the properties and characteristics of NMOS transistors using Cadence Virtuoso, including circuit design, simulation procedures, and analysis of input and output characteristics. The manual includes a structured approach to conducting experiments, recording results, and ensuring design compliance.

Uploaded by

talaganineeraj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LAB MANUAL

of
VLSI LABORATORY-1

B. TECH (ECE) 4th SEMESTER

SUBJECT CODE – ECDC-0238

SUBMITTED BY: SUBMITTED TO:


Name: T Neeraj Name: Ashish Raman
Roll Number: 23118028
GROUP: G4

DEPARTMENT OF ELECTRONICS AND COMMUNICATION


DR. B.R. AMBEDKAR NATIONAL INSTITUTE OF TECHNOLOGY
JALANDHAR

COURSE CODE: ECDC-0238


COURSE TITLE: VLSI LABORATORY

LAB PRACTICALS (JAN-JUNE 2025)

S. No. WEEK No. NAME OF PRACTICAL SIGNATURE


To understand the properties and characteristics of NMOS
1. WEEK 1
2. WEEK 2
3. WEEK 3

4. WEEK 4
5. WEEK 5

6. WEEK 6

7. WEEK 7

8. WEEK 8
9. WEEK 9

10. WEEK 10

11. WEEK 11

12. WEEK 12

13. WEEK 13
Experiment: 1
AIM: To understand the properties and characteristics of NMOS.

Tool Used: Cadence Virtuoso

Theory:
NMOS transistors are manufactured using N-type semiconductor materials. The structure of a
transistor consists of a metal gate separated from the semiconductor by an insulating oxide layer.
Its full name, N-Metal-Oxide-Semiconductor, reflects its structure and composition. This
transistor relies on the movement of electrons (carriers in N-type materials) to conduct current.
An NMOS transistor operates in different regions (Cutoff, Triode, and Saturation) based on the
applied Gate-to-Source Voltage (VGS) and Drain-to-Source Voltage (VDS).

Circuit Design:

Figure 1. NMOS Schematic

Procedure:
1. To open Cadence Virtuoso and launch the Schematic Editor Commands.
1. csh
2. source /home/install/cshrc
3. Virtuoso &
2. Create a new schematic cell (e.g., "NMOS_Characteristics").
3. File -> new -> library (give the name of the library) -> Attach to an existing technology.
4. Select the gpdk180, then OK.
5. File -> new -> cellview (give name to cellview) -> OK.
6. From the Library Manager, add:
 NMOS transistor from the selected technology library (gpdk180).
 DC voltage sources (VGS, VDS) (analoglib).
 Ground (GND) (analoglib).
7. Connect the circuit as follows:
 Drain to VDS source.
 Gate to VGS source.
 Source to GND.
8. Save and check for Design Rule Check (DRC) violations.
For Simulation
1. Open Analog Design Environment (ADE-L).
2. Setup DC Analysis:
 Sweep VGS (0V to VDD) at a fixed VDS (for input characteristics).
 Sweep VDS (0V to VDD) at a fixed VGS (for output characteristics).
For parametric Analysis
Open Tool -> parametric Analysis -> Add Variable -> start and stop time -> step size
 Sweep VGS (0V to VDD) for multiple VDS values (for input characteristics).
 Sweep VDS (0V to VDD) for multiple VGS values (for output characteristics).
3. Set up Probes: Measure Drain Current (ID).
4. Run the Simulation.

Output Waveform of NMOS:

Figure 2(a). Plot ID vs. VGS (Input Characteristics).


Figure 2(b). Plot ID vs. VDS (output Characteristics).

Figure 3(a). Plot ID vs. VGS (Input Characteristics for multiple VDS
values).
Figure 3(b). ID vs. VDS (Output Characteristics for multiple VGS values).

Result: we Analysed the input and output characteristics of NMOS.

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