CS-2006 : Computer Organisation & School of Computer Engineering, SPRING

Architecture (COA) KIIT Deemed to be University, Bhubaneswar 2024

CONTROL UNIT
(Hardwired Unit and Micro-programmed Control Unit)
Sem: 4th Section (s): COA-CSE19, COA-CSE34 Faculty: Prof. Anil Kumar Swain

Lecturer Summary
1. Introduction to control unit
2. Hardwired control unit
3. Microprogrammed control unit

1 Introduction
 In computer organization and architecture, the control unit is a fundamental component
responsible for directing and coordinating the operations of the CPU (Central Processing Unit).
 It acts as the "brain" of the CPU, managing the execution of instructions and controlling the flow
of data within the processor.
 In other words, the unit which directs the operation of the processor & is a part of the CPU is
known as Control Unit. It generates control signals for the operations of a computer.
 Key Functions of Control Unit
For example,
 Instruction Interpretation: The control unit fetches instructions from memory, decodes
them, and determines the actions required to execute them.
 Instruction Decoding: Once fetched, the control unit decodes the instruction to understand
its operation code (opcode) and operands.
 Instruction Execution: After decoding, the control unit coordinates the execution of the
instruction by issuing commands to the appropriate components within the CPU, such as the
arithmetic logic unit (ALU), registers, and memory units.
 Sequencing: The control unit ensures that instructions are executed in the correct order,
following the program's logic. It manages the instruction pipeline and handles branch
instructions, jumps, and other control flow operations.
 Timing and Synchronization: It generates timing signals to synchronize the activities of
various components within the CPU, ensuring proper coordination and data integrity.
 Error Detection and Handling: The control unit may include mechanisms for detecting and
handling errors that occur during instruction execution, such as arithmetic overflow or
invalid memory accesses.
 Overall, the control unit plays a crucial role in orchestrating the operation of the CPU, ensuring
that instructions are executed correctly and efficiently according to the program's logic. It acts as
a bridge between the CPU's hardware components and the software instructions being executed.
 The actions needed to fetch and execute instructions are described in the previous sections. We
now examine how the processor generates the control signals that cause these actions to take
place in the correct sequence and at the right time. There are two basic approaches: hardwired
control and microprogrammed control.
 Types of Control Unit: There are two types of control units as follows. The two approaches
have trade-offs in terms of area, speed, and flexibility.
a) Hardwired control unit: This type of control unit relies on fixed circuitry to decode
instructions and generate control signals. Hardwired control units are simple and fast, but
they are inflexible and cannot be easily modified to support new instructions.
b) Micro-programmed control unit: This type of control unit uses a special program called
microcode stored in control memory to decode instructions and generate control signals.
Microprogrammed control units are more complex than hardwired control units, but they
Computer Organisation and Acrchitecture (COA) Lecture Notes of Prof. Anil Kumar Swain, KIIT-CSE Page 1 / 10
 are more flexible and can be easily modified to support new instructions by simply
updating the microcode.

1.1 Hardwired Control Unit

 Hardwired control refers to a control mechanism in a computer architecture where the control
signals are directly generated by combinational logic circuits. It typically involves a fixed
arrangement of logic gates and interconnections to produce the necessary control signals based
on the current state and inputs of the system. As a result, it’s known as a hardwired controller.
 These circuits are permanently designed and configured during the hardware design phase and
cannot be changed or reconfigured during operation.
 The control hardware can be viewed as a finite state machine (FSM):
 It changes from one state to another in every clock cycle depending on the contents of the
instruction register, the condition codes and the external inputs.
 The output of the state machine is control signal.
 The general hardwired control unit organization is shown below:

(Detailed block diagram of hardware control unit)

 Description of the key components required for hardwired control unit organization for the
generation of control signals are as follows:
i. Control Step Counter: It is used to keep track of the control step we are currently in.
 Let k is the maximum number of control steps required for implementing any
instruction in the CPU.
 Then size of the step counter is n=log2 k bits. In simpler terms, it indicates how many
bits are needed to uniquely identify one step.
ii. Step Counter Decoder: It feeds an n x 2n decoder to generate n control steps T1, T2, T3, ….
Tn.
iii. Instruction Register: It stores instructions fetched from the memory unit.
iv. Instruction Decoder: It is used to decode opcode of IR to generate a signal for each
instruction. The output of instruction decoder consists of a separate line for each machine
instruction.
 If the size of the instruction register is m, then an m x 2m decoder is required to to
select one of the instruction INS1, INS2, INS3,…,INSm, based on the value of IR.
v. Encoder: This is a combinational circuit that generates the required control outputs/signals
like Yin, PCout, ADD, END and so on, depending on the state of all inputs.
vi. Condition Code Flag:
Computer Organisation and Acrchitecture (COA) Lecture Notes of Prof. Anil Kumar Swain, KIIT-CSE Page 2 / 10
 vii. External Input Signals, such as MFC and interrupt requests may also  influence the
actions to be performed.
viii. END Signal is connected to a synchronous reset input of the control step counter.
 When END=1, in a control step, on the next rising edge of the clock the counter resets
0 and hence T1 becomes 1, i.e the control unit goes to T1 to start the fetch process.
ix. RUN Signal is ANDed with the clock to control the step counter clock.
 When RUN=0, the clock feeding the step counter will be 0 and the counter will not be
incremented i.e. stops counting. This is needed whenever the WMFC signal is issued
to cause the processor to wait for the reply from the memory. RUN signal control
waits until the memory finishes its operation and not go to the next control step.
 When RUN=1, the counter is incremented by one at the end of every clock cycle.

(Block diagram of hardware control unit)

 Generation of Control Signals - Designing

 For each signal, we need to find all the conditions that make it 1 by considering all the
control steps that require the signal to be 1 and derive the equation for it.
a. Example-1: Derive the equation for Zin signal considering only the instructions ADD (R3),
R1 and BRANCH Label for the single-bus CPU and design logic circuit for it
Solution
The sequence of control steps required for the single-bus CPU for the following instruction
ADD (R3), R1 and BRANCH L1 are as follows:

ADD (R3), R1 JUMP L2 or BRANCH L1 or BR L1

Step Action Step Action
1. PCout, MARin, Read, Select 4, ADD, Zin 1. PCout, MARin, Read, Select 4,
ADD, Zin
2. Zout, PCin, Yin, WMFC 2. Zout, PCin, Yin, WMFC
3. MDRout, IRin 3. MDRout, IRin
4. R3out, MARin, Read 4. Offset-field-of-IRout, Select Y,
ADD, Zin
5. R1out, Yin, WMFC 5. Zout, PCin, End
6. MDRout, Select Y, ADD, Zin
7. Zout, Rin, End

Computer Organisation and Acrchitecture (COA) Lecture Notes of Prof. Anil Kumar Swain, KIIT-CSE Page 3 / 10
  To derive the equation for Zin, we need to identify where Zin appears in each
instruction. In the case of the ADD instruction, it appears in step-1 and step-6, thus the
equation wrt ADD is T1.ADD + T6.ADD. Similarly, for the BR instruction, Zin
appears in step-1 and step-4 only, leading to the equation T1.BR + T4.BR. Combining
these, we can express it as follows:
Zin = T1.ADD + T6.ADD + T1.BR + T4.BR
= T1.ADD + T1.BR + T6.ADD + T4.BR
= T1 + T6.ADD + T4.BR (as this signal is asserted during time slot T1 for all
instructions )
So, now design a logic circuit for Zin = T1 + T6.ADD + T4.BR , which is as follows:

Assignment-Class-Work1: Derive the equation for Zout signal considering only the
instructions ADD (R3), R1 and BRANCH Label for the single-bus CPU and design logic
circuit for it
b. Example-2: Derive the equation for End signal considering only the instructions ADD (R3),
R1, BRANCH Label and BRANCH < 0 Label for the single-bus CPU and design logic
circuit for it
Solution
The sequence of control steps required for the single-bus CPU for the following instruction
ADD (R3), R1, BRANCH L1 and BRANCH < 0 are as follows:

ADD (R3), R1 JUMP L2 or BRANCH L1 or BR L1

Step Action Step Action
1. PCout, MARin, Read, Select 4, ADD, Zin 1. PCout, MARin, Read, Select 4,
ADD, Zin
2. Zout, PCin, Yin, WMFC 2. Zout, PCin, Yin, WMFC
3. MDRout, IRin 3. MDRout, IRin
4. R3out, MARin, Read 4. Offset-field-of-IRout, Select Y,
ADD, Zin
5. R1out, Yin, WMFC 5. Zout, PCin, End
6. MDRout, Select Y, ADD, Zin
7. Zout, Rin, End
.

Computer Organisation and Acrchitecture (COA) Lecture Notes of Prof. Anil Kumar Swain, KIIT-CSE Page 4 / 10
 BRANCH < 0 L1 or BRN L1
Step Action
1. PCout, MARin, Read, Select 4, ADD, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Offset-field-of-IRout, Select Y,ADD, Zin if N=0, then
End
5. Zout, PCin, End

 To derive the equation for End, we need to identify where End appears in each
instruction (in this case three instructions such as ADD, BR and BRN).
 In ADD, End appears in step-7, so we will write T7.ADD
 In BR (unconditional branching), End appears in step-5 and it will execute always, so
we can write T5.BR
 IN BRN, End appears in step-4 and step-5, but step-4 End will be executed if N=0 and
if N=1 then stp-5 End will be executed. So we can write T4.N.BRN + T5.N.BRN.
 Combiningly we can write as follows:
End = T7.ADD + T5.BR + T4.N.BRN + T5.N.BRN + …
= T7.ADD + T5.BR + (T4.N + T5.N).BRN + ….
 So, now design a logic circuit for End = T7.ADD + T5.BR + (T4.N + T5.N).BRN
+ …., which is as follows:

Assignment-Class-Work2: Derive the equation for WMFC signal considering only the
instructions ADD (R3), R1, BRANCH L1, BRANCH L1 < 0 for the single-bus CPU and
design logic circuit for it

 Advantages of Hardwired Control Unit

 Speed: Hardwired control unit achieves quick operation by utilizing combinational circuits
for signal generation. It is faster than micro-programmed control units.
 Delay Control: The delay in generating control signals is directly influenced by the number
of gates employed.
 Customizability: It can be adjusted to optimize for the fastest operational mode.

 Drawbacks/Limitations of Hardwired Control Unit

 Complexity: Increasing the number of required control signals adds complexity to the
design, necessitating additional encoders or decoders.

Computer Organisation and Acrchitecture (COA) Lecture Notes of Prof. Anil Kumar Swain, KIIT-CSE Page 5 / 10
  Rigidity: Modifying control signals is cumbersome as it involves rearranging hardware
circuitry.
 Feature Expansion Difficulty: Adding new features is challenging and time-consuming.
 Design Evaluation and Debugging: Identifying and rectifying flaws in the initial design is
difficult.
 Cost: Hardwired Control Units tend to be more expensive compared to other control unit
types.

1.2 Micro-programmed Control Unit:

 The Microprogrammed Control organization is implemented by using the programming
approach.
 Here, the micro-instructions are generated by a program similar to machine language programs,
called micro-program, stored in the control memory.
 The microinstruction specifies one or more micro-operations for the system. A sequence of
microinstructions constitutes a microprogram or micro-routine.
 An example of microinstructions for the instruction ADD (R3), R1 for single bus CPU
 The control steps required for the single-bus CPU for the instruction ADD (R3), R1 is as
follows:
ADD (R3), R1
Step Action
1. PCout, MARin, Read, Select 4, ADD, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, Select Y, ADD, Zin
7. Zout, Rin, End

 The following figure shows the CWs corresponding to the 7 steps of single bus architecture
for the instruction ADD (R3), R1 as shown above.

Microroutine

CW or
Microinstructions

Computer Organisation and Acrchitecture (COA) Lecture Notes of Prof. Anil Kumar Swain, KIIT-CSE Page 6 / 10
  The block diagram of micorprogrammed control unit organization is shown below:

(Micro-programmed control unit of a basic computer)

 The components of the micro-programmed control unit that work together are described
below:

(Block diagram of microprogrammed control unit)

i. Sequencer: It is used to determine the address sequence that is read from control memory.
Next address of the next microinstruction can be specified several way depending on the
sequencer input
ii. Control Memory Address Register or Control Address Register or MicroProgram
Counter (µPC) : It contains the address of the next microinstruction to be executed.It is
used to read the control words sequentially from the control store.
iii. Control Store or Memory : It is used to store the microprograms (a series of
microinstructions) that can not be altered, means it is stored in a ROM. The microroutines for
all instructions in the instruction set of a computer are stored in a spectial memory called the
control store.
iv. Control Memory Data Register or Control Data Register: It holds the present
microinstruction while the next address is computed & read from control memory. Allows
the execution of the microoperations specified by the control word simultaneously with
thegeneration of the next microinstruction. This requires two phase clock, with one clock
applied to address register and other to data register.
v. Control Word (CW): It is a word whose individual bits represent the various control
signals. Each Word in Control Memory contains within it a microinstruction.

Computer Organisation and Acrchitecture (COA) Lecture Notes of Prof. Anil Kumar Swain, KIIT-CSE Page 7 / 10
  Working of Microprogrammed Control unit
a) Address Sequencing
 Microinstructions are usually stored in groups where each group specifies a routine,
where each routine specifies how to carry out an instruction.
 Each routine must be able to branch to the next routine in the sequence.
 An initial address is loaded into the µPC when power is turned on; this is usually the
address of the first microinstruction in the instruction fetch routine. That is when a
new instruction is loaded into the IR, the output of “Starting and Branch address
generator” block is loaded into the microprogram counter.
 Next, the control unit must determine the effective address of the instruction.

b) Mapping
 The next step is to generate the microoperations that executed the instruction. This
involves taking the instruction’s opcode and transforming it into an address for the the
instruction’s microprogram in control memory. This process is called mapping.
 While microinstruction sequences are usually determined by incrementing the µPC
automatically by the clock, this is not always the case. If the processor’s control unit
can support subroutines in a microprogram, it will need an external register for storing
return addresses.

c) Conditional Branching:
 When the control unit is required to check the status of the condition codes or external
inputs to choose between alternative courses of action, it uses conditional branch
microinstructions.
 To allow implementation of a conditional branch, inputs to “Starting and Branch
address generator” block consists of the external inputs, condition codes and the
contents of the instruction register.
 The microprogrammed counter (µPC) does not increment in the following situation:
- When a new instruction is loaded into IR
- When a branch micro instruction is encountered and the branch condition is
satisfied.
- When an End microinstruction is encountered.

 Microinstructions (Horizontal Micro-organization Vs. Vertical Micro-organization)

 A straightforward way to structure microinstruction is to assign one bit position to each

control signal required in the CPU. This scheme is called as horizontal organization.

Computer Organisation and Acrchitecture (COA) Lecture Notes of Prof. Anil Kumar Swain, KIIT-CSE Page 8 / 10
  Drawback: Assigning individual bits to each control signal results in long microinstructions
because the number of required signals is usually large.
 The length of the micro-instructions can be reduced easily, because most signals are not
needed simultaneously and many signals are mutually exclusive
 Highly encoded schemes that use compact codes to specify only a small number of control
functions in each micro-instruction are referred to as vertical organization.
 Difference
Horizontal Micro-organization Vertical Micro-organization
 Minimally encoded scheme in which  Highly encoded schemes that use compact
many resources can be controlled with a codes to specify only a small number of
single micro-instruction, is called a control functions in each micro-instruction
horizontal organization. are referred to as vertical organization.
 This scheme is useful when a higher  Vertical approach results in considerably
operating speed is desired and when the slower operating speeds because more
machine structure allows parallel use of micro-instructions are needed to perform
resources. the desired control functions.

1.2 Difference between Hardwired Control and

Sl. Attributes Hardwired Control Microprogrammed Control
No.
1 Speed Speed is fast Speed is slow
2 Cost of More costly Cheaper
Implementation
3 Flexibility Not flexible to More flexible to
accommodate new accommodate new system
system specification or specification or new
new instruction instruction sets.
redesign is required.
4 Ability to Difficult to handle Easier to handle complex
Handle complex instruction instruction sets
Complex sets
Instructions
5 Decoding Complex decoding and Easier decoding and
sequencing logic sequencing logic
6 Applications RISC Microprocessor CISC Microprocessor
7 Instruction set Small Large
of Size
8 Control Absent Present
Memory
9 Chip Area Less More
Required
10 Occurrence Occurrence of error is Occurrence of error is less
more

Computer Organisation and Acrchitecture (COA) Lecture Notes of Prof. Anil Kumar Swain, KIIT-CSE Page 9 / 10
2 Home Assignment
Q1. Write the sequence of control steps for following instructions using single bus CPU organization.
INS1: Add 10(R3),R4
INS2: Branch<0, L1
INS3: MUL –(R5),R5
and design the logic function for WMFC control signal with reference to above instructions i.e
INS1 to INS3. Draw the circuit diagram for hardwired control unit.

Q2. Write the logic function expression and design circuit for Zin, End, Add, MDRout, PCin control
signal with reference to above instructions i.e INS1 to INS3 for hardwired control unit.

Computer Organisation and Acrchitecture (COA) Lecture Notes of Prof. Anil Kumar Swain, KIIT-CSE Page 10 / 10