Mixed Analog-Digital Design Considerations in Deep

Submicron CMOS Technologies

By
Sey Bazarjani
A thesis submitted to the Faculty of Graduate Studies and
Research in partial fulllment of the requirements for the degree
of Doctor of Philosophy.
Ottawa-Carleton Institute for Electrical Engineering
Department of Electronics
Faculty of Engineering
Carleton University
Ottawa, Canada
24 July 1996
Sey S. Bazarjani 1996
The undersigned recommend to the Faculty of Graduate Studies and Research the
acceptance of the thesis
Mixed Analog-Digital Design Considerations in Deep Submicron CMOS Technologies
submitted by Seyfollah S. Bazarjani in partial fulllment of the requirements for the
degree of Doctor of Philosophy.
____________________________
Prof. Martin Snelgrove
Thesis Supervisor
____________________________
Prof. J.S. Wight
Chairman,
Department of Electronics
____________________________
Prof. Gabor Temes
External Examiner
Ottawa-Carleton Institute for Electrical Engineering
Department of Electronics
Faculty of Engineering
Carleton University
24 July 1996
Abstract
Higher speed and higher density are the main thrusts of CMOS technology and are
achieved by device miniaturization. In deep submicron geometries, the supply voltage is
scaled down to prevent reliability hazards such as oxide breakdown and hot carrier effects
and also to reduce energy per operation of digital circuits. Lowering the supply voltage
directly reduces the signal swing, which in turn makes the design of high-speed wide
dynamic range mixed-signal SC circuits a challenge. It is also desirable to implement SC
circuits in a standard digital CMOS process, where double-poly capacitors are not
available, because the driving forces behind the CMOS technologies are DRAMs and
microprocessors which do not require linear capacitors.
This thesis demonstrates that analog circuit design can track projected digital technology
until at least the year 2010. It addresses the design of low-voltage and high-speed SC
circuits and also explores the feasibility of using MOSFET capacitors in a linear SC
circuit. The thesis describes an experimental CMOS process implemented as a subset
of a m dual n
+
/p
+
poly gate process using natural MOSFETs. A experimental
SC sigma-delta modulator is presentedthe lowest supply voltage reported so far for SC
modulators. Also described is a high-speed fourth-order SC bandpass modulator
and a novel fourth-order double-sampled SC bandpass modulator together with their
experimental results. Finally, a fourth-order bandpass SC modulator designed in a
digital CMOS process using pMOSFET capacitors is described.
1 V
0.5 1 V
Acknowledgments
I wish to express my gratitude to my advisor Professor Martin Snelgrove for his support
and guidance during the course of my Ph.D. studies at Carleton University. I would also
like to thank the members of my doctoral committee, Professors Miles Copeland, Tad
Kwasniewski, Calvin Plett, and Garry Tarr for their advice.
It was a great pleasure to interact with members of my research group at Carleton
University. Special thanks are due to Omid Shoaei, for sharing his knowledge on sigma-
delta modulators through many technical discussions; Theo Varelas, for assisting me with
chip layout and testing; Luc Lussier and Philip Lauzon for laying out test boards; and
Alana Wirta, for helping me with administrative matters.
Most of all, I would like to thank my wife Jaleh for her love and companionship, my
daughter Anahid for her cheerfulness which is a source of inspiration for me, and my
mother for her endless support.
The nancial and technical support of Nortel is gratefully acknowledged. I owe thanks to
my past and present management at Nortel for instituting a research agreement for me. In
particular, I am grateful to, Michael Krause, David Simmons, Kathy Howlett, Leonard
McCready, Don Treen, David Agnew, David Lynch, and Jack Dyment. Thanks also to
Robin Collins, microsurgeon at Nortel, for chip microsurgery and microphotographs.
i
Table of Contents
Abstract
Acknowledgments
Table of Contents .................................................................................................................................... i
List of Figures ....................................................................................................................................... iv
List of Tables ........................................................................................................................................ ix
List of Abbreviations ............................................................................................................................. x
List of Symbols .................................................................................................................................... xii
1 Chapter 1 Introduction 1
1.1 Motivation ................................................................................................................................. 1
1.2 Thesis Objectives ....................................................................................................................... 2
1.3 Contributions ............................................................................................................................. 3
1.4 Thesis Outline ............................................................................................................................ 4
2 Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal
Circuits 6
2.1 Introduction ............................................................................................................................... 6
2.2 CMOS Scaling ........................................................................................................................... 7
2.2.1 CMOS Scaling in the Next Decade .............................................................................. 7
2.2.2 Vt Scaling Issues .......................................................................................................... 9
2.3 Low-Voltage Mixed-Signal Design ........................................................................................ 12
2.3.1 Limits on Digital CMOS Supply Voltage Scaling ..................................................... 13
2.3.2 Limits on Analog CMOS Supply Voltage Scaling .................................................... 15
2.3.3 Previous Work on Low-Voltage Digital Circuits ....................................................... 19
2.3.4 Previous Work on Low-Voltage Analog Circuits ...................................................... 20
2.3.4.1 Low-Voltage Active-RC Circuits ............................................................... 20
2.3.4.2 Low-Voltage Switched-Current Circuits .................................................... 21
2.3.4.3 Low-Voltage Switched-Capacitor Circuits ................................................. 22
2.3.5 Impact of Voltage Scaling on Power Dissipation of Mixed-Signal Circuits ............. 24
2.4 Oversampled Sigma-Delta Modulator Overview .................................................................... 28
2.4.1 Lowpass Sigma-Delta Modulators ............................................................................. 30
2.4.2 Bandpass Sigma-Delta Modulators ............................................................................ 31
ii
2.4.3 High-Speed SC Bandpass Sigma-Delta Modulator .................................................... 32
2.5 Analog Circuit Design in a Standard Digital CMOS Process ................................................. 34
2.5.1 SI Circuit Technique .................................................................................................. 35
2.5.2 High Performance Memory Cells ............................................................................... 39
2.5.3 Linear SC Circuit Techniques in a Digital CMOS Process ........................................ 41
2.6 A Comparative Study of SC and SI for Low-Voltage Applications ....................................... 46
2.7 Summary .................................................................................................................................. 48
3 Chapter 3 Low-Voltage SC Design with Low-Vt MOSFETs 50
3.1 A Low-Vt Process ................................................................................................................... 51
3.2 Circuit Technique for Vt Reduction ........................................................................................ 54
3.3 Low-Vt Transmission Gate Design for SC Circuits ................................................................ 57
3.4 Series Transmission Gate and Composite Switch ................................................................... 63
3.4.1 Series Transmission Gate Switch ............................................................................... 65
3.4.2 Composite Switch ....................................................................................................... 67
3.5 A 2.25 V Second-Order Sigma-Delta Modulator .................................................................... 70
3.5.1 Short-Channel MOSFETs .......................................................................................... 70
3.5.2 Short-Channel MOSFETs Layout Issues ................................................................... 72
3.5.3 Measured SNDR ......................................................................................................... 72
3.6 A 1 V First-Order Sigma-Delta Modulator ............................................................................. 73
3.6.1 1 V opamp .................................................................................................................. 74
3.6.2 Comparator ................................................................................................................. 75
3.6.3 Switches ...................................................................................................................... 76
3.6.4 Measured Results for the 1 V Sigma-Delta Modulator .............................................. 77
3.7 Summary .................................................................................................................................. 78
4 Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators
80
4.1 Modulator Architecture ........................................................................................................... 80
4.2 Half Delay SC Circuits ............................................................................................................ 83
4.3 Full Delay SC Circuits ............................................................................................................. 93
4.4 A SC Bandpass Sigma-Delta Modulator ............................................................................... 101
4.4.1 Sources of Error ........................................................................................................ 106
4.5 A Double-Sampled SC Bandpass Sigma-Delta Modulator ................................................... 111
4.5.1 Sources of Error ........................................................................................................ 113
iii
4.6 Implementation ...................................................................................................................... 117
4.7 Measurement Results ............................................................................................................. 125
4.7.1 Fourth-Order Bandpass Sigma-Delta Modulator ..................................................... 125
4.7.2 Double-Sampled Fourth-Order SC Bandpass Sigma-Delta Modulator ................... 127
4.8 Summary ................................................................................................................................ 129
5 Chapter 5 SC Bandpass Sigma-Delta Modulator Design In a Digital CMOS
Process 130
5.1 MOS Capacitor ...................................................................................................................... 130
5.2 Distortion in SC Amplifier Caused by Non-linear Capacitors .............................................. 136
5.3 A SC Delay Circuit Using pMOSFET Capacitors ................................................................ 139
5.4 A Fourth-Order SC Bandpass Sigma-Delta Modulator Using pMOSFET Capacitors ......... 141
5.4.1 Linear Charge Processor Viewpoint ......................................................................... 145
5.5 Summary ................................................................................................................................ 146
6 Chapter 6 Conclusions and Future Work 147
6.1 Summary ................................................................................................................................ 147
6.2 Conclusions ........................................................................................................................... 149
6.3 Future Work ........................................................................................................................... 149
Appendix A: Appendix A MOSFET Equations 151
Appendix B: Appendix B Natural MOSFET Characteristics 153
References 156
iv
List of Figures
Figure 2.1: A negative feedback Vt adjust circuit ..........................................................................................12
Figure 2.2: A basic CML inverter-buffer gate................................................................................................14
Figure 2.3: A fully differential CMOS Opamp ..............................................................................................15
Figure 2.4: Complementary transmission gate switch on-conductance for (a) VDD<2Vt, (b) VDD=2Vt, and
(c) VDD>2Vt .............................................................................................................................17
Figure 2.5: A simple current mirror cell .........................................................................................................18
Figure 2.6: An active-RC integrator ...............................................................................................................21
Figure 2.7: A non-inverting SC integrator and its associated 2-phase non-overlapping clock ......................22
Figure 2.8: A switched-opamp SC integrator .................................................................................................24
Figure 2.9: CMOS inverter .............................................................................................................................25
Figure 2.10: A block diagram of a SD modulator ..........................................................................................28
Figure 2.11: Equivalent linear system of Figure 2.10 ....................................................................................29
Figure 2.12: Pole/zero placement of (a) a first-order lowpass SD and (b) a second- order bandpass SD derived
by transformation......................................................................................................................32
Figure 2.13: A weighted current mirror..........................................................................................................36
Figure 2.14: A first generation memory cell ..................................................................................................36
Figure 2.15: First generation SI integrator .....................................................................................................37
Figure 2.16: Second generation SI memory cell ............................................................................................38
Figure 2.17: A second generation non-inverting lossless integrator ..............................................................38
Figure 2.18: Second generation damped integrator........................................................................................39
Figure 2.19: Regulated cascode memory cell.................................................................................................40
Figure 2.20: S2I memory cell .........................................................................................................................41
Figure 2.21: nMOSFET CV plot ....................................................................................................................42
Figure 2.22: A charge mirror cell ...................................................................................................................44
Figure 2.23: A SC building block...................................................................................................................45
Figure 2.24: The MOSFET SC branch...........................................................................................................45
Figure 2.25: A SC circuit using the MOSFET SC branch..............................................................................46
Figure 2.26: A two-stage pole-splitting opamp..............................................................................................48
Figure 3.1: Gate-substrate workfunction of nMOSFET and pMOSFET in an n+/p+ dual poly gate CMOS
process........................................................................................................................................52
Figure 3.2: Measured ID (A) and Gm (A/V) versus VGS (V) for natural nMOSFET...............................53
Figure 3.3: Measured |ID (A)| and Gm (A/V) versus VGS (V) for natural pMOSFET .............................53
Figure 3.4: Measured subthreshold characteristics of natural nMOSFET and pMOSFET............................54
v
Figure 3.5: Threshold voltage as a function of channel length.......................................................................55
Figure 3.6: Turned-off nMOSFET switch exhibiting (a) no punchthrough, (b) punchthrough due to short
channel length, and (c) punchthrough due to large drain to source potential ............................56
Figure 3.7: A non-inverting SC integrator......................................................................................................58
Figure 3.8: Equivalent circuit of Figure 3.7 during........................................................................................60
Figure 3.9: Equivalent circuit of Figure 3.7 during non-overlapping period .................................................62
Figure 3.10: Equivalent circuit of Figure 3.7 during......................................................................................63
Figure 3.11: Measured iDS vs. vG for an nMOSFET with Vt=130 mV and vS=0 (solid line) and vS=0.2 V
(dotted line) ................................................................................................................................64
Figure 3.12: Turned-off (a) nMOSFET and (b) pMOSFET switches ............................................................65
Figure 3.13: A series transmission gate switch ..............................................................................................66
Figure 3.14: Leakage off-current through an nMOSFET switch (dotted line) and a STG switch (solid line)
versus input voltage ...................................................................................................................66
Figure 3.15: On-conductance of the nMOSFET (dotted-line) and STG switch (solid-line) versus input
signal ..........................................................................................................................................67
Figure 3.16: A composite switch....................................................................................................................68
Figure 3.17: Simulated on-conductance for high-Vt TG switch (dashed-line), low-Vt series transmission gate
switch (dotted-line), and the composite switch (solid-line) versus input signal........................68
Figure 3.18: On-conductance for high-Vt TG switch (dashed-line), low-Vt TG switch (dotted-line), and the
composite switch (solid-line) versus input signal ......................................................................69
Figure 3.19: Leakage current for high-Vt TG switch (dashed-line), low-Vt TG switch (dotted-line), and the
composite switch (solid-line) versus input signal ......................................................................69
Figure 3.20: Drain current versus gate voltage for a 0.6 mm nMOSFET with vDS=0.1 V (solid line) and
vDS=2 V (dashed line)...............................................................................................................71
Figure 3.21: Drain off-current (vG=0) versus drain to source voltage for a 0.6 mm nMOSFET with vSB=0
(solid line) and vSB=0.5 V (dashed line)...................................................................................72
Figure 3.22: Measured SD modulator performance .......................................................................................73
Figure 3.23: A first-order SC SD modulator ..................................................................................................74
Figure 3.24: A two-stage pole-splitting opamp..............................................................................................75
Figure 3.25: Schematic of the comparator......................................................................................................76
Figure 3.26: Simulated transmission gate switch resistance as a function of input signal ............................77
Figure 3.27: Simulated off-current for the nMOSFET switch .......................................................................78
Figure 3.28: Chip die microphotograph..........................................................................................................78
Figure 3.29: Measured spectrum (Vip = 420 mVpp) .....................................................................................79
Figure 4.1: A fourth-order double resonator bandpass SD modulator ...........................................................81
vi
Figure 4.2: Histograms of output levels for the first (solid line) and the second (dashed line) resonator for a -
6 dB tone input...........................................................................................................................82
Figure 4.3: Simulated output spectrum of the fourth-order bandpass SD modulator in Figure 4.1 for a
sinusoidal input. .........................................................................................................................82
Figure 4.4: Resonator using delay cells..........................................................................................................83
Figure 4.5: (a) A SC half delay gain stage, (b) 2-phase non-overlapping clock, (c) input (dashed line) and
output (solid line) waveforms ....................................................................................................84
Figure 4.6: A single-ended equivalent circuit of Figure 4.5a during (a) and (b) phases ..............................85
Figure 4.7: Opamp in the closed-loop configuration during ..........................................................................86
Figure 4.8: A simple SC sample-and-hold circuit ..........................................................................................87
Figure 4.9: Bottom-plate sampling technique to eliminate signal dependent charge injection......................88
Figure 4.10: Fully differential bottom-plate sampling to cancel fixed charge injection and clock
feedthrough ................................................................................................................................89
Figure 4.11: Single-ended equivalent circuits of Figure 4.5a during (a) sampling phase, and (b) holding
phase ..........................................................................................................................................89
Figure 4.12: One capacitor sample-and-hold circuit ......................................................................................91
Figure 4.13: A simple cascade SC delay circuit .............................................................................................93
Figure 4.14: A SC delay gain stage ................................................................................................................94
Figure 4.15: A single-ended equivalent circuit of Figure 4.14 during (a) and (b) phases............................94
Figure 4.16: A double-sampled SC delay circuit............................................................................................97
Figure 4.17: A single-ended equivalent circuit of Figure 4.16 during (a) and (b) phases............................98
Figure 4.18: Two-path SC circuit and clock phases .....................................................................................100
Figure 4.19: Spectrum of the input signal (solid line) and the attenuated odd samples of the input signal
(dotted line) ..............................................................................................................................101
Figure 4.20: A SC resonator using two delay cells ......................................................................................102
Figure 4.21: A fourth-order SC bandpass sigma-delta modulator................................................................104
Figure 4.22: Worst case opamp loading for (a) bandpass SD of Figure 4.21 (b) bandpass SD modulator in
[Longo93] ................................................................................................................................105
Figure 4.23: Output spectrum from Eldo simulation....................................................................................105
Figure 4.24: Output spectrum of the fourth-order bandpass SD modulator with an opamp gain of 40 dB and
opamp input capacitance of Cin =2Cu.....................................................................................109
Figure 4.25: SNR loss versus OSR / HR0 from analytical result (solid line) and from simulation results (o
points). .....................................................................................................................................110
Figure 4.26: A double-sampled SC resonator...............................................................................................112
Figure 4.28: Output spectrum from Eldo simulation....................................................................................113
vii
Figure 4.27: A double-sampled SC fourth-order bandpass sigma-delta modulator .....................................114
Figure 4.29: Output spectrum of the double-sampled bandpass sigma-delta modulator with 1% capacitor
mismatch between the two paths. Note that the image power is 40 dB below the signal power. .
115
Figure 4.30: Chip microphotograph of the fourth-order SC bandpass sigma-delta modulator ....................117
Figure 4.31: Chip microphotograph of the fourth-order double-sampled SC bandpass sigma-delta
modulator .................................................................................................................................118
Figure 4.32: Transmission gate switch on-resistance vs. signal level ..........................................................120
Figure 4.33: Fully differential cascode opamp.............................................................................................121
Figure 4.34: Simulated open loop gain (solid line) and phase (dotted line) of the cascode opamp for 1 pF load
capacitance...............................................................................................................................122
Figure 4.35: Test structure for settling time simulation ..............................................................................123
Figure 4.36: Worst case settling time simulation in Eldo.............................................................................123
Figure 4.37: Fully differential comparator ...................................................................................................124
Figure 4.38: Measured output spectrum of the fourth-order bandpass sigma-delta modulator for an input
signal of 10 dB below full scale...............................................................................................126
Figure 4.39: Expanded view of the output spectrum around the notch. Note that the notch frequency is shifted
by about 500 kHz to the left (lower frequency) .......................................................................127
Figure 4.40: Measured output spectrum of the double-sampled fourth-order SC bandpass sigma-delta
modulator for an input signal of 10 dB below full scale. Note that image signal is about 39 dB
below the fundamental signal. .................................................................................................128
Figure 4.41: Expanded view of the output spectrum around the notch. Note that the notch frequency is shifted
by about 1 MHz. ......................................................................................................................128
Figure 5.1: Structure of (a) a MOS capacitor and (b) an nMOSFET transistor ...........................................131
Figure 5.2: Analytical C-V characteristics of an nMOSFET transistor........................................................132
Figure 5.3: Measured (solid line) and simulated (dashed line) C-V plot of an nMOSFET .........................134
Figure 5.4: Measured (solid line) and simulated (dashed line) C-V plot of a pMOSFET ...........................134
Figure 5.5: Simulated C-V characteristics of a low-Vt natural nMOSFET (dashed line) and a threshold
adjusted nMOSFET (solid line) ...............................................................................................136
Figure 5.6: A single-ended SC amplifier......................................................................................................137
Figure 5.7: SC delay cell using pMOSFET capacitors.................................................................................140
Figure 5.8: Output spectrum of the fully differential SC gain stage, Figure 5.7, during .............................141
Figure 5.9: Output spectrum of the fully differential SC unity gain stage, Figure 5.7, during f1................142
Figure 5.10: A fourth-order bandpass sigma-delta modulator using pMOSFET capacitors........................143
Figure 5.11: Output spectrum of the fourth-order SC bandpass sigma-delta modulator of Figure 5.10 for an
viii
input signal of 6dB below full scale ........................................................................................144
Figure 5.12: A fully differential cascode opamp..........................................................................................144
Figure B.1: Measured ID (A) and Gm (A/V) versus VGS (V) for natural nMOSFET ...........................154
Figure B.2: Measured |ID (A)| and Gm (A/V) versus VGS (V) for natural pMOSFET...........................154
Figure B.3: Measured nMOSFET IDS-VDS characteristics. IDS ~ (VGS-Vt)1.27 ....................................155
Figure B.4: Measured pMOSFET IDS-VDS characteristics. IDS ~ (VGS-Vt)1.32 ....................................155
ix
List of Tables
Table 1.1: SIA semiconductor technology roadmap ................................................................................ 1
Table 2.1: CMOS scaling schemes........................................................................................................... 8
Table 2.2: A guideline for CMOS scaling................................................................................................ 8
Table 3.1: On-resistance of switches with W=10mm............................................................................. 71
Table 3.2: Dimension of MOSFETs used in the opamp of Figure 3.24................................................. 74
Table 3.3: Simulated opamp performance for a 1 pF load capacitance.................................................. 75
Table 3.4: Transistor sizes for the comparator ....................................................................................... 76
Table 4.1: Some MOSFET parameters in HCMOS5a process............................................................. 118
Table 4.2: Target specification for the bandpass SD modulator .......................................................... 119
Table 4.3: Transistors sizes used in the opamp ................................................................................... 121
Table 4.4: Transistor sizes used in the CMFB circuit ......................................................................... 121
Table 4.5: Simulated characteristics of opamp for 1 pF load capacitance ........................................... 124
Table 4.6: Comparator transistor sizes ................................................................................................. 125
Table 5.1: nMOSFET capacitance voltage coefficients ....................................................................... 135
Table 5.2: pMOSFET capacitance voltage coefficients ....................................................................... 135
Table 5.3: Simulated characteristics of opamp for 1pF load capacitance ............................................ 145
x
List of Abbreviations
A/D Analog-to-Digital
ASIC Application Specic Integrated Circuit
BiCMOS Bipolar and Complementary Metal Oxide Semiconductor
CE Constant Electric Field
CML Current Mode Logic
CMOS Complementary Metal Oxide Semiconductor
CV Constant Voltage
DC Direct Current
DR Dynamic Range
DRAM Dynamic Random Access Memory
FE Forward Euler
harmonic distortion
IF Intermediate Frequency
LDI Lossless Discrete Integrator
LDD Lightly Doped Drain
LT Low Temperature
MOSFET Metal Oxide Semiconductor Field Effect Transistor
NTF Noise Transfer Function
nMOSFET n-channel Metal Oxide Semiconductor Field Effect Transistor
opamp operational amplier
Oversampling Ratio
OTA Operational Transconductance Amplier
HD
k
k
th
OSR
xi
pMOSFET p-channel Metal Oxide Semiconductor Field Effect Transistor
QCV Quasi-Constant Voltage
SC Switched-Capacitor
SCE Short-Channel Effect
SI Switched-Current
SNR Signal to Noise Ratio
SNDR Signal to Noise+Distortion Ratio
STF Signal Transfer Function
STG Series Transmission Gate
TG Transmission Gate
TTL Transistor-Transistor Logic
UGBW Unity-gain Bandwidth
VLSI Very Large Scale Integration
Sigma-Delta
xii
List of Symbols
Absolute value
A opamp DC gain
Gate-bulk capacitance of MOSFET
Gate-source capacitance of MOSFET
Specic gate capacitance of MOSFET
Conduction band edge
Silicon bandgap energy
Valence band edge
Quantization noise
Frequency in Hz
Center frequency
Sampling frequency
Drain-source conductance
MOSFET transconductance
-domain transfer function
-domain transfer function
Drain current
Input current
Output current
MOSFET subthreshold off-current
CMOS technology scaling factor
Boltzmans constant
C
gb
C
gs
C
ox
E
c
E
g
E
v
e
f
f
0
f
s
g
ds
g
m
H s ( ) s
H z ( ) z
I
ds
i
i
i
o
i
off
k
k
xiii
MOSFET channel length
Magnitude error frequency response
Acceptor impurity density
Subthreshold slope factor
Quantization noise in signal band
Fixed charge density
MOSFET drain-source on-resistance
MOSFET junction depth
Subthreshold swing factor
Sensitivity of to variation in
Clock period
Temperature
Delay time
Gate oxide thickness
Base-Emitter voltage
Power supply voltage
Flat-band voltage
Input common-mode voltage
Output common-mode voltage
MOSFET gate over-drive voltage (on-voltage)
MOSFET threshold voltage
nMOSFET threshold voltage
pMOSFET threshold voltage
RMS noise voltage
L
m ( )
N
A
n
n
0
Q

R
on
r
j
S
S
y
x
x y
T
T
t
D
t
ox
V
BE
V
DD
V
FB
V
icm
V
ocm
V
on
V
t
V
tn
V
tp
v
n
xiv
Drain voltage
Differential input voltage
Negative input voltage
Positive input voltage
Differential output voltage
Negative output voltage
Positive output voltage
Source voltage
MOSFET channel width
Sampled-data representation of delay ( )
Velocity saturation index
First-order voltage coefcient of capacitance
Second-order voltage coefcient of capacitance
MOSFET transconductance parameter ( )
Feedback factor
Oxide dielectric constant
Silicon dielectric constant
Bulk potential
Fermi potential
Metal-silicon work function difference
Clock phase
Thermal voltage
Body effect coefcient
Mobility
v
D
v
id
v
in
v
ip
v
od
v
on
v
op
v
S
W
z
1
z
1
e
jT
=

2
C
ox
W 2L =

ox

si

ms

n
n

xv
Electron mobility
Hole mobility
Phase error frequency response
Unity-gain bandwidth
Cut-off frequency ( )

p
( )

0
3dB
1
Chapter 1
Introduction
1.1 Motivation
Higher speed and higher density are the main benets of CMOS VLSI technology and are
achieved by shrinking the feature size of the MOSFET devices. In the past, Constant
Voltage (CV) scaling has been used for CMOS (down to m) to achieve higher
performance and to maintain supply voltage compatibility. However, as MOSFET
miniaturization reaches to deep submicron sizes ( m and below), supply voltage
scaling based on Quasi-Constant Voltage (QCV) scaling must be adopted to assure
reliability [Kakumu90]. Hot carrier effects and gate oxide breakdown are the two
important reliability factors determining how high power supply voltage can be. The
Semiconductor Industry Association (SIA) roadmap (Table 1.1) predicts a supply voltage
of V for semiconductors by the year 2010 [SIA94].
The move toward lower supply voltages is also fueled by low-power battery powered
portable devices [Thomas93]. An ideal power supply for a battery powered system is a
single-cell ( - ) off-the-shelf battery.
Year 1995 1998 2001 2004 2007 2010
Feature size (m) 0.35 0.25 0.18 0.13 0.1 0.07
Power supply voltage (V) 3.3 2.5 1.8 1.5 1.2 0.9
Table 1.1: SIA semiconductor technology roadmap
0.5
0.5
0.9
1.2 V 0.9 V
Chapter 1 Introduction 2
Integrated circuits are moving increasingly into the mixed-signal world where more parts
of a system are implemented on a single chip. Performance and density of digital circuits
are expected to follow the famous Moores lawachieving a 2X increase in circuit
density and a slower rate of (1.4-1.2)X increase in circuit speed every three years. Energy
per operation in digital circuits ( ) is also reduced due to supply voltage scaling in
deep submicron CMOS. However, lowering the supply voltage directly reduces the signal
swing in analog circuits, which in turn makes the design of wide dynamic range mixed-
signal circuits a challenge. This raises the following question:
Will mixed-signal supply voltage follow the digital supply voltage down to 1 V?
In deep submicron CMOS ( m), the charge carriers velocity will be saturated at
the pinch-off point in the channel and as a result the classical quadratic saturation current
becomes , where to instead of [Hu94]. Therefore,
1.4X circuit speed improvement every generation will slow down to about 1.2X, leading to
another question:
What are the circuit techniques to maintain a high dynamic range at high speed?
Analog circuits are usually implemented using Switched-Capacitor (SC) techniques
because of their high circuit accuracy. Traditionally, SC circuits are implemented in
analog CMOS processes where linear double poly capacitors are available. However, the
driving forces behind the CMOS technologies are DRAMs and microprocessors which do
not require a double-poly process. The next question is:
Can linear SC circuits be implemented in a standard digital CMOS process?
These questions form the core of the research conducted in this thesis.
1.2 Thesis Objectives
This thesis is concerned with the three key issues mentioned above, namely: low voltage,
high speed, and the implementation of linear SC circuits in a digital CMOS process.
Through analysis and some preliminary experimental circuits it will be shown that SC
mixed-signal circuits will scale down to .
Low voltage: To demonstrate the feasibility of mixed-signal circuits, low-threshold
E CV
2

L 0.5 <
I
dsat
v
GS
V
t
( )

1.3 = 1.4 2
1 V
1 V
Chapter 1 Introduction 3
MOSFET transistors are required. A CMOS process technology is developed as a
subset of a m n
+
/p
+
dual poly gate CMOS process. In this process, natural threshold
voltage MOSFETs are optimized to have a of about . A rst-order voice-band
SC modulator is implemented in this process and operates at power supply.
High speed: Low-voltage operation is known to compromise speed unless the technology
shrink is in proper relation to the supply voltage. Two new high-speed bandpass
modulators are implemented in a m CMOS process to verify their performance
and functionality.
Linear SC design in a digital CMOS process: MOSFET capacitors biased in strong
inversion or accumulation regimes can be used to replace linear capacitors. A telescopic
opamp with different input and output common mode voltages is shown to be suitable for
this purpose. Also described is the design of a fourth-order SC bandpass modulator
using pMOSFET transistors, biased in strong inversion, as linear capacitors.
The benchmark circuits are chosen to be modulators for the following two reasons.
First, a modulator is a typical mixed-signal circuit with enough complexity to test the
technology and to demonstrate the achievable performances. It contains important analog
cells such as opamps, comparators and switches as well as some digital gates including
inverters, NORs, and a D-type ip-op. Second, modulators are widely used as
precision Analog-to-Digital (A/D) converters and are becoming popular in A/D
conversion of narrow-band signals at Intermediate Frequencies (IF) in radio receiver
circuitry.
1.3 Contributions
Contributions of this work include:
Proposed and veried suitability of low- natural MOSFETs for mixed analog/
digital applications.
Compared Switched Capacitor (SC) and Switched Current (SI) analog techniques for
low-voltage applications.
Analyzed low-voltage SC circuits using low- MOSFETs.
1 V
0.5
V
t
200 mV
1 V
3 V 0.5
V
t
1 V
V
t
Chapter 1 Introduction 4
Proposed low-leakage series transmission gate and composite switches.
Demonstrated a technique for exploiting the short-channel effects to obtain low-
voltage switches.
Implemented a high-speed architecture for bandpass modulator.
Developed a novel double-sampled bandpass modulator.
Designed a fourth-order SC bandpass modulator in a standard digital CMOS
process.
1.4 Thesis Outline
Chapter 1 provides an introduction.
Chapter 2 starts with an examination of CMOS scaling in deep submicron geometries
which require supply voltage scaling down to . Theoretical limits on low-voltage
digital and analog CMOS due to circuit topology are discussed and some recent work in
this area is reviewed. Oversampling and noise-shaping are then briey overviewed and a
simple mapping of lowpass to bandpass [Jantzi] is described. High-speed SC
bandpass modulator techniques are also presented. Next, the Switched-Current (SI)
analog circuit technique [Hughes89] is introduced and methods of implementing SC
circuits in a digital CMOS process are discussed. Finally, a comparative study of SC and
SI for low-voltage applications is presented. It is concluded that the SC technique is
preferred in low-voltage circuits from a dynamic range point of view.
In Chapter 3, low-voltage SC circuit design using low- MOSFETs is considered. First,
two methods of achieving low- MOSFETs in current CMOS processes are proposed.
The impact of subthreshold leakage current on the accuracy of the SC circuit is then
analyzed. Methods of reducing the subthreshold leakage through analog switches are
discussed next and two new switch topologies (series transmission gate and composite
switch) addressing this problem are presented. Finally, two experimental circuits, a
modulator using short-channel MOSFETs and a modulator using low-
natural MOSFET are discussed.
Chapter 4 begins by examining motivations for a high-speed bandpass modulator. A
1 V
V
t
V
t
2.25 V 1 V
V
t
Chapter 1 Introduction 5
high-speed fourth-order SC bandpass modulator is discussed, followed by presentation
of a double-sampled SC bandpass modulator. Fully differential circuit
implementations of both modulators in a m analog CMOS process are
described and measured results are presented.
Chapter 5 describes a SC circuit technique employing MOSFET capacitors biased in
strong inversion as linear capacitors. Distortion caused by capacitor non-linearity in a SC
amplier is analyzed. Then, the design of a fourth-order bandpass modulator using a
pMOSFET transistor as a linear capacitor is described.
Chapter 6 draws the thesis conclusions and proposes future work.
Appendices which provide some additional information on MOSFET equations used in
this thesis and measured characteristics of natural MOSFETs are also included.
3 V 0.5
6
Chapter 2
Impacts of CMOS Scaling on
Performance of Mixed-Signal Circuits
2.1 Introduction
The scaling of CMOS technology in the deep submicron regime is expected to continue
providing faster and denser devices. In section 2.2, CMOS scaling is reviewed along with
the fact that, for device reliability, the supply voltage is being scaled down in deep
submicron technologies. The power supply voltage of m CMOS technology is
expected to be about [Davari95]. Along with the power supply, the threshold voltage
of MOSFETs must be scaled down to achieve high-speed circuits. Limits on supply
voltage scaling for mixed-signal circuits are considered in section 2.3; some current
research in the area of low-voltage digital and analog circuits is also presented. The impact
of reducing the supply voltage on power dissipation of digital and analog circuits is
discussed next. In section 2.4, modulators, which are the benchmark circuits in this
thesis, are introduced and high-speed bandpass SC modulators reported in the
literature are discussed. Most advanced CMOS processes are developed to support
memory and digital circuits. Thus, mixed-signal circuits that are realizable in a standard
digital CMOS process are desired. Analog SI and SC circuit techniques that allow mixed-
signal circuits to be implemented in a digital CMOS process are discussed in section 2.5.
Finally, a comparative study of SC and SI sampled-data analog circuit techniques is
presented in section 2.6. It will be seen that SC has advantages over SI for low-voltage
design.
0.1
1 V
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 7
2.2 CMOS Scaling
The scaling of CMOS technology is achieved by reducing the dimensions of MOSFET
transistors by a factor of ( ). The original Constant Electric-eld (CE) scaling law
proposed by Dennard [Dennard74] involved supply voltage scaling as well as scaling all
the device dimensions to preserve the same electric-eld in the scaled-down device. A
constant electric-eld in the substrate is obtained by increasing device-well doping
concentrations in the smaller devices. The CE scaling scheme improves the device density
by , reduces the gate delay by , and lowers power dissipation by thus maintaining
a constant power density.
Drawbacks of CE scaling are the departure from standard power supply voltage, problems
with MOSFET threshold voltage scaling, and degradation in analog signal swing.
Therefore, in the past (down to m technology) a Constant Voltage (CV) scaling rule
has been used for CMOS to maintain a supply voltage of and to achieve higher circuit
performance; gate delay is reduced by in a CV scaling. However, in CV scaling the
higher electric eld causes a reliability hazard due to hot carriers and gate oxide
breakdown. A higher electric eld in deep submicron devices also brings about carrier
velocity saturation, which causes speed improvement to become linearly proportional to
(similar to CE scaling). Another drawback of CV scaling is an increase in power
dissipation density which is proportional to .
A compromise between CV and CE scaling schemes is a general scaling theory called
Quasi-Constant Voltage (QCV) scaling. In a QCV scaling, power supply voltage is
reduced at a slower rate of approximately . In Table 2.1, various scaling schemes and
their effects on MOSFET device characteristics are summarized.
Studies of CE, CV, and QCV scaling for mixed-signal circuits in high-micron [Wong83]
and submicron [Sano88] CMOS technologies have shown that QCV scaling is close to an
optimum scaling scheme.
2.2.1 CMOS Scaling in the Next Decade
Recently, Davari published a guideline for CMOS scaling in the next decade for digital
circuits [Davari95]. A summary of this guideline is produced in Table 2.2. Two different
k k 1 >
k
2
k k
2
0.5
5 V
k
2
k
k
3
k
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 8
power supply voltages are recommended for each generation of deep submicron
technology: one for high-performance ( ) circuits and another one for low-power ( )
circuits.
This guideline is in agreement with the SIA technology roadmap for semiconductors
presented in Chapter 1. By the year , the power supply voltage is predicted to be
scaled down to for high-performance circuits and for low power applications.
Supply voltage scaling in CMOS, undertaken to maintain reliability, causes severe speed
performance degradation unless the MOSFET threshold voltage ( ) is scaled down.
Parameters CE CV QCV
Lateral dimensions (L)
Gate oxide thickness (t
ox
)
Doping concentration
Supply voltage (V)
Electric eld
Current (I)
Area (A)
Capacitance (C=A/t
ox
)
Gate delay (VC/I)
Power dissipation (VI)
Power density (VI/A)
Energy dissipation (CV
2
)
Table 2.1: CMOS scaling schemes
Year 1995 1998 2001 2004
Supply voltage ( ) V 3.3/2.5 2.5/1.5 1.5/1.0 1.2/1.0
Channel length (m) 0.35 0.25 0.18 0.13
Oxide thickness (nm) 9 6 3.5 2.5
Table 2.2: A guideline for CMOS scaling
1 k 1 k 1 k
1 k 1 k 1 k
k k
2
k
1.5
1 k 1 1 k ( )
1 k 1
1 k k 1 k
1 k
2
1 k
2
1 k
2

1 k 1 k 1 k
1.5

1 k 1 k
2
1 k
1 k
2
k 1 k
1.5

1 k
3
k
1 k
3
1 k k
2.5
HP LP
HP LP
2004
1.2 V 1 V
V
t
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 9
Circuit speed suffers because it is proportional to transconductance ( ) and for a fully
turned- on MOSFET (i.e., ) the transconductance is .
2.2.2 V
t
Scaling Issues
A MOSFET transistor biased below threshold voltage ( ) operates in the weak
inversion mode where drain current is exponentially dependent on the value of
(Appendix A). The subthreshold off-current (for ) is given by the following
simplied equation:
, ( 2-1 )
where is the subthreshold swing and is given by
( 2-2 )
and typically .
Non-Scalability of Subthreshold Swing
As can be seen from (2-2), subthreshold swing does not scale with technology scaling.
Therefore, the main limitation of scaling is due to the non-scalability of .
At room temperature, has a typical value of for bulk CMOS, and
increases to about at . Reducing the threshold voltage of
MOSFETs by increases the subthreshold off-current by an order of magnitude.
Higher off-current increases the standby power dissipation in digital circuits and limits the
accuracy of the analog SC circuits.
Digital circuits: In digital CMOS circuits the total power consumption expression is
, ( 2-3 )
where is the activity factor, is the clock frequency, is the load capacitance,
is the supply voltage, and is the short circuit current during each input transition
when both nMOSFET and pMOSFET are temporarily on.
Lowering the increases the off-current and the second term in the above equation will
g
m
v
GS
V
DD
= g
m
V
DD
V
t

v
GS
V
t

v
GS
V
t

v
GS
0 =
i
off
I
D0
W
L
-----10
V
t
S
=
S
S n
kT
q
------ln 10 ( ) =
n 1.4
V
t
S
S 80 mV/decade
100 mV/decade 85C
100 mV
P p
0 1
f C
L
V
DD
2
i
off
V
DD
i
sc
V
DD
+ + =
p
0 1
f C
L
V
DD
i
sc
V
t
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 10
rise. However, low- MOSFETs allow operation at a lower without sacricing
speed performance. A reduced decreases the dynamic power consumption, the rst
term in (2-3).
Several studies [Liu93] [Burr91] have shown that a signicant power saving is achieved
by operating at very low supply voltages (as low as ) using low- MOSFETs,
while preserving circuit speed.
Analog circuits: Analog switches in SC and SI circuits must exhibit a low on-resistance
when closed and very low leakage current when opened. At a low supply voltage, low-
MOSFET are suitable as switches due to their low on-resistance. However, low-
switches are leaky and limit the precision of the analog circuits. In Chapter 3, the impact
of leakage through analog switches is analyzed and some solutions are proposed.
A sharper subthreshold slope (i.e., a lower value of ) is obtained by reducing , or , or
both in (2-2). The lowest possible value for is achieved in a CMOS on Silicon-on-
Insulator (SOI) process where . The corresponding value of is
at room temperature. Low-Temperature (LT) CMOS is another method of scaling the
subthreshold swing. Operation at liquid nitrogen temperature ( K) reduces by a
factor of four to about .
Both SOI and LT-CMOS furnish a better scaling and are promising technologies for
very low-voltage deep sub- m CMOS processes.
Threshold Voltage Fluctuation
Another limitation of scaling is based on the fundamental variability of the threshold
voltage due to process variations. Fluctuation in is mainly due to random dopant and
channel length variations. For a normally distributed threshold voltage, the standard
deviation due to random dopant concentration variation is
, ( 2-4 )
where is the doping density, and are the channel length and width of the
transistor, and is the depletion width [Keyes75].
V
t
V
DD
V
DD
200 mV V
t
V
t
V
t
S n T
n
n 1 = S 57.5 mV/decade
77 S
14.5 mV/decade
V
t
0.1
V
t
V
t
V
t
q
2C
ox
------------
N
A
2
----------- WL ( )
3 8
X
D
( )
1 4
=
N
A
L W
X
D
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 11
Recent studies based on measurements [Mizuno93] and simulations [Nishinohra92]
[Wong93] show that variation due to dopant uctuation is proportional to , in
agreement with (2-4), and increases as channel length is reduced. In [Nishinohra92], 2-D
and 3-D simulations indicate that is expected to increase from , for m
technology, to about for a m technology.
Temperature variation also changes the by approximately [Chen90]. For
an industrial temperature range of to , the total threshold shift due to
temperature alone is about .
In low- processes, threshold voltage changes due to process variations and temperature
have a big impact on speed and standby power dissipation. For instance speed
performance variation (based on quadratic equation formulae given in Appendix A) due to
a change in is about % in a process with , and rises to
% in a process with . Assuming at and
, the highest off-current in the above example would be for
the high- and for the low- processes, respectively. Such a large
impact on speed and standby power dissipation due to threshold variation in a low-
scenario is intolerable and circuit techniques to address this problem are discussed briey
here.
Multi-threshold voltage: A process with multiple threshold voltage transistors offers
circuit design exibility at the cost of additional threshold adjust masks and an implants.
Low- transistors can be used for circuit speed and high- transistors can be used to
reduce the leakage current [Shinichiro93].
Back-bias adjusting: Threshold voltage can be held constant by adjusting the
substrate voltage. Figure 2.1 shows negative feedback circuitry which generates a
substrate voltage to keep equal to a constant [Shoji92] [Bazarjani95d]. The
amplier in this circuit operates with supply voltages of and where is
the positive supply (generated by a charge-pumped circuit) to keep source/drain and bulk
junctions reverse biased at all times.
A self-substrate-biasing circuit technique is also reported in [Kobayashi94] to reduce the
V
t
1 L
V
t
( ) 10 mV 1
30 mV 0.1
V
t
1.25 mV/C
50C 85C
170 mV
V
t
100 mV t V
t
2.5 t 5 V V
t
0.8 V =
12 t 1 V V
t
0.2 V = i
DS
1 A = v
GS
V
t
=
S 100 mV/decade = 100 fA
5 V V
t
10 nA 1 V V
t
V
t
V
t
V
t
V
t
V
tp
V
ref
V
P
V
DD
V
P
V
DD
>
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 12
uctuation. In [Kuroda96], a back-bias feedback circuit that adjusts to in
active mode and in the standby mode is discussed. A complete study of
adjusting circuits in SOI through back-bias along with the charge pump circuitry is under
investigation [Soreefan96].
Summary
Supply and threshold voltages of future deep submicron CMOS technologies are being
scaled down. Reducing the threshold voltage increases the off-current due to non-
scalability of subthreshold swing, , limiting the minimum .
2.3 Low-Voltage Mixed-Signal Design
Low-voltage micropower circuit techniques were developed in the late 1960s and early
1970s for electronic wristwatches. These circuits had to operate from a single cell
mercury or silver oxide battery. The operating frequencies of these circuits were
typically a few kHz and their total power consumption was below W. Other low-power
applications include calculators, hearing aid devices, and pacemakers. In all these systems,
the required speed performance of the circuit is low, typically less than .
The technology of choice for low-power applications has been CMOS due to its very low
static power dissipation. Techniques to build low threshold voltage MOSFETs with
were developed in the late 1960s [Nagane69][Leuenberger69] and
V
DD
-V
ref
V
DD
V
p
V
sub
AI
D0
W/L=A
Figure 2.1: A negative feedback V
t
adjust circuit
V
t
V
t
0.1 V
0.5 V V
t
S V
t
1.35 V
1.5 V
1
1 MHz
V
t
0.5 0.8 V
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 13
methods of adjusting the threshold voltage by doping implants were successfully
demonstrated by Swanson [Swanson72].
In this section, limitations to low-voltage digital and analog designs due to circuit
topology are discussed and some recent research in the area of low-voltage digital and
analog circuits is presented. Finally, the impact of supply voltage scaling on power
consumption of digital and analog circuits is considered.
2.3.1 Limits on Digital CMOS Supply Voltage Scaling
A lower limit on the supply voltage of digital circuits is set by the requirement that the
voltage gain of a logic gate must be greater than unity. This condition is necessary to
obtain regeneration of logic levels at the output of each gate.
In [Swanson72], MOSFET equations in weak inversion are derived and low-voltage
operation of a CMOS inverter circuit is analyzed. Voltage gain of the CMOS inverter at
mid-rail is found to be: . Thus, the minimum required supply
voltage for digital CMOS is
. ( 2-5 )
This is the theoretical lower bound for the supply voltage of a static CMOS inverter
circuit, about at room temperature. Some experimental circuits that have
demonstrated the validity of the above limit include: a 11-stage ring oscillator
[Swanson74], a 7-stage ring oscillator operating at at room temperature and
at [Burr95].
The present supply voltage of for CMOS is a factor of larger than the theoretical
limit of found in (2-5). Therefore, a large margin for supply voltage reduction
exists for CMOS.
In CMOS logic, a certain energy ( ) is stored on the gate capacitance to represent
logic 1. This stored energy must be greater than the thermal noise in that capacitor. The
mean thermal noise energy in a capacitor is and in [Stein77], it is shown that for an
error rate of the minimum energy required per operation is . Considering
this energy requirement and the minimum supply voltage of (2-5), a logic operation
V
DD
2 ( ) q nkT ( ) ( )
V
DD
min
2nkT
q
------------- >
50 70 mV
100 mV
75 mV
27 mV 77 K
3.3 V 47
70 mV
CV
2
2
kT 2
10
19
165kT
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 14
involves only electrons.
At this point, it would be interesting to see what are the minimum required supply voltage
and logic swing for a bipolar circuit. A similar study for a Current Mode Logic (CML)
gate, Figure 2.2, shows that exceeding unity gain requires the logic swing to be [Gray93]
. ( 2-6 )
At room temperature, the lower bound of logic swing for bipolar circuits is about .
The lower limit of the power supply voltage for this CML gate is determined by the
voltage required to turn on the input transistors Q1 and Q2 which is
. ( 2-7 )
Assuming a turn-on of , a logic swing, and a minimum of
, the minimum required supply voltage for the CML gate is about .
Existing CML gates, with a logic swing of , operate close to the limits of
power supply (higher by a factor of 3) and logic swing (higher by a factor of
4).
Thus, there is a very narrow margin for supply voltage reduction of bipolar CML gates.
118
V
Swing
2kT
q
---------- >
V
ip
V
b1
V
in
V
op
V
on
V
CC
R
L
R
L
Q1 Q2
Q3
Figure 2.2: A basic CML inverter-buffer gate
50 mV
V
CC
min
V
BE
V
Swing
V
CE
+ + =
V
BE
0.75 V 50 mV V
CE
0.2 V 1 V
3 V 200 mV
1 V 50 mV
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 15
2.3.2 Limits on Analog CMOS Supply Voltage Scaling
This section is an investigation into the lower limit of the supply voltage for an opamp,
analog switch, and current mirrorthe three basic building blocks commonly used in
analog SC and SI circuits.
Operational Transconductance Amplier
Consider a simple single-stage fully differential opamp circuit, as shown in Figure 2.3.
The minimum input common-mode voltage required for the proper operation of this
amplier is determined by the voltage needed to turn on the input differential pair
MOSFETs, transistors N1 and N2, as given by
. ( 2-8 )
Here, is the input common-mode voltage, is the threshold voltage of the
transistor M1, is the drain-source voltage of the transistor N3, and is the gate
to source overdrive voltage of the transistor N1 which is dened as
. ( 2-9 )
V
ip
V
in
N1
N2
N3
P1 P2
V
DD
V
op V
on
V
b1
V
b2
Figure 2.3: A fully differential CMOS Opamp
V
icm
min
V
tn1
V
on1
v
DS3
+ + =
V
icm
V
tn1
v
DS3
V
on1
V
on
v
GS
V
t
=
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 16
The minimum required to keep the transistor M3 in saturation is
. ( 2-10 )
If equal threshold voltage and overdrive voltage is assumed for all the transistors
and also assumed that (i.e., charge-pump techniques are not used), from
equation (2-8) the lower bound on the supply voltage of the opamp is
. ( 2-11 )
The minimum required drain-source saturation voltage depends on the MOSFET mode of
operation. If the device is in weak inversion, the minimum saturation voltage required is
about [Vittoz94], which is at room temperature. However,
the minimum drain-source saturation voltage of MOSFETs operating in strong inversion
is about .
In a typical m CMOS process, with a threshold voltage of , and assuming an
overdrive voltage of , the minimum supply voltage of this opamp is . In this
calculation, we ignored variations due to process uctuation, temperature changes and
back-bias voltage as well as constraints on input and output common-mode levels.
In a low- process, the minimum supply voltage of the opamp (Figure 2.3) may be
determined by the drain-source saturation voltage (or ) and the required output
voltage swing . Assuming equal gate to source overdrive voltage for all the
transistors, the minimum supply voltage is
. ( 2-12 )
For and an output voltage swing of , the minimum power supply
voltage is .
Analog Switch
An analog switch must have a full rail-to-rail signal handling capability with a low on-
resistance. An nMOSFET transistor used as a switch operates in triode mode with on-
resistance of approximately
v
DS3
v
DS3
min
V
on3
v
GS3
V
t3
= =
V
t
V
on
V
DD
V
icm
>
V
DD
min
V
t
2V
on
+ =
4 6 ( )kT q 100 150 mV
200 mV
0.5 0.6 V
0.2 V 1 V
V
t
V
t
V
on
V
out swing ( )
V
DD
min
3V
on
V
out swing ( )
+ =
V
on
0.2 V = 0.4 V
1 V
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 17
. ( 2-13 )
A parallel nMOSFET and pMOSFET switch (transmission gate) has a rail-to-rail signal
swing capability if the supply voltage is
. ( 2-14 )
The effective threshold voltages, , and are given by
. ( 2-15 )
is the upper value of threshold voltage due to process variations,
and are the threshold voltage changes due to temperature, and the back bias
respectively and are given by
( 2-16 )
. ( 2-17 )
Here, is temperature in degrees Celsius, and is the slope of threshold voltage as a
function of temperature, which is about . Other parameters are the body
effect coefcient , the bulk potential , and the source to bulk voltage .
The on-conductance of a transmission gate switch as a function of signal level is shown in
Figure 2.4 for three different values of power supply voltages [Vittoz93]. In this gure the
R
on
1
C
ox
W
L
----- v
GS
V
tn
( )
------------------------------------------------ =
V
DD
V
tn e ,
V
tp e ,
2V
on
+ + =
V
tn e ,
V
tp e ,
V
te
V
t0
Max ( ) V
t
T ( ) V
t
v
SB
( ) + + =
V
t
Max ( ) 3 V
t
T ( )
V
t
v
SB
( )
V
t
T ( ) a 25 T ( ) =
V
t
v
SB
( ) 2
B
v
SB
+ 2
B
( ) =
T a
1 2 mV C
0.5
B
v
SB
Figure 2.4: Complementary transmission gate switch on-conductance for
(a) V
DD
<2V
t
, (b) V
DD
=2V
t
, and (c) V
DD
>2V
t
V
in
g
on
V
DD
V
in
g
on
V
DD
V
in
g
on
V
DD
V
SS
V
DD
V
in
(a) (b) (c)
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 18
threshold voltages of nMOSFET and pMOSFET are assumed to be equal to .
In a m process with effective threshold voltages of , a supply voltage of is
required to turn the transmission gate on with a minimum overdrive of at mid-rail.
Current mirror
A current mirror circuit is a current gain cell that provides a weighted output copy of an
input current. This circuit forms the foundation of SI signal processing and is also widely
used to provide bias currents in such blocks as opamps and comparators. A simple current
mirror circuit is shown in Figure 2.5. The voltage generates a current in the
transistor which is fed to the diode-connected transistor . Since transistors and
have the same gate and source potential, their drain-source currents are related by
. ( 2-18 )
If and are identical transistors, will mirror . For accurate operation, all the
transistors in the circuit must be in the saturation regime. Transistor is diode
connected and when it is turned on it will be in saturation with a gate (or drain) to source
voltage of . Assuming the same overdrive voltage ( ) for all the MOSFETs,
transistor requires a drain to source voltage of at least to be in saturation. Thus, the
minimum required supply voltage for proper operation of the simple current mirror is
, ( 2-19 )
V
t
0.5 0.8 V 2 V
0.2 V
V
B
I
B
P N1 N2
N1
I
2
I
1
-----
W L ( )
N2
W L ( )
N1
------------------------ =
I
B
N1 N
2
1
V
B
P I
2
~ I
B
Figure 2.5: A simple current mirror cell
N1 N2 I
2
I
B
N1
V
t
V
on
+ V
on
P V
on
V
DD
V
t
2V
on
+ >
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 19
which is identical to the minimum supply voltage expression obtained for a simple opamp
(2-11). Comparison of (2-11), (2-19) and (2-14) shows that switches are the bottleneck for
low-voltage SC and SI operation.
2.3.3 Previous Work on Low-Voltage Digital Circuits
A low-voltage digital design using standard CMOS technology, by A. Chandrakasan at
Berkeley University, is described rst. Then, a theoretical analysis by Dake Liu at
Linkoping University, showing power savings achieved by supply voltage and threshold
voltage down-scaling, is discussed. Finally, an experimental encoder-decoder system
operating at , by Jim Burr at Stanford University, is presented.
Berkeley
Power optimization at different levels of technology, circuit style, architecture, and supply
voltage scaling is considered in [Chandrakasan92]. The most efcient logic family was
found to be CPL (Complementary Pass-transistor Logic) if low threshold nMOSFETs are
available. Logic gates must be designed for the lowest acceptable speed to save
unnecessary energy loss.
In a m CMOS technology, a power supply of is found to be the optimum for a
large variety of cases. At such a low voltage ( ), circuit speed may become
unacceptably low for some applications. In such cases, techniques such as parallel
architecture and pipelining can be used to obtain lower latency and higher throughput
rates.
Linkoping
An extensive study of the impacts of supply voltage and threshold voltage scaling is
reported in [Liu93]. Reducing the supply voltage decreases the power consumption in
CMOS logic ( ). However, speed performance is
degraded unless the threshold voltage is scaled down.
In a m CMOS technology it is shown that a factor of reduction in power
dissipation is possible, without any speed loss, by reducing the supply voltage from
to and properly optimizing the MOSFETs threshold voltages from to
and .
200 mV
2 1.5 V
V
DD
2V
t
=
P fCV
2
T V
DD
( ) V
DD
V
t
( )
2

0.25 40
3 V
0.48 V 0.7 V
V
tn
0.1 V = V
tp
0.01 V =
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 20
Stanford
Low-power research at Stanford University [Burr91] focuses on the use of near zero
threshold voltage (~ ) MOSFETs and selecting a power supply voltage of
. The threshold voltage is ne-tuned by applying a back-bias potential.
Low threshold voltage devices allow reduced power supply voltage, which in turn
decreases AC power dissipation quadratically. However, DC power consumption, due to
the subthreshold leakage, increases exponentially. The minimum total power dissipation is
obtained at a supply voltage where the AC component of the power dissipation and the DC
power dissipation are equal. In a m CMOS technology, is shown to be the
optimum supply voltage for digital circuits with a logic depth of and an activity ratio
of . An experimental CMOS Encoder/Decoder circuit is demonstrated in [Burr94] to
operate at supply voltage.
2.3.4 Previous Work on Low-Voltage Analog Circuits
Work on low-voltage analog circuits started in bipolar technology in the 1970s. Some
reported 1V circuits in bipolar technology include: a bandgap voltage reference
[Vittoz77], operational ampliers [Widlar78] [Huijsing85], an active lowpass lter
[Tanimoto91], and an analog current mode multiplier cell [Chan95].
Low-voltage analog circuits in CMOS (the focus of this work) started in the late 1970s
[Vittoz77] and early 1980s [Vittoz80] [Krummen82]. Low-voltage analog circuits are
implemented using Switched-Capacitor (SC), active-RC, and Switched-Current (SI)
techniques. This section starts by describing a A/D converter using an active-RC
technique. A converter implemented with the SI technique is then discussed.
Finally, three papers dealing with low-voltage SC lters are presented.
2.3.4.1 Low-Voltage Active-RC Circuits
A second-order modulator, implemented in a m multi-threshold voltage
CMOS technology, is reported in [Matsuya94]. Integrators in the modulator are
implemented using an active-RC technique, as shown in Figure 2.6. For an oversampling
ratio of , this modulator has a SNDR of and a dynamic range of . The
modulator operates at a clock frequency of (signal bandwidth of )
100 mV
V
DD
3V
t
=
2 200 mV
10
0.1
200 mV
1 V
1.2 V
1 V 0.5
16 51 dB 58 dB
6.14 MHz 192 kHz
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 21
and consumes at a power supply voltage.
Since subthreshold leakage current through low- analog switches was the main source
of concern in this design, SC implementation was ruled out. In Chapter 3 of this thesis, the
impact of leakage current through analog switches on the accuracy of SC circuits are
discussed and methods of reducing the subthreshold leakage are also presented.
A drawback of integrated active-RC circuits is inaccuracy in the RC time constant,
because monolithic resistors and capacitors have a tolerance of more than % and do
not track each other. For lowpass modulators, variations in the RC time constant
causes a gain variation and is not critical.
2.3.4.2 Low-Voltage Switched-Current Circuits
Recently [Tan95], a low-voltage second-order SI modulator was reported which
operates at . The circuit, however, is not a true part because the switches
operate from a higher external supply voltage.
The circuit is implemented in a m digital CMOS process using a fully differential SI
memory cell with a common-mode feed forward circuit. This modulator is clocked at
and consumes . The measured SNDR and SNR for an oversampling
ratio of are and respectively. Ideally, this modulator should achieve a
SNDR of more than . The low performance of this SI circuit is attributed (by the
authors of the original paper) to circuit noise generated by the rst current copier cell.
A review of SI technique is provided in section 2.5. In section 2.6 it will be shown that SC
has some advantages over SI for low-voltage applications.
1.56 mW 1 V
C
s
Vip
Vop
R
i
Figure 2.6: An active-RC integrator
V
t
15 t
1.2 V 1.2 V
0.8
1 MHz 0.78 mW
64 55 dB 51 dB
80 dB
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 22
2.3.4.3 Low-Voltage Switched-Capacitor Circuits
In CMOS, SC is the dominant technique for implementing analog circuits due to its high
circuit accuracy and low distortion even at low supply voltages [Castello91]. For low-
voltage applications, the most critical component in a SC circuit (and a SI circuit) is the
transmission gate switch, which requires a gate voltage of at least for proper full
swing signal handling. In SC circuits, few switches usually require rail-to-rail signal
swing. For instance, in the non-inverting SC integrator of Figure 2.7 only the input switch
(S1) needs to be implemented with a transmission gate, an nMOSFET and an pMOSFET
in parallel. All the other switches are connected to analog ground and thus
can simply be nMOSFET transistors.
In general, to achieve full signal transmission through a MOSFET switch with acceptable
on-resistance, either the gate voltage must be increased (e.g., clock voltage multiplication)
or the threshold voltage of MOSFETs must be reduced. A third solution would be to
eliminate the need for switch . In the following section, the above methods of low-
voltage SC design are described.
(I) Clock Voltage Multiplication
If the supply voltage is less than , the MOSFET switches will not be able to conduct
when biased at the mid-rail. Clock voltage boosting is an effective way of increasing the
conductance of the MOSFET switches. This is the most commonly used technique in low-
voltage SC circuits [Krummen83] [Callias89] [Castello91] [Wayne92] [Grilo96] [Au96].
A biquadratic SC lowpass lter operating at is reported in [Castello91] for
2V
t
V
ag
V
DD
2
Figure 2.7: A non-inverting SC integrator and its associated 2-phase
non-overlapping clock
C
S
C
I
V
op

2
S1
S2
S3
S4
A B
V
in
Analog Ground = V
DD
/2
S1
2V
t
1.5 V
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 23
telephony applications. This lter uses a fully differential architecture and is fabricated in
a m BiCMOS technology. The clock frequency is and the measured THD
is for a signal.
This technique requires extra circuitry for voltage multiplication, may need an off-chip
capacitor, and is noisy. Another drawback of voltage boosting is that in deep submicron
modern processes, the higher electric eld of clock voltage is a reliability hazard and is not
acceptable.
(II) Low-V
t
MOSFETs
Reducing the threshold voltage of MOSFETs will reduce the on-resistance of the
switches. In [Adachi90], a lower threshold voltage nMOSFET ( ) is fabricated
by adding an extra mask for threshold adjust implant to a double-poly m CMOS
process. A 7th- order Chebyshev SC lowpass telephony lter, implemented in this process,
operates at and consumes . This lter is clocked at and has a
cutoff frequency of . The in-band noise for an input signal with a signal is
measured to be . This performance is comparable to the SC lters operating at
.
This method may require process modication. However, in multi-threshold processes
[Sun92] [Mutoh93], low- MOSFETs are available at no extra cost. A low-cost method
of fabricating low- devices in a dual poly gate process is also discussed in Chapter 3.
An advantage of this approach (i.e., the low- MOSFET switch) is compatibility with the
future of CMOS technology and low-power digital design [Liu93][Burr94] because power
supply scaling is forcing down-scaling.
(III) Switched-Opamp Circuits
In a SC circuit most switches are connected to analog (or virtual) ground. By selecting an
analog ground which is very close to , nMOSFETs that conduct well can be used as
switches. The input switch that requires full signal swing, switch in Figure 2.7, can be
replaced with a switched-opamp as shown in Figure 2.8.
A second-order lowpass lter implemented using a switched-opamp is described in
[Crols94] and operates at while consuming W. This biquadratic lter is
0.8 447 kHz
70 dB 1.5 Vpp
V
t
0.2 V =
2
1.4 V 0.49 mW 111 kHz
3 kHz 1 Vpp
67 dBm
5 V
V
t
V
t
V
t
V
t
V
SS
S1
1.5 V 110
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 24
clocked at and has a cutoff frequency of . For an output swing of
, the total harmonic distortion is measured to be . The dynamic range of
this lter is about .
In a SC circuit, the very rst input switch is not driven by an integrator and therefore can
not be replaced with a switched-opamp. One solution is to implement the rst stage of the
circuit using an active-RC technique. This causes a gain error, which may be acceptable,
while all the loop time constants are determined by SC topologies.
2.3.5 Impact of Voltage Scaling on Power Dissipation of Mixed-Signal Circuits
Power dissipation in a circuit must be studied in relation to other performance parameters
of the circuit. For instance, in digital circuits there is a trade-off between power dissipation
and speed of the circuit. In general, one is interested in reducing power consumption while
not sacricing speed. This means reducing the energy consumption of the circuit. In
analog circuits, power minimization must be considered along with the speed and dynamic
range of the circuit. In this section, the effects of supply voltage scaling on energy
dissipation of digital circuits and power dissipation of analog circuits (for a xed speed
and dynamic range) are investigated.
Power Dissipation in Digital CMOS
In general, power dissipation is caused by two types of current: a dynamic current and a
static current. A CMOS inverter, Figure 2.9, is used to illustrate various components of the
power dissipation in static CMOS logic.
The static power dissipation is caused by MOSFET subthreshold leakage and leakage
C
S
C
I2
Vop
C
I1
Figure 2.8: A switched-opamp SC integrator
115 kHz 1.5 kHz
0.55 Vpp 64 dB
69 dB
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 25
currents through reverse-biased junctions ( ). When switching, charging and
discharging of the load capacitor ( ) is the main source of power dissipation which is
quadratically proportional to the supply voltage. During each input transition, there is also
a short circuit (crowbar) current ( ) owing directly from the power supply to ground
when both nMOSFET and pMOSFET are temporarily on ( ). The
total power consumption is
. ( 2-20 )
Dynamic power dissipation is usually the dominant term in (2-20) [Burr91].
Energy dissipation is a measure of the power-delay product, which is
. ( 2-21 )
Supply voltage scaling reduces the energy dissipation in digital CMOS circuits
quadratically.
Power Dissipation in Analog SC Circuits
The SC integrator shown in Figure 2.7 is considered for the study of power dissipation in
analog SC circuits.
Just as for digital circuits, there are two types of power dissipation: dynamic and static.
Leakage currents, DC bias currents in bias circuitry, and opamp bias currents for class A
operation will all contribute to static power dissipation.
( 2-22 )
N
P
C
V
in
V
op
Figure 2.9: CMOS inverter
I
leak
C
I
sc
V
tn
V
in
V
DD
V
tp
< <
P I
leak
V
DD
fCV
DD
2
I
sc
V
DD
+ + =
fCV
DD
2
E CV
DD
2
=
P
static
I
leak
V
DD
I
bias
I
A
+ ( )V
DD
+ =
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 26
Dynamic power is dissipated by the clock generator, charging and discharging MOSFET
switches, as well as by ampliers charging load capacitors ( and ). The dynamic
power dissipated in clock drivers due to the gate capacitance of MOSFET switches is
. ( 2-23 )
The average power dissipated in driving the load capacitors is given by the following
equation [Castello85]:
( 2-24 )
Here, is the peak amplitude of a sinusoidal signal and is the clock frequency. In
analog circuits an important gure of merit is dynamic range (DR), which is a measure of
circuit accuracy and is given by
. ( 2-25 )
is the RMS value of the input sinusoidal signal, is the
Boltzman constant, and is the temperature in degrees Kelvin. If we assume that the
input is a sinusoidal signal and can swing between supply rails, the RMS value of the input
is
. ( 2-26 )
Equations (2-24), (2-25), and (2-26) can be combined to describe power dissipation in the
sampling capacitor as a function of dynamic range and clock frequency. The resulting
equation is
. ( 2-27 )
This equation shows that for a given dynamic range the power dissipated in driving the
load capacitor is independent of the power supply voltage.
C
S
C
I
P
sw
f
clock
C
sw
V
DD
2
=
P
C
2

---V
i
V
DD
C
s
f
clock
=
V
i
f
clock
DR
Signal rms ( )
noise
------------------------------- -
V
i rms ,
kT C
s

--------------------- = =
V
i rms ,
k 1.38 10
23
J/K ( ) =
T
V
i rms ,
V
DD
2 2
----------- =
P
C
DR
2
2
----------- kT ( ) f
clock
=
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 27
Thus, in the limit, when DC power dissipation and power dissipated due to the switches
are negligible compared to AC power dissipation in driving the load capacitors, reducing
the power supply will not change the power dissipation in the analog circuitry.
In the above analysis, limitation on the unity gain bandwidth ( ) was not included. A
more realistic approach is to relate power dissipation to and . Power dissipation in
driving the load capacitor is
. ( 2-28 )
The speed of a SC circuit is determined by the unity gain bandwidth of the opamp which is
. ( 2-29 )
Here, is the transconductance of the opamp which has the following relation with the
quiescent current:
. ( 2-30 )
Combining equations (2-25), (2-26), (2-28), (2-29) and (2-30), the power dissipation can
be expressed in terms of dynamic range, speed, and supply voltage as
. ( 2-31 )
Thus, reducing the supply voltage, if accompanied by an increase in load capacitance to
compensate for dynamic range loss, will increase the total power dissipation in analog
circuits. Scaling with the supply voltage would give constant power dissipation but
would require process scaling to correct for the reduced transistor , which is inversely
proportional to channel length squared, .
If supply voltage scaling does not require increasing the load capacitor (and consequently
increasing the quiescent current), power dissipation will be reduced linearly with supply
voltage down-scaling. This happens when the value of the capacitor is determined by other
considerations such as stability or matching, and is higher than the required value due to

u
DR
u
P V
DD
I =

u
g
m
C
------ =
g
m
I g
m
V
on
2
--------- =
P DR
2
kT
u
V
on
V
DD
-----------
,

_

V
on
f
t
f
t
V
on
L
2

Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 28
noise.
Summary
Limits to low-voltage digital CMOS circuits indicate that there is a large margin for
supply voltage down scaling. A review of the literature in the area of low-voltage circuits
suggests that digital circuits using low- MOSFETs achieve a great saving in power
dissipation. In analog SC circuits, if the process is xed lowering the supply voltage will
increase the power dissipation in driving the load capacitance. On the other hand,
technology scaling allows to be scaled down along with the power supply without
sacricing device . In this case, power dissipation for a given dynamic range and unity
gain bandwidth will remain unchanged.
2.4 Oversampled Sigma-Delta Modulator Overview
Oversampled modulation is a noise shaping technique that converts an analog input
signal into a simple digital code (typically 1-bit) at a sampling frequency which is much
higher than the Nyquist rate. A block diagram of a general n-bit modulator comprising
a loop lter, an n-bit A/D, and an n-bit D/A in a negative feedback loop is shown in Figure
2.10.
The loop lter shapes the quantization noise out of the band of interest. If a lowpass lter
is placed in the loop, the quantization noise will be highpass ltered and if a bandpass
lter is chosen as loop lter, the quantization noise will be band-reject ltered. n a sigma-
delta A/D converter, the out of band quantization noise is removed by a digital lter that
also performs decimation.
kT C
V
t
V
on
f
t
Loop Filter
n-bit D/A
n-bit A/D

+
-
x(t)
y(t) u(t)
Figure 2.10: A block diagram of a modulator
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 29
is becoming the method of choice for high-precision low- or medium-speed A/D
converters. This is because compared to other techniques, such as ash and pipelined A/D,
the analog circuitry in a modulator is simple and relatively insensitive to circuit
imperfection and component mismatch. Also, due to the oversampling, the antialiasing
lter at the input of a A/D converter has relaxed requirements compared to that of a
Nyquist rate A/D converter. However, modulators require a large digital signal
processing unit for the decimation lter. Both simplicity of analog circuits and extensive
use of digital circuits in modulators are highly compatible with scaled-down CMOS
technologies.
In Figure 2.10, if the transfer function of the loop lter is denoted as and the n-bit
A/D (multilevel quantizer) is modeled as an additive noise , the equivalent linear
feedback system of Figure 2.11 is obtained.
The expression for the output -transform in terms of the signal transfer function
and noise transfer function is
. ( 2-32 )
The signal transfer function and the noise transfer function are respectively
( 2-33 )
. ( 2-34 )
H z ( )
Q z ( )

+
-
X(z)
Y(z)
H(z)

U(z)
Q(z)
+
+
Figure 2.11: Equivalent linear system of Figure 2.10
z F
X
z ( )
F
Q
z ( )
Y z ( ) F
X
z ( )X z ( ) F
Q
z ( )Q z ( ) + =
F
X
z ( )
H z ( )
1 H z ( ) +
--------------------- =
F
Q
z ( )
1
1 H z ( ) +
--------------------- =
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 30
2.4.1 Lowpass Sigma-Delta Modulators
A simple rst-order modulator is obtained by letting the loop lter be a discrete-time
integrator and also allowing the quantizer to have only two levels of . The z-domain
transfer function of a unity delay integrator is
. ( 2-35 )
Substituting the above into equations (2-33) and (2-34) will give the corresponding
signal transfer function and noise transfer function, as follows:
( 2-36 )
. ( 2-37 )
The signal transfer function is simply a unit delay and the noise transfer function is a rst-
order differentiator which behaves like a highpass lter. Since has a zero at DC, the
quantization noise is reduced at low frequencies and is pushed to high frequencies.
If the quantization error is assumed to be white noise with a mean square value of ,
the quantization noise in the signal band is approximately [Candy92]
, ( 2-38 )
where is the oversampling ratio dened as the ratio of the sampling frequency to
the Nyquist rate of the signal .
Increasing the by a factor of 2 reduces the quantization noise, in the rst-order
modulator, by which adds bits to the resolution.
A second-order noise shaping is achieved by allowing a double differentiator noise
transfer function as dened by
. ( 2-39 )
This noise transfer function has a double zero at DC. The corresponding single loop lter
t 2
H z ( )
z
1
1 z
1

---------------- =
H z ( )
F
X
z ( ) z
1
=
F
Q
z ( ) 1 z
1
=
F
Q

2
12
0 f f
B
< <
n
0
2
2
12
------

2
3
------
1
OSR
-----------
,
_
3
=
OSR f
s
2 f
B
OSR
9 dB 1.5
F
Q
z ( ) 1 z
1
( )
2
=
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 31
transfer function is obtained by substituting (2-39) into (2-34) and doing some simple
algebra. The second-order modulator loop lter transfer function is
. ( 2-40 )
The in-band power of quantization noise at the output of a second-order modulator is
[Candy92]
. ( 2-41 )
Doubling the reduces the quantization noise by , adding bits to the
resolution of a second-order modulator.
2.4.2 Bandpass Sigma-Delta Modulators
The basic principle of noise shaping can be extended by placing the quantization noise
nulls at an arbitrary center frequency . Then, the quantization noise will be pushed away
from the signal band ( ) at the desired center frequency.
A simple way of designing bandpass modulators is to perform a lowpass to bandpass
transformation. One such transformation in the discrete-time domain is achieved by the
following change of variable,
. ( 2-42 )
This transformation maps the zeros of the lowpass prototype from DC to .
Therefore, noise in the resulting bandpass modulator is suppressed around the and
the frequencies. The stability and SNR characteristics of this bandpass modulator
will be identical to that of the lowpass prototype [Jantzi].
In the following, the above transformation, equation (2-42), is applied to a rst-order
lowpass modulator . The resulting bandpass modulator, , is a second-order
modulator as expected from (2-42).
H z ( )
z
1
2 z
1
( )
1 z
1
( )
2
----------------------------- =
n
0
2
2
12
------

4
5
------
1
OSR
-----------
,
_
5
=
OSR 15 dB 2.5
f
0
BW
z
1
z
2

f
s
4 t
f
s
4
3 f
s
4
H
lp1
H
bp2
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 32
( 2-43 )
The above mapping is illustrated in Figure 2.12.
For a bandpass modulator with center frequency located at , the oversampling
ratio is simply .
The second-order modulator represented by (2-40) can also be transformed to a fourth-
order bandpass modulator as follows:
( 2-44 )
The stability of this fourth-order bandpass modulator is assured due to the
stability of the second-order lowpass prototype .
2.4.3 High-Speed SC Bandpass Sigma-Delta Modulator
Bandpass modulators allow A/D conversion to be performed on narrow-band signals at
IF (Intermediate Frequency) frequencies. These A/Ds are useful in some communication
systems, such as AM radio, digital radio, and in high speed modems. Digitizing the analog
signal at a high IF and processing the signal in the digital domain is desirable due to the
H
lp1
z
1
1 z
1

---------------- = H
bp2

z
2
1 z
2
+
----------------- =
BW
BW
0

OSR=f
s
/2BW OSR=f
s
/2BW
(a) (b)
Lowpass Bandpass
Figure 2.12: Pole/zero placement of (a) a rst-order lowpass and (b) a second-
order bandpass derived by transformation z
1
z
2

f
0
f
s
4
2 f
0
BW
H
lp2
z ( )
z
1
2 z
1
( )
1 z
1
( )
2
-------------------------------- = H
bp4
z ( )
z
2
2 z
2
+ ) (
1 z
2
+ ( )
2
------------------------------ =
H
bp4
H
lp2
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 33
robustness of digital circuits.
High-speed analog signal processing will be dominated by continuous-time Gm-C
[Shoaei94] or LC based circuits. These circuits typically require tuning circuitry which is
non-trivial. Recently, a high-speed bipolar sampled-data bandpass modulator has been
reported [Varelas96]. Here, we focus on high-speed SC implementation of bandpass
modulator using standard CMOS processes.
In the following, monolithic bandpass modulators reported in refereed publications are
discussed and their performances summarized.
The rst reported monolithic bandpass modulator was a fourth-order SC circuit with
optimally placed zeros for noise transfer function [Jantzi92]. This modulator was
implemented in a m, , double-poly analog CMOS process. It operated at a
clock and achieved a SNDR for signals at IF with a
bandwidth.
Another fourth-order SC bandpass modulator operating at a clock frequency
was reported in [Longo93]. This modulator has a transfer function similar to in
equation (2-44) and is implemented in a m double-poly CMOS technology. The
resonators are built using two SC delay cells in a negative feedback loop. Over a
bandwidth centered at , the measured SNDR is . This modulator operates
at and consumes mW.
A high-speed second-order SC modulator operating at a clock frequency of
was described by Singor and Snelgrove in [Singor94]. This modulator was implemented
in a m, double-poly BiCMOS technology. The transfer function of this modulator is
identical to in equation (2-43) and the resonator is implemented using LDI and FE
SC integrators. A performance of SNDR was achieved in a bandwidth
centered at , while dissipating from a power supply.
In [Song95], a hardware efcient fourth-order bandpass SC is described which
requires two opamps instead of four. The two opamps consume from a
power supply. This modulator is based on a 2-path system and is designed in a m
CMOS technology. The circuit is clocked at and the measured SNDR is in
3 5 V t
1.82 MHz 63 dB 455 kHz 10 kHz
7.2 MHz
H
bp4
1
30 kHz
1.8 MHz 75 dB
5 V 40
42.8 MHz
0.8
H
bp2
55 dB 200 kHz
10.7 MHz 60 mW 5 V
0.8 mW 3.3 V
2
8 MHz 56 dB
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 34
a bandwidth.
A 6th-order two stage (4-2) bandpass modulator is reported in [Hairapet96]. This
modulator uses a pseudo-two-path SC resonator with one opamp. A dynamic range of
is achieved for this bandpass A/D converter over a bandwidth of and an
IF frequency of . This modulator is implemented in a m CMOS
technology and consumes from a supply.
In [Norman96], a fourth-order bandpass modulator in a m BiCMOS
technology is reported. A dynamic range of is achieved for a signal bandwidth of
centered at in a medical ultrasound application. The architecture of this
modulator is based on a SC integrator.
Summary
Oversampled sigma-delta converters are compatible with VLSI technology due to their
architecture which contains simple analog circuitry followed by a complex digital signal
processing unit. A narrow-band signal at IF can be digitized using a bandpass
modulator. A simple transformation from lowpass to bandpass is achieved by a
change of variable.
2.5 Analog Circuit Design in a Standard Digital CMOS Process
As CMOS VLSI technology advances to ner geometries, more analog functions of a
mixed-signal chip nd economic solutions in the digital domain. Advantages of digital
circuits over analog include noise immunity, programmability, efcient scaling with
technology, availability of excellent automated design tools, and a systematic test strategy.
The boundary between digital and analog circuits is moving toward minimizing the
amount of analog circuitry. However, interfacing with the physical world requires analog
circuits at least for implementing A/D and D/A converters.
A cost effective implementation of mainly digital mixed-signal circuits requires the analog
circuits to be implemented in a standard digital CMOS process.
In CMOS, analog circuits are usually implemented using SC techniques due to their high
circuit accuracy. SC circuits are traditionally implemented in CMOS processes where
30 kHz
72 dB 200 kHz
3.25 MHz 0.8
7 mW 3 V
160 MHz 0.8
84 dB
2.5 MHz 5 MHz
z
1
z
2

Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 35
linear double-poly capacitors are available. Since a standard digital CMOS process does
not offer a second layer of polysilicon, therefore, the double-poly option requires a
process change to the mainstream digital CMOS technologies. In a predominantly digital
mixed-signal chip, the extra cost associated with the special double-poly process option
may not be justiable.
To address this problem, a new sampled-data analog signal processing technique, called
Switched-Current (SI) was proposed by Hughes [Hughes89]. This technique requires only
MOSFET transistors in a dynamic current circuit conguration to perform analog signal
processing. Thus, it is compatible with baseline digital CMOS technologies. However,
reported performance results for SI circuits indicate poor accuracy due to settling error
and charge injection. In a recent publication [Nedved95], 11 bits of resolution is measured
over the voice-band for a modulator operating at . For the same
modulator, SC circuits have achieved 14 bits.
In section 2.5.1, the SI technique is described and in section 2.5.2, two high performance
memory cells are discussed. Different techniques for implementing linear SC circuits in a
single-poly digital CMOS process are presented in section 2.5.3.
2.5.1 SI Circuit Technique
Signal processing in the analog sampled-data domain requires four operations on the
signals, namely: summation, inversion, scaling, and delay [Fiez90]. SC technique uses
MOSFET transistors and oating capacitors as basic components to realize these
operations.
A simple weighted current mirror, Figure 2.13, does the inversion, summation, and scaling
operations. The output current is given by
, ( 2-45 )
where is the aspect ratio ( ) of with respect to the aspect ratio of
.
A delay operation is achieved by adding a switch to a simple current mirror to isolate the
gates of the MOSFETs and as shown in Figure 2.14.
This current sample-and-hold circuit is called a rst generation memory cell [Hughes89]
5 V 1.024 MHz
i
o
i
o
n ( ) A i
1
n ( ) i
2
n ( ) + [ ] =
A W L N
2
N
1
N
1
N
2
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 36
and performs a half-delay operation. The transfer function of this circuit is
. ( 2-46 )
A non-inverting damped integrator is realized using a full delay cell (two half-delay cells
in cascade) in a feedback loop as shown in Figure 2.15 along with its corresponding 2-
phase non-overlapping clock.
The transfer function of this integrator is
, ( 2-47 )
which corresponds to the Forward Euler transformation ( ) of
I
B
AI
B
i
2
i
o
N1 N
2
1 A
i
1
Figure 2.13: A weighted current mirror
I
B
I
B
i
i
i
o
N
1
N
2
1 1
f
Figure 2.14: A rst generation memory cell
H z ( )
H z ( )
i
o
z ( )
i
i
z ( )
----------- z
1 2
= =
H z ( )
Az
1
1 Bz
1

-------------------- =
s 1 T 1 z
1
( ) z
1
[ ]
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 37
the following continuous time integrator.
( 2-48 )
is the DC gain and is the cut-off frequency.
The sampled data integrator of (2-47) corresponds to the continuous time integrator of (2-
48) with a phase shift ( ) [Battersby93] and
. ( 2-49 )
The sensitivity of with respect to variation in is dened as
. ( 2-50 )
The sensitivity of the cut-off frequency and DC gain with respect to variation in is
found to be:
( 2-51 )
Thus, the performance of this integrator with a low damping factor ( ) is very
sensitive to variation in the coefcient which is determined by transistor matching.
I
B
i
i
i
o
1 1
A B
AI
B
BI
B
1
Figure 2.15: First generation SI integrator

2
H s ( )
a
0
1
s

0
------ +
---------------- =
a
0

0
e
jT ( ) 2
a
0
A
1 B
--------------
0
2
T
-----
1 B
1 B +
---------------
,

_
= =
x y
S
y
x y
x
--
,
_
y
x
=
B
S
B
a
0 B
1 B
------------ = S
B

0 2B
1 B
2

--------------- =
B 1
B
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 38
The second generation memory cell [Hughes90], shown in Figure 2.16, solves the
MOSFET mismatch problem by utilizing the same transistor for sampling the signal as
well as holding it.
A lossless non-inverting integrator circuit constructed using a second generation SI
memory cell is shown in Figure 2.17. The transfer function of this circuit is
. ( 2-52 )
A damped non-inverting integrator is obtained by adding feedback to the lossless
I
B
i
i
i
o
Figure 2.16: Second generation SI memory cell
I
B
i
i
i
o
aI
B
1 1
a
Figure 2.17: A second generation non-inverting lossless integrator
N
H z ) (
z
1
1 z
1

---------------- =
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 39
integrator as shown in Figure 2.18.
The transfer function of the above damped integrator is
( 2-53 )
where
. ( 2-54 )
Cut-off and DC gain sensitivity with respect to and are
( 2-55 )
. ( 2-56 )
Both and exhibit low sensitivity to variations in and .
2.5.2 High Performance Memory Cells
An ideal SI memory cell must exhibit innite input conductance during the sampling
phase and innite output resistance during the hold phase. However, the simple
memory cell in Figure 2.16 has a nite input impedance and output resistance .
I
B
i
i
I
B
1 1
i
o
I
B

Figure 2.18: Second generation damped integrator
H z ( )
Az
1
1 Bz
1

-------------------- =
A

1 +
------------- B
1
1 +
------------- = =

S
B
a
0
1 = S
B

0
0 =
S
B
a
0
1 = S
B

0 2
2 +
------------- =

0

0

g
i
r
o
g
m
1 g
ds

Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 40

The accuracy of a SI circuit is proportional to . There are many circuit
techniques proposed to improve the accuracy of SI circuits. Here, two prominent methods,
regulated cascode [Toumazou90] and S
2
I [Hughes93] are discussed.
Regulated Cascode Memory Cell
The regulated cascode memory cell, illustrated in Figure 2.19, is based on a regulated
cascode current mirror [Sackinger87] that improves the output conductance of the
memory cell by a factor which is higher than that of simple cascoding.
This cell operates as follows. During the sampling phase the voltage on the gate of
reaches to maintain a drain current of . In the hold phase, the gate of is
isolated and the sampled current is fed to the output. The negative feedback loop formed
by transistors and keeps the voltage constant at a value of .
The input and output conductance of this circuit are
. ( 2-57 )
Compared to a simple current copier, the value of for a regulated cascode is higher
g
i
r
o
g
m
g
ds
=
I
B
i
i
i
o
N
1
N
2
N
3
I
B
Figure 2.19: Regulated cascode memory cell
N1
v
GS1
I
B
i
i
+ N1
N2 N3 v
DS1
v
GS3
g
i
g
m1
r
o
g
m2
g
m3
g
ds1
g
ds2
g
ds3
-------------------------------- - = =
g
i
r
o
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 41
by a factor of .
S
2
I Memory Cell
A two-step memory cell, called S
2
I cell, and its associated clock waveforms are shown in
Figure 2.20.
On phase , the coarse memory transistor is diode connected and the input current is
sampled. The bias current is provided by transistor during this phase. During , the
gate of is opened and its drain-source current will be sustained (parasitic holds the
gate to source voltage). Circuit non-idealities and charge injection from sampling switch
cause the stored current in to be different than the input current. The ne memory
transistor is now diode connected and will sample the difference between the actual
input current and the stored current . This difference is the error current caused
during the coarse sampling phase. On phase , the stored current (in ) is subtracted
from the error current (in ) and provides an error free output current .
2.5.3 Linear SC Circuit Techniques in a Digital CMOS Process
As previously discussed, implementation of the linear SC circuits requires linear oating
capacitors. In standard digital CMOS processes, where a linear double-poly capacitor is
not available, parasitic poly-to-metal or metal-to-metal capacitors may be used as linear
capacitors. The parasitic capacitance per unit area is typically low ( fF/m
2
)
compared to that of a poly-poly capacitor, which is fF/m
2
. The penalty of using
parasitic capacitances is the increase in silicon real estate (by a factor of almost 20) that
g
m2
g
m3
( ) g
ds2
g
ds3
( )
i
i
i
o
N
P

1a

1b

1a
V
B

1a

1b

2
Figure 2.20: S
2
I memory cell
S1
S2
S3
S4

1a
N
P
1b
N C
gs
S1 N
P
i
i
i
ds1

2
N
P i
o
0.05
1
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 42
may not be acceptable if the total capacitance used in the circuit is large.
Another type of capacitor available in CMOS processes is the MOSFET gate capacitor,
which is the one exploited in SI circuits. The capacitance per unit area of a MOSFET gate
capacitor is typically higher (by a factor of ) than the capacitance per unit area of
a poly-poly capacitor. However, MOSFET gate capacitance exhibits a non-linear behavior
as shown in Figure 2.21.
Reported research in the area of employing MOSFET gate capacitance to realize a linear
SC circuit is reviewed in the following section.
Weakly Non-linear MOSFETs
As can be seen from the CV characteristics of an nMOSFET shown in Figure 2.21, a
relatively linear capacitor is achieved by operating the MOSFET in strong inversion
( ) or accumulation ( ) regimes. Techniques to bias the MOSFETs in
strong inversion or accumulation to reduce distortion in the SC lter design were rst
reported in [Montoro88].
A theoretical analysis of the harmonic distortion caused by the weakly non-linear
MOSFET capacitors biased in strong inversion or accumulation is described in [Behr92].
It is shown that distortions due to these capacitors are technology independent. The
1.5 2.5
Figure 2.21: nMOSFET CV plot
5 0 5
0
0.2
0.4
0.6
0.8
1
(Volts) v
GB
(
N
o
r
m
a
l
i
z
e
d

g
a
t
e
-
s
u
b
s
t
r
a
t
e

c
a
p
a
c
i
t
a
n
c
e
)
C
G
B
C
o
x

Strong inversion Accumulation

v
GS
V
t
> v
GS
0 <
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 43
voltage coefcient (called in [Behr92]) for gate MOSFET capacitor is derived
from
, ( 2-58 )
where is the gate capacitance and is the gate to bulk voltage. For a MOSFET gate
capacitor biased at , the voltage coefcients in strong inversion and in the
accumulation region are given respectively by
( 2-59 )
. ( 2-60 )
Here, is the thermal voltage and is the at band voltage. A voltage capacitance
coefcient of is obtained for a MOSFET with a of , biased in
strong inversion.
A simple damped integrator circuit is used to test MOSFET capacitors. Measured THD
results are in good agreement with computed results showing that approximately
THD is achievable using a signal swing.
In another study [Schneider94], an explicit formula is derived for the harmonic distortion
in SC circuits with a weakly non-linear capacitor. It is shown that harmonic distortions as
low as to can be obtained in SC lters using MOSFETs biased in strong
inversion or accumulation as linear capacitors. A single-ended discrete SC biquad lter is
implemented, using a Motorola P5N40 transistor as capacitor, to verify the theoretical
analysis.
SC Circuits as Linear Charge Processors
In [Bermudez92], the basic operation of a SC circuit is considered as a charge mirror cell
composed of capacitors and an opamp. The charge processing is linear and is independent
of the non-linearity of the capacitors involved.
V
cc

1
C
g
------
v
GB
d
dC
g
=
C
g
v
GB
v
GB
V
R
=

str
2
t
V
R
V
t
( )
2
-------------------------- =

acc
2
t
V
R
V
FB
( )
2
------------------------------- =

t
V
FB
17 kppm/V V
t
0.8 V 2.5 V
40 dB
3 V
40 dB 60 dB
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 44
A charge mirror is shown in Figure 2.22. A charge injected at the inverting terminal of
the opamp will appear on capacitor with the following relationship between charge
and voltage:
. ( 2-61 )
A non-linear capacitor is described by [Lee85]
. ( 2-62 )
The parameter is the capacitance at zero voltage and is proportional to the area of the
capacitor.
The charge on capacitor , in Figure 2.22, is
. ( 2-63 )
If capacitors and have the same non-linearity function, then
. ( 2-64 )
This is a linear charge mirror and the gain is dened by the area ratio.
A typical SC building block which performs summation, scaling and delay operation on
two charge signals is shown in Figure 2.23.
In the charge domain, the operation is linear from input to output. If the external signals
are in the voltage domain, a linear input and output converters are required.
q
A
C
A
q
A
C
A0
f
A
v )v ( =
C
A
v
C
B
q
A
q
B
Figure 2.22: A charge mirror cell
C
X
C
X
C
X0
f
X
v ) ( =
C
X0
C
B
q
B
C
B0
f
B
v ( ) =
C
A
C
B
q
B
q
A
------
C
B0
C
A0
----------
area C
B
( )
area C
A
( )
------------------------ = =
V Q Q V
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 45
This means any capacitor connected to either inputs or output (voltage) must be a linear
capacitor.
A High-Linearity MOSFET SC Branch
A high-linearity SC circuit branch using MOSFET capacitors, proposed in [Yoshizawa95],
is shown in Figure 2.24. In this circuit, MOSFETs are biased in a weakly non-linear region
(accumulation) and the non-linearity effects are canceled to a rst-order, because the two
capacitors are connected in series and back-to-back.
This MOSFET capacitor branch can be used in a SC circuit as shown in Figure 2.25. An
expression similar to (2-61) is used for the weakly non-linear capacitors and and
it is assumed that . If , it can be shown that the charge
delivered by the SC branch during is
. ( 2-65 )
C
A
q
A
C
B
q
B
q
1
q
2
Figure 2.23: A SC building block

2
V
B
1
2
3
Virtual ground input (output)
Figure 2.24: The MOSFET SC branch
C
A
C
B
C
A0
C
B0
C = = V
in
2 V
B

2
q
C
2
---- f V
B
( )
v d
df
V
B
+ V
in
n ( ) =
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 46
Since is a constant voltage, the term in the bracket is a constant. Therefore, the
effective capacitance term is a constant and charge is a linear function of the
voltage.
An experimental SC amplier with a gain of was implemented using pMOS capacitors
in accumulation to verify the linearity of the above SC branch [Yoshizawa96]. For
and a input signal at , the largest harmonic was
below the fundamental of the input signal.
Summary
Sampled-analog circuits can be realized in standard digital CMOS process using SI or SC
circuit techniques. In SC design, linear capacitors can be achieved using parasitic poly-to-
metal or metal-to-metal capacitors or using MOSFET gate capacitors biased in strong
inversion or accumulation regimes.
2.6 A Comparative Study of SC and SI for Low-Voltage Applications
Supply voltage down-scaling was shown to be essential in future deep submicron VLSI
circuits to prevent problems caused by breakdown voltage, hot electron effects, and power
dissipation. A reduced supply voltage decreases the voltage signal swing which in turn
makes the design of high-speed wide dynamic range SC circuits a challenge. In SI circuits,
the signal is in the current domain and this originally led some researchers to believe that
the SI technique is more suitable for low-voltage analog design [Hughes90a] [Fiez90]
[Battersby91]. Further research [Crawley92] [Temes93] [Bazarjani93] indicated that SI
V
B
q V
in
n ( )
V
B
C
A
C
B
q
V
ip
Figure 2.25: A SC circuit using the MOSFET SC branch
V
op
10
V
B
1.5 V = 400 mVpp 1 kHz 72 dB
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 47
would not benet from supply voltage scaling. In this section, limits to low-voltage SC
and SI are explored and it will be shown that SI exhibits no clear advantage over SC for
low-voltage analog function. In fact, analysis of dynamic range (for a given supply
voltage) indicates that SC circuits achieve a higher dynamic range than SI circuits.
A SC circuit consists of capacitors, opamps, and switches and a SI circuit comprises
current mirrors and analog switches. In section 2.3, limits to low-voltage operation of the
opamp, switch, and current mirror were investigated. A transmission gate switch requires
a supply voltage of greater than . Both opamp and current mirror need a
supply voltage of greater than . Therefore, the minimum supply voltages
required for proper operation of either SC circuits or SI circuits are the same.
An important performance parameter for low-voltage operation is the maximum
achievable circuit dynamic range as dened by (2-25). For dynamic range comparison, the
SC integrator circuit shown in Figure 2.7 and the SI integrator circuit shown in Figure 2.17
are considered.
The maximum output voltage swing in the SC integrator is determined by the linear
voltage swing at the output of the opamp. For a two-stage opamp, as shown in Figure 2.26,
the maximum output voltage swing is
, ( 2-66 )
where is the minimum voltage needed to keep the output transistors and
in the opamp (Figure 2.26) in saturation. The noise in a SC circuit is limited by and
the circuit dynamic range is
. ( 2-67 )
In the SI circuit, during the sampling phase the minimum voltage on the gate of is
and the maximum voltage on the gate of can rise to , to keep in
saturation. The voltage signal swing on the gate of is
. ( 2-68 )
2V
t
2V
on
+
V
t
2V
on
+
V
swing opamp ( )
V
DD
2V
on
=
V
on
v
DS
N4 P3
kT C
DR
SC
V
DD
2V
on

8kT ( ) C
S

------------------------------ =
N
V
t
V
on
+ N V
DD
V
on
P
N
V
swing SI ( )
V
DD
V
t
2V
on
=
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 48
The minimum stored voltage on the gate capacitance of the nMOSFET transistor must
be greater than the thermal noise , where is the gate capacitance of . The
dynamic range of the SI integrator is
. ( 2-69 )
For example, assuming , , , and the
DR of the SC integrator is larger than the DR of the SI integrator.
2.7 Summary
In this chapter, CMOS scaling in deep submicron technologies was reviewed and it was
mentioned that supply voltage has started to scale down due to reliability issues. Along
with the supply voltage, threshold voltage must be scaled down to achieve high speed
circuits. Threshold voltage scaling issues due to non-scalability of subthreshold swing
were discussed. Limits to digital and analog supply voltage scaling were discussed and it
was shown that a large margin for supply voltage reduction exists for digital CMOS.
Dynamic power consumption in CMOS logic is reduced quadratically with supply voltage
V
in
V
ip N1
N2
N3
P1 P2
V
DD
V
op
V
b1
P3
N4
Figure 2.26: A two-stage pole-splitting opamp
N1
kT C
g
C
g
N1
DR
SI
V
DD
V
t
2V
on

8kT ( ) C
g

------------------------------------------ =
C
s
C
g
= V
t
0.6 V = V
DD
1.6 V = V
on
0.2 V =
6 dB
Chapter 2 Impacts of CMOS Scaling on Performance of Mixed-Signal Circuits 49
reduction factor. A rst-order analysis showed that for a given dynamic range and speed,
power consumption of an analog circuit is independent of the supply voltage. Research in
the area of low-voltage digital and analog circuits was presented.
Then, modulators, which are the benchmark circuits in this thesis, were introduced and
reported high-speed bandpass SC modulators were reviewed.
Finally, analog circuit techniques that allow mixed-signal circuit to be implemented in a
standard digital CMOS process were presented.
50
Chapter 3
Low-Voltage SC Design with Low-V
t
MOSFETs
In Chapter 2, CMOS scaling was reviewed and it was discussed that in deep submicron
technologies the supply voltage is scaling down to assure device reliability. In conjunction
with supply voltage, MOSFET threshold voltage must be reduced to attain high-speed
circuits. However, lowering the threshold voltage of MOSFET transistors will increase the
subthreshold off-current which raises the standby power dissipation in digital circuitry and
limits the accuracy of analog SC circuits. It was discussed that scaling the supply voltage
along with the threshold voltage reduces the total power dissipation in digital CMOS.
Low-voltage analog SC circuit techniques using low- MOSFETs are investigated in this
chapter.
Low- MOSFETs are available in advanced m CMOS technologies. This chapter
starts by presenting two different methods of achieving low- MOSFETs in the current
CMOS processes; the rst scheme may involves a process change, and the second method
uses circuit techniques. Accuracy degradation in SC circuits due to the subthreshold
leakage current of low- MOSFET transmission gate switch is analyzed next. Then,
methods for reducing the subthreshold leakage in analog switches are discussed and two
new switch topologies, the series transmission gate and composite switch [Bazarjani94b],
addressing this problem are proposed. Finally, the design and measured results for two
low-voltage SC modulators are presented. The rst design is a second-order
modulator designed in a m BiCMOS technology using short-channel ( m)
MOSFET switches. This modulator operates at a clock rate and achieves
V
t
V
t
0.1
V
t
V
t
2.25 V
0.8 0.6
2.5 MHz 92 dB
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 51
SNDR over the C-message weighted telephony bandwidth ( ). The second
design is a rst-order modulator implemented in a m CMOS process using
low- natural MOSFETs. This modulator is clocked at and has dynamic
range for an oversampling of (voice band ) and consumes about W.
3.1 A Low-V
t
Process
As channel lengths of MOSFET transistors are shrunk to m and below, buried-
channel pMOSFET devices with strong short-channel effects (SCEs) must be replaced
with surface channel devices. SCE is a combination of several 2-D phenomena in short
channel MOSFETs and is expressed as roll-off due to channel shortening [Tsividis87].
Fabrication of surface-channel MOSFETs requires a dual poly gate process technology
where n
+
-poly is used for nMOSFETs and p
+
-poly is used for pMOSFETs. In such
technologies, the natural threshold voltages of the transistors are set by the well implants
and are given by [Chen90],
( 3-1 )
where is the at-band voltage, is the bulk Fermi potential, is the device well
doping concentration, and is the gate specic capacitance. and are related to
process parameters and physical constants by
( 3-2 )
, ( 3-3 )
where is the xed charge density and is the gate-to-substrate workfunction. In an
n
+
/p
+
dual poly gate CMOS technology, the threshold voltages of the natural MOSFETs
are symmetric. This is due to the symmetrical gate-to-substrate workfunction of the
MOSFETs, as shown in Figure 3.1.
The for nMOSFETs and pMOSFETs are
60 Hz 5 kHz
1 V 0.5
V
t
1 MHz 54 dB
128 4 kHz 100
0.5
V
t
V
t
V
FB
2
F
2q
si
N
W
2
F
( ) C
ox
+ + =
V
FB

F
N
W
C
ox
V
FB

F
V
FB

MS
Q

C
ox
--------- =

F
kT
q
------
N
W
n
i
---------
,

_
ln =
Q

MS

MS
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 52
( 3-4 )
. ( 3-5 )
Here, is the bandgap energy which is about at room temperature and is
the charge of an electron that is .
Example 3.1: Assuming a xed charge density of q/cm
3
and device well dopings
of q/cm
3
, the natural threshold voltage of MOSFETs in a typical m CMOS
technology with gate oxide thickness of is found to be .
In some dual n
+
/p
+
poly gate processes [Sun92], it is possible to mask out the threshold
adjust implant and obtain the low- natural MOSFETs. In the next section, device
characteristics of an experimental CMOS process [Bazarjani95b] are described.
Experimental Natural MOSFETs
Natural threshold voltage CMOS transistors have been fabricated using a m CMOS
process. This process does not require any threshold adjust implant (for natural
MOSFETs). For operation, this process can be further simplied by eliminating the
steps required for hot-carrier reduction i.e., Lightly-Doped-Drain (LDD).
Vacuum Level
E
c
, E
F
E
c
E
i
E
F
E
v
E
v
E
i

si
n
+
-type SiO
2
p-type
E
c
E
c
E
i
E
F
E
v
E
v,
E
F
E
i

si
Vacuum Level
p
+
-type
SiO
2
n-type
nMOSFET pMOSFET
q
M
q
S
q
M
q
S
Figure 3.1: Gate-substrate workfunction of nMOSFET and pMOSFET in an
n+/p+ dual poly gate CMOS process
(Gate)
(Channel) (Gate)
(Channel)

MS
nMOSFET
E
g
2q
------
F
+
,
_
=

MS
pMOSFET
E
g
2q
------
F
+
,
_
=
E
g
1.124 eV q
1.602 10
19
C
2 10
10

4 10
16
0.5
12 nm V
t
220 mV =
V
t
1 V
0.5
1 V
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 53
The threshold voltages of m channel length nMOSFET and pMOSFET devices are
measured to be and respectively. Figure 3.2 and Figure 3.3 show the I
D
and G
m
versus gate voltage for a nMOSFET and a
pMOSFET biased at respectively.
Subthreshold slopes are measured to be as illustrated in Figure 3.4.
Summary
Low- natural threshold voltage MOSFETs can be fabricated as a by-product of a dual
0.5
202 mV 197 mV
20 m / 0.5 m 20 m / 0.5 m
V
DS
0.1 V =
0 1 2 3 4
0
0.5
1
1.5
2
2.5
3
3.5
4
x 10
4
I
D
G
m
I
D

(
A
)
,

G
m
(
A
/
V
)
V
DS
=0.1 V
V
GS
(V)
Figure 3.2: Measured I
D
(A) and G
m
(A/V) versus V
GS
(V) for
natural nMOSFET
4 3 2 1 0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
x 10
4
V
GS
(V)
I
D
G
m
|
I
D

(
A
)
|
,

G
m
(
A
/
V
)
V
DS
=-0.1 V
Figure 3.3: Measured |I
D
(A)| and G
m
(A/V) versus V
GS
(V) for
natural pMOSFET
78 mV/decade
V
t
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 54
poly gate CMOS process where the threshold voltage is set by a well implant. The natural
MOSFET is obtained by selectively shielding the threshold adjust implant or removing the
steps for threshold adjust for the whole wafer. Measured results, for a m technology,
indicate that typical values for and are about and
respectively. These low- natural MOSFETs are suitable for low-voltage ( )
mixed-signal design. In a dual- process, the low- transistors can be used to achieve
higher speed in digital circuits. In Chapter 5, application of a low- MOSFET to the
design of a high-swing linear MOSFET capacitor will be discussed.
3.2 Circuit Technique for V
t
Reduction
If a low- process is not available, circuit techniques must be used to reduce the
threshold voltage. In this section, methods of reducing the threshold voltage by
to are discussed.
(I) Low-Vt Short-Channel Devices: Taking advantage of SCEs
As the channel length of a MOSFET transistor is made smaller than a critical value
( ), several 2-D phenomena known as short channel effects (SCEs) will occur. The
onset of SCEs is empirically given [Brews80] by
|
I
D

(
A
)
|
V
GS
(V)
4 2 0 2 4
10
8
10
7
10
6
10
5
10
4
10
3
nMOSFET pMOSFET
Figure 3.4: Measured subthreshold characteristics of natural
nMOSFET and pMOSFET
0.5
V
t
S 200 mV 80 mV/decade
V
t
V
DD
1 V
V
t
V
t
V
t
V
t
100 mV
200 mV
L
min
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 55
. ( 3-6 )
Normally, process engineers select the minimum feature size of the technology ( ) to be
slightly greater than . One of the characteristics of short channel devices is that
threshold voltage rolls off quickly as channel length is reduced below . Figure 3.5
illustrates the threshold voltage as a function of channel length, for a generic m
CMOS technology, based on the charge-sharing model approximation formula
[Tsividis87] given by
. ( 3-7 )
Here, is the long channel threshold voltage, is the channel length, is the surface
potential at the onset of strong inversion which is approximately , and is a tting
parameter.
MOSFET transistors with channel lengths shorter than the minimum feature size of a
given technology (called short-channel MOSFETs hereafter), have lower threshold
voltages due to SCE. These short-channel MOSFETs can be used as efcient analog
L
min
8.8 r
j
t
ox
W
S
W
D
+ ( )
2
[ ]
1 3
=
L
0
L
min
L
min
1.5
V
t
L ( ) V
t0
1

1
L
------
2
si

B
qN
A
----------------
,

_
=
V
t0
L
B
2
F

1
0 1 2 3 4
0.3
0.4
0.5
0.6
0.7
0.8
L (m)
V
t
(
V
o
l
t
s
)
Figure 3.5: Threshold voltage as a function of channel length
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 56
switches [Bazarjani94a] due to higher (as a result of lower ), higher aspect
ratio( ) for the same width, and lower charge injection (based on channel length
reduction). However, undesirable SCEs, such as increased subthreshold conduction and
punchthrough current, set a limit to the minimum channel length acceptable for the short-
channel devices. Subthreshold conduction has been discussed before (section 2.2.2); in the
following punchthrough is briey discussed.
Short-channel MOSFETs are susceptible to barrier lowering that results in an unwanted
current ow from drain to source. This phenomenon is affected by and . Figure
3.6a shows a turned-off nMOSFET switch which is not affected by punchthrough. For
, the peak potential barrier is lowered if the channel length is not larger than the
sum of the two depletion region widths (source and drain to substrate), as shown in Figure
3.6b. The barrier is lowered further for (Figure 3.6c) because eld lines penetrate
from drain to source [Troutman79]. The resulting punchthrough current has a two
dimensional nature and no analytical model predicting it exists. Two dimensional
computer simulation and experiments show that punchthrough current decreases as is
lowered or negative bulk to source voltage is applied. In section 3.3, it will be shown that
in a SC circuit all of the off switches have both back bias and a maximum lower
than , which helps in reducing punchthrough current.
Channel length variation due to process uctuation must be carefully considered for short-
channel MOSFETs. A drawn channel length ( ) can vary by due to error in
V
on
V
t
W L
L v
DS
v
DS
0 =
v
DS
0 >
v
DS
v
DS
V
DD
2
V
D
V
SS
P-type B
V
ag
=V
DD
/2
V
SS
P-type
B
V
ag
=V
DD
/2
V
SS
P-type B
V
ag
=V
DD
/2
V
D
V
D
(a)
(b)
(c)
Figure 3.6: Turned-off nMOSFET switch exhibiting (a) no punchthrough,
(b) punchthrough due to short channel length, and (c) punchthrough due to
large drain to source potential
L
0
L
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 57
lithography and etching. For channel lengths below the minimum feature size in a given
technology, this variation might be larger. Thus, the optimum channel length must be
selected such that devices with the absolute minimum channel length obtained on silicon
have acceptable subthreshold and punchthrough currents.
(II) Substrate Forward Biasing
The threshold voltage of MOSFETs is a function of source to substrate voltage, owing to
the body effect and is given by
, ( 3-8 )
where is the body effect coefcient dened as
. ( 3-9 )
Application of a negative in nMOSFET (i.e. forward biasing the well potential with
respect to source) will reduce the threshold voltage. However, junction forward bias
current limits the maximum forward biasing to about .
Example 3.2: Assuming a of and , a forward bias voltage of
reduces the threshold voltage by about .
Summary
In a CMOS process with a normal , lower threshold voltage MOSFETs are obtained
using short-channel MOSFETs or by forward biasing the well.
3.3 Low-V
t
Transmission Gate Design for SC Circuits
In SC circuits, analog switches are implemented with MOSFET transistors having the
following two distinct modes of operation.
On State:
In this case, MOSFETs operate in strong inversion-triode mode with a non-linear signal
dependent on-conductance of approximately
V
t
V
t0

B
v
SB
+
B
( ) + =

2q
si
N
A
C
ox
------------------------- =
v
SB
0.4 V
0.5 V
1 2

B
0.8 V =
0.4 V 130 mV
V
t
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 58
, ( 3-10 )
where .
Off State:
A turned-off MOSFET transistor ( ) operates in the weak inversion regime and it
can be modelled as a current source with the following value:
. ( 3-11 )
Here, is the subthreshold swing (the gate voltage change needed to reduce the leakage
current by one decade), and is the value of the drain current when the gate to source
voltage of a unit transistor ( ) is set to and is given by
. ( 3-12 )
An analog switch has several requirements, the most important ones being: low on-
resistance, full signal swing handling, and low off-current.
A low on-resistance switch is obtained by using low- MOSFETs. Rail-to-rail signal
swing handling is achieved by using a full transmission gate (TG) switch also known as a
complementary switchan nMOSFET and a pMOSFET in parallel. Here, we focus on
the behavior of the off switches in the context of stray-insensitive SC circuits.
Consider a stray-insensitive non-inverting SC integrator and its corresponding two-phase
non-overlapping clock, as shown in Figure 3.7.
g
on
2 v
GS
V
t
( ) =
1 2 ( ) C
ox
W L ( ) =
v
G
0 =
i
off
I
D0
W
L
-----10
v
S
V
t
+ ( )
S
------------------------
=
S
I
D0
W L 1 = V
t
I
D0
C
ox

t
2
=
V
t
C
S
C
I
v
op

2
S1
S2
S3
S4
A B
v
in
Analog Ground = V
DD
/2
Figure 3.7: A non-inverting SC integrator
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 59
All the off switches have the following properties:
At least one side of any off switch is connected to analog ground, either directly or
through another switch. This is a critical property used in the development of a non-
leaky switch as described later.
The maximum drain to source voltage across an off switch is less than and
is given by
. ( 3-13 )
Note that during off-state, the drain to source voltages of MOSFET switches and
are almost zero. If the signal swing is limited to , the maximum
drain to source voltage of switches and will be
. ( 3-14 )
There is a negative back bias (bulk to source voltage for nMOSFET) on all the
switches. Again, assuming the signal swing is reduced by from each supply rail,
the minimum back bias voltage on MOSFET switches and is
. ( 3-15 )
Switches and have a back bias of .
The effects of low- leaky MOSFET switches on the precision of analog SC circuits will
be examined in the context of the non-inverting integrator illustrated in Figure 3.7. In this
circuit, we assume that switch is implemented with a full transmission gate and all the
other switches are simply nMOSFET transistors. In the following, error voltages on nodes
and due to nite on-resistance and off-current are analyzed for different periods of a
complete clock cycle.
(I) During
The equivalent circuit of the non-inverting SC integrator (Figure 3.7) during is shown
in Figure 3.8.
The leakage is the off-current through the nMOSFET switch and is calculated
V
DD
2
v
DS
max
max V
DD
2 ( ) v
in
min
v
in
max
V
DD
2 ( ) ,

' ;

=
S3 S4
V
on
v
in
V
DD
V
on
< <
S1 S2
v
DS
max
V
DD
2
----------- V
on
=
V
on
S1 S2
v
SB
V
on
=
S3 S4 V
DD
2
V
t
S1
A B

1
i
off 2
S2
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 60
from (3-11) to be:
( 3-16 )
This off-current is largest for a signal level closest to and causes an error voltage
( ) in the transmission of signal from to given by
, ( 3-17 )
where is the effective on-resistance of the complementary MOSFET
switch . The on-conductance is obtained from (3-10) as follows:
( 3-18 )
( 3-19 )
( 3-20 )
The error voltage ( ) is a non-linear function of the input signal and causes offset and
gain errors as well as distortion at the end of the cycle at the output. This error voltage is
proportional to and . reaches a maximum at about mid-rail (assuming
) and rises as the signal gets closer to . Since is exponentially
proportional to , the maximum value of occurs when reaches its maximum
value, i.e . Assuming nMOSFETs used in and have the same , the
maximum error voltage is
C
S
C
I
v
op
A B
v
in
R
on1
i
off2
R
on3
i
off4
Figure 3.8: Equivalent circuit of Figure 3.7 during
1
i
off 2
I
D0
W
L
-----10
v
in
V
tn
+
S
--------------------
,
_

=
V
SS
v
1
v
in
V
A
v
1
R
on1
i
off 2
=
R
on1
1 g
on1
=
S1 g
on1
g
on1
g
on1
nMOSFET
g
on1
pMOSFET
+ =
g
on1
nMOSFET
2
n
V
DD
v
in
V
tn
( ) = v
in
V
DD
V
tn
<
g
on1
pMOSFET
2
p
v
in
V
tp
( ) = v
in
V
tp
>
v
1
R
on1
i
off 2
R
on1

n

p
= i
off 2
V
SS
v
1
i
off 2
v
1
i
off 2
v
in
V
SS
= S1 S2 W L
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 61
, ( 3-21 )
where is the thermal voltage ( @ room temperature). This error
voltage is independent of device size and is determined solely by the process technology
parameters and the thermal voltage. For example, in a process with a threshold
voltage of and a subthreshold swing of the maximum error
voltage is about V.
A required dynamic range implies an upper limit on the error voltage, and from ( 3-21 )
one can nd the minimum required threshold voltage. In the same way, for a given
dynamic range and the maximum tolerable can be found. For example, a
SNR with a power supply of , and an on-resistance of requires an off-current
of less than .
Switch is biased at mid-rail (analog ground and virtual ground); thus, ideally there is
no potential across this switch and leakage off-current through it is zero. However, due to
non-idealities (nite opamp gain, etc.) there will be some voltage across switch . Since
this switch is biased at mid-rail, the subthreshold leakage is reduced by two different
actions; threshold increase due to body effect, and negative gate to source voltage. The
subthreshold leakage current will be
. ( 3-22 )
For some typical values , , and , a device with
and mV/decade will have a leakage off-current of about pA,
which is very small and comparable to junction leakage.
Non-Overlapping Period:
The equivalent circuit of the SC integrator during the non-overlapping period is shown in
Figure 3.9. As discussed in the previous section, the leakage off-currents through and
are negligible.
In this circuit, and are the parasitic capacitances from the top and bottom plate of
v
1
max

t
2
V
DD
V
t

-----------------------10
V
t
S
-----
=

t
kT q 25 mV =
1 V
200 mV 100 mV/decade
v
1
7.8
R
on
i
off
100 dB
1 V 10 k
1 nA
S4
S4
i
off 4
I
D0
W
L
-----10
V
DD
2 V
t
+
S
-----------------------------
,
_

=
W L 10 = I
D0
100 nA = V
DD
1 V =
V
t
180 mV = S 90 = 0.1
S3
S4
C
T
C
B
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 62
capacitor to ground. The sum of leakage currents through and is called ,
which is provided by and .
These leakage currents cause a change in charge across each capacitor as shown in the
above gure. The error charge across causes no net error at the output (this is a
stray insensitive conguration), because during node A is shorted to analog ground
and is dumped to ground. The error charges on capacitors and have
different polarities (during ) and as such cause no net error at the output.
During :
During the SC integrator has an equivalent circuit as shown in Figure 3.10. At steady
state, node will be at the virtual ground potential (similar to the negative input of the
opamp). Thus, leakage would be negligible. However, at the beginning of , the
voltage at node is changed suddenly from analog ground to . This can cause switch
to become leaky (for close to the source of will fall to resulting in
). Any charge lost by will cause an error voltage ( ) at the output given by
, ( 3-23 )
where is the time taken for the opamp to force back to virtual ground.
For example if and , an average leakage current of causes
an error voltage of V.
Another source of error during this phase is due to leakage current . Ideally, at the end
C
S
C
I
v
op
A
B
i
off
C
B C
T
+Q
T
-Q
T
+Q
T
-Q
T
+Q
B
-Q
B
i
B i
T
Figure 3.9: Equivalent circuit of Figure 3.7 during non-overlapping period
C
S
S1 S2 i
off
i
T
i
B
Q
B
C
B

2
Q
B
Q
T
C
S
C
T

2
B
i
off 3

2
B v
in

S3 v
in
V
DD
S3 V
SS
v
GS
0 = S3 v
2
v
2
1
C
S
------ i
off 3
t d
0
t

=
t V
B
C 1 pF = t 5 ns = i
off
1 nA
V
2
5 =
i
off 1
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 63
of node must be at the analog ground potential. Leakage current and on-
resistance cause an error voltage on node which is given by
( 3-24 )
Assuming the input voltage is close to and nMOSFET transistors in and have
the same , the error voltage is
. ( 3-25 )
Again, maximum error occurs for close to or . The maximum error caused
during this phase ( ) is larger than the maximum error caused during , (3-21),
because of the higher on-resistance in (3-24).
Summary
Low- MOSFETs are leaky and limit the accuracy of SC circuits. The error caused
during sampling is process dependent. For a process with a threshold voltage of
and a subthreshold swing of , the sampling error is V which
limits the accuracy to about .
3.4 Series Transmission Gate and Composite Switch
As described in the previous section, subthreshold off-current through analog switches
implemented with low threshold voltage MOSFETs introduces errors in SC circuits and
reduces the dynamic range of the analog circuit.
C
S
C
I
v
op
A B
v
in
i
off1
R
on2
i
off3
R
on4
Figure 3.10: Equivalent circuit of Figure 3.7 during
2

2
A i
off 1
R
on2
A
v
3
i
off 1
R
on2
=
V
SS
S1 S2
W L
v
3

t
2
V
DD
2 ( ) V
t

--------------------------------10
V
t
v
in
+
S
------------------
=
v
in
V
SS
V
DD

2

1
V
t
1 V
100 mV 100 mV 156
76 dB
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 64
A method of reducing the off-current is by limiting the signal swing. If the signal swing is
reduced by from each rail, the subthreshold off-current ( 3-11 ) will be reduced by
decades. Notice that for a (which may be required for drain-source
saturation voltage in the amplier) and , the off-current is reduced by
more than times.
Measurements of vs. for a nMOSFET with a threshold
voltage of are shown in Figure 3.11 for two different values of and
. The drain to source voltage is set to in both measurements. Note that the
leakage off-current ( at ) is reduced from Ato nA by applying a
negative gate-to-source voltage of (i.e., limiting the signal swing).
Another way of reducing the subthreshold off-current is by adjusting through back
bias. A major problem with low- MOSFET transistors is the threshold voltage variation
due to processing errors (about ) [Mizuno94] and temperature uctuation (about
). These can have a compounding effect and increase the off-current
drastically. A technique of setting the to a constant value, by adjusting the substrate
V
V S V 200 mV =
S 90 mV/decade =
100
i
DS
v
GS
W L 20m 0.5m =
130 mV v
SB
0 =
0.2 V 0.1 V
Figure 3.11: Measured i
DS
vs. v
G
for an nMOSFET with V
t
=130 mV and
v
S
=0 (solid line) and v
S
=0.2 V (dotted line)
v
G
(V)
i
D
S

(
A
)
1 0 1 2 3
10
14
10
12
10
10
10
8
10
6
10
4
10
2
W/L=20 m/0.5 m
v
B
=0
v
DS
=0.1 V
i
DS
V
G
0 = 2.38 20
200 mV
V
t
V
t
100 mV t
1.25 mV/C
V
t
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 65
voltage, has been discussed in section 2.2.2.
In low-voltage design we can not afford to limit the signal swing by more than
, the minimum required drain-to-source saturation voltage in the amplier.
If the threshold voltage is very low, limiting the signal swing may not decrease the off-
current enough and other techniques ought to be exploited.
3.4.1 Series Transmission Gate Switch
In section 3.3, it was shown that in a stray insensitive SC circuit off switches have one
side connected to analog/virtual ground (either directly or through another switch). An
nMOSFET switch during the off-phase is shown in Figure 3.12a.
For a the subthreshold leakage off-current through the nMOSFET switch is
low because of the negative gate to source voltage and an increase in due to back bias.
The current is,
( 3-26 )
where
. ( 3-27 )
However, as voltage drops below , subthreshold leakage increases
exponentially and reaches a maximum for . In this case the exponent
( ) is small for low- devices and results in a large off-current.
A turned-off pMOSFET switch (Figure 3.12b) has the opposite behavior; the off-current is
150 200 mV
(a) (b)
Figure 3.12: Turned-off (a) nMOSFET and (b) pMOSFET switches
V
ag
=V
DD
/2
V
A
=0
V
ag
V
A
=1
V
A
V
DD
2 >
V
t
i
off
i
off
I
D0
W
L
-----10
P
=
P
V
DD
2 V
t
+
S
------------------------------- =
V
A
V
DD
2
V
A
V
SS
=
P V
t
S = V
t
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 66
low for below and the largest off-current ows for .
A very low leakage switch (with one side tied to analog ground), is obtained by a series
transmission gate switch as shown in Figure 3.13. The maximum subthreshold leakage
off-current through this switch is similar to an nMOSFET switch with , as
analyzed previously.
Figure 3.14 illustrates the simulated subthreshold leakage current through an nMOSFET
and a series transmission gate (STG) switch. Threshold voltages of MOSFETs are set to
and transistor sizes are .
The leakage off-current through the STG switch is very low (~ ) while a low-
nMOSFET has a relatively high leakage off-current (~ A) for low input voltages.
V
A
V
DD
2 V
A
V
DD
=
V
A
V
DD
2 =
Figure 3.13: A series transmission gate switch
V
ag
V
A
=1 =0
N P
110 mV W L ( )
p
2 W L ( )
n
10 = =
0 0.2 0.4 0.6 0.8 1
10
15
10
14
10
13
10
12
10
11
10
10
10
9
10
8
10
7
10
6
Input Voltage V
A
(Volts)
L
e
a
k
a
g
e

o
f
f
-
c
u
r
r
e
n
t

(
A
m
p
)
Figure 3.14: Leakage off-current through an nMOSFET switch (dotted line)
and a STG switch (solid line) versus input voltage
1 pA V
t
0.1
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 67
The on-conductance of the series transmission gate switch is
. ( 3-28 )
For and , the maximum on-conductance for a STG occurs at
. This is exactly where all the switches to analog ground are operating. The
maximum on-conductance of a series transmission gate is
, ( 3-29 )
which is lower than the on-conductance of a simple nMOSFET by a factor of 2.
Simulation for on-conductance, Figure 3.15, conrms the validity of the above analysis.
A drawback of the series transmission gate switch is the limited input signal swing. This
switch cannot conduct signals that are within a of the supply rails. In the next section, a
solution to this problem is presented.
3.4.2 Composite Switch
In a multi-threshold process, the high- (threshold adjusted) transistors can be used in a
g
on
2
n
V
DD
V
tn
V
in
( )
p
V
in
V
tp
( )

n
V
DD
V
tn
V
in
( )
p
V
in
V
tp
( ) +
--------------------------------------------------------------------------------------------- =

n

p
= V
tn
V
tp
V
t
= =
V
DD
2
g
on max ( )
STG

V
DD
2
----------- V
t

,
_
=
0 0.2 0.4 0.6 0.8 1
0
2
4
6
8
x 10
4
Input Voltage V
A
(Volts)
O
n
-
c
o
n
d
u
c
t
a
n
c
e
g
o
n

(
1
/

)
Figure 3.15: On-conductance of the nMOSFET (dotted-line) and
STG switch (solid-line) versus input signal
V
t
V
t
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 68
parallel transmission gate (TG) conguration along with the series transmission gate
switch to handle rail-to-rail switch capability. The composite switch is shown in Figure
3.16 (the adjusted MOSFETs are shown with bold lines in the channels).
The simulated on-conductance of the composite switch is shown in Figure 3.17. In this
conguration, the high- parallel transmission gate conducts well when the signal is
V
t
V
ag
V
A

Figure 3.16: A composite switch

0 0.2 0.4 0.6 0.8 1
0
2
4
6
x 10
4
Figure 3.17: Simulated on-conductance for high-V
t
TG switch (dashed-line), low-Vt
series transmission gate switch (dotted-line), and the composite switch (solid-line)
versus input signal
Input Voltage V
A
(Volts)
O
n
-
c
o
n
d
u
c
t
a
n
c
e
g
o
n

(
1
/

)
V
t
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 69
close to the rails, and the low- series transmission gate conducts well when the signal is
at mid-rail. The on-conductance and leakage through this composite switch is simulated
along with simple high- and low- parallel transmission gates and all three are
illustrated in Figure 3.18 and Figure 3.19.
V
t
V
t
V
t
0 0.2 0.4 0.6 0.8 1
10
6
10
5
10
4
10
3
Input Voltage V
A
(Volts)
O
n
-
c
o
n
d
u
c
t
a
n
c
e
g
o
n

(
1
/

)
Figure 3.18: On-conductance for high-V
t
TG switch (dashed-line), low-V
t
TG
switch (dotted-line), and the composite switch (solid-line) versus input signal
0 0.2 0.4 0.6 0.8 1
10
15
10
14
10
13
10
12
10
11
10
10
10
9
10
8
10
7
10
6
Input Voltage V
A
(Volts)
L
e
a
k
a
g
e

o
f
f
-
c
u
r
r
e
n
t

(
A
m
p
)
Figure 3.19: Leakage current for high-V
t
TG switch (dashed-line), low-V
t
TG
switch (dotted-line), and the composite switch (solid-line) versus input signal
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 70
Summary
Subthreshold off-current through MOSFET switches is reduced by (1) limiting the signal
swing, (2) adjusting the by back bias, and (3) using low-leakage series transmission
gate and composite switch.
3.5 A 2.25 V Second-Order Sigma-Delta Modulator
This modulator is based on an existing SC oversampled double integration
sigma-delta modulator [Howlett93] in BATMOS, Northern Telecoms m BiCMOS
process [Hadaway91]. The design operates at and achieves SNDR
for an oversampling ratio of . Simulations indicated that the characteristic of the
amplier and comparator blocks used in this modulator are not signicantly degraded at
. The modulator performance was limited by the increase in switch resistance at
. This has been remedied by using short-channel MOSFET switches. At
the SNDR of the original design drops to . However, the modied design using
channel length MOSFET switches achieves of SNDR at .
Unfortunately, a two-stage BiCMOS opamp is used in this modulator which can not
operate below . Thus, in-circuit low-voltage performance of these short-channel
switches can not be veried below .
The block diagram of this modulator is similar to the one in [Boser88] and it is a
differential SC design, implemented using two single-ended opamps.
3.5.1 Short-Channel MOSFETs
Medici, a 2-D device simulator, was used to nd the minimum achievable channel length
for short-channel MOSFETs with acceptable punchthrough current in BATMOS.
Measurements were also carried out on different sizes of short-channel MOSFETs to
verify the simulation results and MOSFETs with channel length of m were found
reliable as low-voltage switches.
Characteristics of different short-channel MOSFETs (all with )
were measured for both nMOSFET and pMOSFET transistors. At supply voltage of ,
the on-resistances of switches biased at mid-rail ( and ) were
measured. Results are shown in Table 3.1.
V
t
2.25 V 3.3 V
0.8
3.3 V 2 MHz 94 dB
256
2.25 V
2.25 V 2.25 V
86 dB
0.6 m 92 dB 2.25 V
2.25 V
2.25 V
0.6
W L 10 m 0.6 m =
3 V
v
SB
1.5 V = v
DB
1.6 V =
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 71
Further measurements of the m nMOSFET switch show that of is
achieved with a supply voltage of .
Figure 3.20 illustrates the versus characteristic of an nMOSFET with m
channel length under two different conditions.
Since the turn-off leakage ( at ) is of prime importance to us, versus
is also measured for the same device (a m nMOSFET), with different back bias
voltages. It is seen (Figure 3.21) that extremely low current leakage is obtained by setting
the back bias to . Both Figure 3.20 and Figure 3.21 show current per micron of
width of the transistor.
Measurements of a m pMOSFET device gave similar results.
Transistor
Type
Reduction
L=0.8 m L=0.6 m
nMOSFET 1.3 K 0.709 K 45%
pMOSFET 5.8 K 3.2 K 44%
Table 3.1: On-resistance of switches with W=10m
R
on
0.6 R
on
1.2 k
2.1 V
i
DS
v
GS
0.6
v
DS
Gate voltage (Volts) v
GS
D
r
a
i
n

c
u
r
r
e
n
t

(
A
m
p
)
i
D
S
0 0.5 1 1.5 2 2.5 3 3.5
10
12
10
11
10
10
10
9
10
8
10
7
10
6
10
5
10
4
10
3
10
2
v
DS
=0.1
v
DS
=2
W/L=1/0.6
Figure 3.20: Drain current versus gate voltage for a 0.6 m nMOSFET with
v
DS
=0.1 V (solid line) and v
DS
=2 V (dashed line)
i
DS
v
G
0 = i
DS
v
DS
0.6
0.5 V
0.6
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 72
3.5.2 Short-Channel MOSFETs Layout Issues
Channel length variation due to processing errors (lithography and etching) is very critical
for short-channel MOSFETs and must be minimized. Some layout techniques that help to
reduce the 3 (inter die and intra wafer) channel length variations are as follows.
Place the structure of interest close to the center of the die; thereby ensuring the best
possible optical and focus performance.
Maintain symmetry around the structure of interest to ensure similar resist ow/
planarization from all directions [Gehm92].
Keep all the underlying steps (e.g., device well edges) as far away from the area of
interest as is feasible.
3.5.3 Measured SNDR
The second-order modulator using short-channel MOSFET switches was fabricated in
BATMOS and the measured SNDR is shown in Figure 3.22. Zero dB input level
corresponds to a peak-to-peak signal. This modulator operates at and has a
maximum SNDR of for an oversampling ratio of . The SNDR of the original
design drops to at supply voltage.
0 0.5 1 1.5 2 2.5 3 3.5
10
14
10
13
10
12
10
11
10
10
10
9
10
8
v
SB
=0.5
v
SB
=0
W/L=1/0.6
Drain to source voltage (V) v
DS
D
r
a
i
n

l
e
a
k
a
g
e

c
u
r
r
e
n
t

(
A
m
p
)
i
D
S
Figure 3.21: Drain off-current (v
G
=0) versus drain to source voltage for a 0.6 m
nMOSFET with v
SB
=0 (solid line) and v
SB
=0.5 V (dashed line)
1.5 V 2.25 V
92 dB 256
3.3 V 86 dB 2.25 V
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 73
3.6 A 1 V First-Order Sigma-Delta Modulator
In a low supply-voltage environment, fully differential circuits are preferred due to larger
dynamic range, elimination of second harmonic distortions, and the tolerance to various
common mode noises. This design was done at the early stages of process development
and the CAD tools had very limited capability. Thus, a simple single-ended rst-order SC
modulator was chosen as a benchmark to demonstrate the feasibility of using natural
MOSFETs for SC design. To our knowledge, this is the rst reported SC
modulator operating at a power supply voltage of [Bazarjani95a].
The architecture of a rst-order SC modulator is shown in Figure 3.23. It consists of a
discrete integrator and a two level quantizer in a negative feedback loop.
This modulator was implemented in a m n+/p+ dual poly gate CMOS process using
natural threshold voltage MOSFETs. The natural transistors in this process have threshold
voltages of about which is suitable for circuits. In the following, design of
opamp, comparator and switches used in this circuit is discussed along with some
simulation and measured results.
100 80 60 40 20 0 20
20
0
20
40
60
80
100
Input level (dB)
S
N
D
R

(
d
B
)
Figure 3.22: Measured modulator performance
1 V
1 0.1 t V
0.5
200 mV 1 V
1V
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 74
3.6.1 1 V opamp
Lowering the power supply voltage directly reduces the dynamic range and consequently
the accuracy of the analog circuitry. Thus rail-to-rail signal swing is desired to maximize
the dynamic range. In a SC circuit, signals at the inputs of the opamp are at analog ground,
thus no input signal swing is required. However, the output(s) of the opamp must provide
the largest possible signal swing. Each transistor at the output stage requires a certain
voltage to be kept in saturation ( ) which limits the output signal swing.
Therefore, cascode structures are avoided at the output stage of the amplier. A two-stage
pole-splitting opamp, Figure 3.24, provides enough gain and maximum signal swing at the
output of the amplier.
In this opamp, the bias current is set to A and the compensation capacitor is
. The dimensions of all the MOSFETs are listed in Table 3.2.
This opamp was simulated in Eldo [Eldo] using MISNAN, a physically based MOSFET
MOSFET N1 N2 N3 N4 P1 P2 P3 P4 P5 P6
W(m) 10 10 10 2 120 120 60 60 4 60
L(m) 1 1 1 1 0.5 0.5 1 1 1 1
Table 3.2: Dimension of MOSFETs used in the opamp of Figure 3.24
V
rp
V
rn
V
ip
V
op
V
op
V
op
C
2C
Figure 3.23: A rst-order SC modulator
v
DS
v
GS
V
t
>
I
bias
10 C
c
2 pF
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 75
model [Boothroyd92]. The device model parameters were obtained from [Tarr95], where
parameters are estimated using SUPREM3 and MINIMOS5 simulations.
The overall simulated opamp performance at power supply voltage and load is
summarized in Table 3.3.
3.6.2 Comparator
In modulators the performance of the comparator is not critical. A class AB
comparator similar to [Boser88] is used here. Figure 3.25 illustrates the schematic of this
Parameter Result
DC gain 60 dB
Unity gain bandwidth 40 MHz
Phase Margin 60
Slew rate 10 V/s
Output range 0.5 V
Power Dissipation 30 W
Table 3.3: Simulated opamp performance for a 1 pF load capacitance
V
in
C
c
I
bias
V
op
N1 N2
N3
N4
P1 P2
P3
P4 P6
P5
V
ip
Figure 3.24: A two-stage pole-splitting opamp
1 V 1 pF
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 76
comparator. Simulations indicate a delay of is achieved at a power supply for a
load capacitance.
All the transistors sizes for this comparator are listed in Table 3.4.
3.6.3 Switches
As previously discussed, a good analog switch will exhibit a low on-resistance when
turned on and a very low off-current when turned off. In this SC design, switches are
implemented with complementary low- natural MOSFETs. A transmission gate switch
with for both nMOSFET and pMOSFET was simulated in
Eldo at supply voltage. Figure 3.26 shows the on-resistance of the transmission gate
switch as a function of the input signal level.
A worst case on-resistance of is obtained for a signal level of . In the SC
circuit of Figure 3.23 two of these switches and the sampling capacitor constitute an RC
circuit. For the sampling capacitor of the time constant will be . Settling to
MOSFET N1 N2 N3 N4 N5 N6 N7 N8 P1 P2 P3 P4 P5 P6
W (m) 10 10 10 10 5 5 10 10 3 30 30 3 10 10
L (m) 2 2 2 2 0.5 0.5 0.5 0.5 0.8 2 2 0.8 0.5 0.5
Table 3.4: Transistor sizes for the comparator
6 ns 1V
1 pF
V
op
V
on
V
in
V
ip
CK
N1 N2 N3 N4
N5 N7 N6 N8
P1 P2 P3 P4
P5 P6
Figure 3.25: Schematic of the comparator
V
t
W L 1.5 m 0.5 m =
1 V
12 k 790 mV
1 pF 24 ns
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 77
0.1% of the full scale requires ( ) allowing an upper limit of operation
for this switch.
The subthreshold off-current of these switches can be calculated from the simplied
equation of (3-11). In this process, typical values of and for an nMOSFET are
and respectively.The nMOSFET
switch will have less than subthreshold leakage current for a signal at .
However, the minimum signal in this modulator is about . Therefore, the
maximum leakage current through the above nMOSFET switch (when the signal is
) is less than . Simulation of the leakage current through a natural
nMOSFET transistor is shown in Figure 3.27 and the results correlate well with the above
analysis.
3.6.4 Measured Results for the 1 V Sigma-Delta Modulator
The modulator was fabricated in a m n
+
/p
+
dual poly gate CMOS process with a
linear poly-poly capacitor and triple level metal CMOS process. The chip die photograph
is shown in Figure 3.28.
The modulator was tested at a clock frequency of using a supply voltage and
reference voltages of (with respect to analog ground, ). The output
0 0.2 0.4 0.6 0.8 1
2000
4000
6000
8000
10000
12000
14000
Input signal (V)
O
n
-
r
e
s
i
s
t
a
n
c
e

(

)
Figure 3.26: Simulated transmission gate switch resistance as a
function of input signal
168 ns 7 3 MHz
I
D0
S
100 nA 86 mV/decade W L 1.5 m 0.5 m =
1 nA V
SS
0.25 V
0.25 V 10 pA
0.5
1 MHz 1 V
0.25 V t 0.5 V
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 78
spectrum for an input signal of and is shown in Figure 3.29.
The output bit-stream was captured by a logic analyzer and 131072-point FFT was
performed in Matlab [Matlab]. For an oversampling of , a SNDR of is
obtained.
3.7 Summary
In this chapter, a process technology and two circuit techniques for achieving low-
MOSFETs in current CMOS processes were presented. Effects of low- subthreshold
V
GB
(V)
I
D
S
(
A
)
0 0.2 0.4 0.6 0.8 1
10
11
10
10
10
9
10
8
10
7
10
6
10
5
10
4
V
S
=0
V
S
=0.2 V
V
D
=0.5 V
Figure 3.27: Simulated off-current for the nMOSFET switch
Figure 3.28: Chip die microphotograph
4 kHz 420 mVpp
128 54 dB
V
t
V
t
Chapter 3 Low-Voltage SC Design with Low-V
t
MOSFETs 79
leakage currents to the precision of analog SC circuits were analyzed. It was shown that
off-current leakage through MOSFET switches reduces the accuracy of SC circuits.
Methods of reducing the leakage current through analog switches were discussed and two
very low leakage analog switches suitable for SC circuits were proposed.
Finally, two experimental low-voltage voice-band modulators using low-
MOSFETs were described. In the rst design, an existing modulator designed
in m BiCMOS process was modied using short-channel MOSFET as switches
and the new design operates at . The second design is a SC modulator
using low- natural MOSFETs in a m CMOS technology.
10
2
10
0
10
2
10
4
120
100
80
60
40
20
0
KHz
M
a
g
n
i
t
u
d
e

(
d
B

r
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
Figure 3.29: Measured spectrum (Vip = 420 mVpp)
V
t
3.3 V
0.8
2.25 V 1 V
V
t
0.5
80
Chapter 4
High-Speed SC Fourth-Order Bandpass
Sigma-Delta Modulators
In Chapter 2, a method of transfer function design for a bandpass modulator from a
lowpass modulator using a change of variable was discussed. It was also
mentioned that the stability and SNR characteristics of the resulting bandpass
modulator are identical to those of the lowpass prototype.
This chapter starts by introducing a -domain architecture for a fourth-order bandpass
modulator. This modulator is obtained by performing the above mapping to a second-
order (double integration) lowpass modulator. The resulting bandpass modulator is a
double-resonator modulator. In the sampled-data domain, an efcient method of
implementing resonators uses two delay cells in a negative feedback loop. Switched-
capacitor delay circuits are considered next and a double-sampled SC delay cell is
presented. The impacts of non-ideal circuit behaviors on the performance of a simple SC
delay cell and the double-sampled SC delay circuit are analyzed. Then, two SC
implementations of the fourth-order bandpass modulatornamely a simple SC
structure and a double-sampled SC architectureare presented along with Eldo
simulation results. Finally, the design of both modulators in a m CMOS process is
considered and measured results of the modulators are presented.
4.1 Modulator Architecture
The loop lter transfer function for a fourth-order bandpass modulator was derived in
Chapter 2, and is
z
1
z
2

z
0.5
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 81
. ( 4-1 )
Assuming the quantization error to be white noise and the comparator gain to be unity,
the output-input transfer characteristic of this modulator is
. ( 4-2 )
Lowpass modulators are usually implemented as a cascade of integrators. A natural
choice for bandpass modulators seems to be a cascade of resonators. One such architecture
is shown in Figure 4.1. The quantizer is typically implemented using a 1-bit comparator
with two levels at . The -domain transfer function of this modulator is
. ( 4-3 )
Comparing equations (4-2) and (4-3), the values of and are found to be and
respectively. Since the second resonator is followed by a high gain quantizer, the
coefcient is irrelevant [Boser88] and is set to , as is the coefcient of the rst
stage. This architecture is a direct map of the lowpass modulator in [Boser88] to
bandpass by transforming integrators to resonators. Analogous to the lowpass prototype,
the signal swings at the output of the resonators are almost within the full scale input
range, . Figure 4.2 illustrates the histograms of the signal levels at the output of the
resonators for an input signal of below full scale (i.e., the peak-to-peak signal
amplitude is ). We use statistical techniques to characterize signal swings, because
sigma-delta modulators produce pseudo-random outputs.
The noise transfer function of this modulator has a pair of complex conjugate zeros
H
bp4
z ( )
z
4
2z
2
+
1 z
2
+ ( )
2
------------------------- =
e
Y z ( ) z
4
X z ( ) 1 z
2
+ ( )
2
E z ( ) + =
k1

z
2
1 z
2
+
-----------------
+
-
k2

z
2
1 z
2
+
-----------------
+
+
x y
Figure 4.1: A fourth-order double resonator bandpass modulator
V
ref
t z
1 2 k2 ( )z
2
1 k1k2 k2 + ( )z
4
+ + [ ]Y z ( ) k1k2z
4
X z ( ) 1 z
2
+ ( )
2
E z ( ) + =
k1 k2 0.5 2
k2 0.5
V
ref
t
6 dB
V
ref
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 82
located at . In the frequency domain, this corresponds to notches around
, where , ..., and is the sampling frequency. The -domain
simulated output spectrum of this modulator is shown in Figure 4.3.
The noise shaping is clearly seen at around a quarter of the sampling frequency. As we
discussed in Chapter 2, this fourth-order modulator is guaranteed to be stable because of
Resonator outputs ( ) V V
ref

P
r
o
b
a
b
i
l
i
t
y

D
e
n
s
i
t
y
Figure 4.2: Histograms of output levels for the rst (solid line) and
the second (dashed line) resonator for a -6 dB tone input
1.5 1 0.5 0 0.5 1 1.5
0
0.02
0.04
0.06
0.08
0.1
0.12
z j t =
2n 1 + ( ) f
s
4 n 0 1 2 , , = f
s
z
Normalized frequency ( ) f f
s

N
o
r
m
a
l
i
z
e
d

p
o
w
e
r

(
d
B

r
e
l
a
t
i
v
e

t
o

f
u
l
l

s
c
a
l
e
)
Figure 4.3: Simulated output spectrum of the fourth-order
bandpass modulator in Figure 4.1 for a sinusoidal input.
0 0.1 0.2 0.3 0.4 0.5
180
160
140
120
100
80
60
40
20
0
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 83
the stability of the second-order lowpass prototype.
The resonator can be implemented in several different ways using SC techniques. In
[Singor94], resonators are implemented using Lossless Discrete Integrators (LDI) and
Forward-Euler (FE) integrators. Another approach is to use two delay cells in a negative
feedback loop [Longo93], as shown in Figure 4.4.
The latter design is chosen here for SC implementation because: (1) it operates at a higher
speed [Singor94], (2) an SC delay circuit is immune to capacitor non-linearity
[Bazarjani95c] which is useful when a SC circuit is implemented by weakly non-linear
MOSFET capacitors and (3) a variation of this architecture can be implemented using a
high-speed bipolar sample-and-hold circuit [Varelas96].
4.2 Half Delay SC Circuits
There are many SC amplier designs that contain a half delay in their operation
[Gregorian86]. Some involve techniques to reduce DC offset and noise
[Gregorian81], others utilize gain-enhancing methods to compensate for low opamp DC
gain [Haug84].
Here, the delay cell is intended to be used in a bandpass modulator, thus, offset and
noise do not affect the performance of the circuit. Moreover, sampled-data
modulators typically require moderate opamp DC gain (opamp DC gain must be
comparable to the oversampling ratio) and, as such, a gain-compensation scheme may not
be needed. A simple SC amplier is used for speed considerations.
The circuit of a fully differential SC amplier is shown in Figure 4.5a. A two-phase non-
overlapping clock, as shown in Figure 4.5b, is required for the operation of this circuit.
The output is delayed by a half-clock period and has a gain of . Assuming innite
opamp DC gain and denoting the differential input and output by and , where
f
s
4

+
-
x
z
1
z
1
y
Figure 4.4: Resonator using delay cells
1 f
1 f
C
S
C
H

v
od
v
id
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 84
, ( 4-4 )
the -domain transfer function of this amplier (output sampled during ) is
. ( 4-5 )
If the sampling capacitor, , and the holding capacitor, , are identical, the circuit is
called a unity gain buffer or sample-and-hold circuit.
The ideal transfer function of the SC amplier is affected by a number of non-ideal circuit
behaviors. The impacts of nite opamp gain, incomplete settling, switch charge-injection,
circuit noise, and capacitor mismatch on the performance of the half delay SC amplier
are analyzed in the following section.
Finite Opamp Gain Errors
Finite DC opamp gain ( ) and a non-zero opamp input capacitance ( ) introduce gain
error in (4-5), as analyzed below. Figure 4.6 shows single-ended equivalent circuits of
Figure 4.5: (a) A SC half delay gain stage, (b) 2-phase non-overlapping clock,
(c) input (dashed line) and output (solid line) waveforms

2
Analog Ground ~ V
DD
/2
0 0.5 1 1.5 2
x 10
7
0.5
0
0.5
(a)
(b)
(c)
C
S
C
H
v
ip
v
in
v
op
v
on
C
S
C
H
C
L
C
L
v
od
v
op
v
on
and v
id
v
ip
v
in
= =
z
2
V
od
z ( )
V
id
z ( )
----------------- H
HD
z ( )
C
S
C
H
--------z
1 2
= =
C
S
C
H
A C
in
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 85
Figure 4.5a during and phases.
Charge conservation on capacitors , , and before and after yields the
following difference equation:
( 4-6 )
In the -domain the actual transfer function of the fully differential SC amplier becomes
, ( 4-7 )
where is the feedback factor and is given by
. ( 4-8 )
Here, represents the sum of all parasitic capacitances appearing at the input of the
opamp, including opamp input capacitance. If , the transfer function of (4-7) can
be simplied to
( 4-9 )
An opamp with DC gain ( ) causes % error in a sample-and-hold circuit

1

2
C
S
C
H
v
i
(n-1/2)
C
in
+ -
+ -
+
-
C
S
C
H
v
o
(n)
C
in
+ -
+ -
+
-
-v
o
(n)/A
Figure 4.6: A single-ended equivalent circuit of Figure 4.5a
during (a) and (b) phases
1

2
(a) (b)
C
S
C
H
C
in

2
C
S
v
i
n 1 2 ( )
v
o
n ( )
A
------------- C
H
v
o
n ( )
v
o
n ( )
A
------------- + C
in
v
o
n ( )
A
------------- =
z
H
HD
z ( )
V
od
z ( )
V
id
z ( )
-----------------
C
S
C
H
--------
1
1
1
A
------- +
----------------- z
1 2
= =

C
H
C
H
C
S
C
in
+ +
------------------------------------ =
C
in
A 1
H
HD
z ( )
C
S
C
H
-------- 1
1
A
-------
,
_
z
1 2
=
50 dB A 300 1
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 86
if the input capacitance of opamp is comparable to and .
Settling Errors
Another source of error in the half delay circuit is due to incomplete settling. During the
hold phase ( ), the opamp is connected in a negative feedback conguration and is
modelled by Figure 4.7.
If the opamp is a single-stage topology with a gain of , the closed-loop transfer
function will be
. ( 4-10 )
Thus, the output of the SC half delay amplier follows an exponential behavior as follows:
( 4-11 )
Here, is the nal output value and is the closed-loop time constant given by
, ( 4-12 )
where is the open-loop unity gain frequency of the opamp. The hold time of the SC
half delay circuit is about half a clock period. Therefore, the output cannot reach the exact
nal value and there will be a settling error. The required time constant to settle to
percent of the nal value in a half clock period ( ) is given by
. ( 4-13 )
For instance, settling to 0.1% of the nal value requires the time constant to be
C
in
C
S
C
H

+
-
V
id
V
od
A(s)

Figure 4.7: Opamp in the closed-loop conguration during

2
A
u
s =
V
od
V
id
--------- s ( )
A s ( )
1 A s ( ) +
------------------------

u
s
u
+
------------------- = =
v
od
v
F
1 e
t
( ) =
v
F

u
---------- =

T
s
2

T
s
2
100 ( ) ln
--------------------------- =
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 87
.
In the time constant equation (4-12), the unity gain frequency is determined by
, ( 4-14 )
where is the transconductance of the opamp and is the total load capacitance
appearing at the opamp output during , which in the SC amplier of Figure 4.5 is
. ( 4-15 )
is the opamp load capacitance plus all the parasitic capacitances at the output of the
opamp.
Switch Charge Injection Errors
A third source of error is due to charge injection from MOSFET switches. Consider a
simple sample-and-hold circuit comprised of an nMOSFET switch and a holding
capacitor as shown in Figure 4.8.
At the end of the sampling phase, , the holding capacitor reaches a voltage that
is equal to the input voltage (assuming the settling error is negligible). During the hold
phase, , the clock voltage is dropped from to zero and ideally the voltage on
the holding capacitor is held constant and equal to the value of the input voltage at the end
of the sampling phase. However, the sampled voltage is disturbed due to channel charge
injection and clock feedthrough when the nMOSFET switch is turned off. The inversion
channel charge in a turned-on nMOSFET is given by
. ( 4-16 )
T
s
13.8 ( )

u
g
m
C
TL
---------- =
g
m
C
TL

2
C
TL
C
L
C
H
C
S
C
in
+ ( )
C
H
C
S
C
in
+ ( ) +
----------------------------------------- + =
C
L
C
H
C
H

v
i

Figure 4.8: A simple SC sample-and-hold circuit

V
DD
=
v
i
0 = V
DD
Q
ch
C
ox
WL ( ) v
GS
V
t
( ) =
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 88
When the transistor is turned off, this charge is released to drain, source and substrate. If
the fall time of the clock is longer than the channel transit time
( ), the charge absorbed by the substrate is negligible. The charge
partition between source and drain is a function of clock fall time and drain/ source
capacitance. For a sharp clock edge, channel charge is divided equally between source and
drain sides [Wegmann87].
The error introduced in the sample-and-hold circuit is
( 4-17 )
where is the percent of channel charge injected to the holding capacitor. This channel
charge causes offset, gain error and distortion in the sample-and-hold circuit.
A method for eliminating the signal dependent charge injection is bottom plate sampling
[Gregorian86], as illustrated in Figure 4.9. The channel charge associated with the
nMOSFET switch is independent of the signal because it is connected to analog
ground. Switch is opened rst, thus the charge injected to the sampling capacitor is
signal independent. Charge injected by the switch to the top plate causes no error
because it is shorted to ground in the next phase.
Another charge injection error is due to clock coupling through the gate to drain overlap
capacitance. In a fully differential architecture, Figure 4.10, both clock feedthrough and
xed channel charge is cancelled.
Noise Errors

0
L
2

n
v
GS
V
t
( ) =
V
C
ox
WL ( ) V
DD
v
i
V
t
( )
C
H
-------------------------------------------------------------- =

Figure 4.9: Bottom-plate sampling technique to eliminate signal dependent

charge injection
C
H

1
v
i
1

1D
Analog Ground

1D
N1
N2 N3

2
N4

2D

2

2D
N2
N2
N1
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 89
In SC circuits, thermal and icker ( ) noise generated by transistors used in opamps
and analog switches determine the minimum detectable signal amplitude. The power of
icker noise at high frequencies is very low and therefore its effect on the performance of
high frequency SC circuits can be neglected. Thermal noise due to on-resistance of the
analog switches and opamp wide-band noise is analyzed for a single-ended SC amplier.
During the sampling phase, Figure 4.11a, there will be a mean squared noise charge
( ) on both sampling capacitor and holding capacitor . In the hold phase ,
Figure 4.11b, there will be a new noise on sampling capacitor. The thermal noise on
holding capacitor during is at low frequencies and will not affect the circuit. The net
C
H

1
v
ip
1

1D
Analog Ground

1D
N1
N2 N3

2
N4

2D

2D
C
H

1
v
in

1D
N1p
N2p N3p

2
N4p

2D
v
on
v
op
Figure 4.10: Fully differential bottom-plate sampling to cancel xed
charge injection and clock feedthrough
1 f
Figure 4.11: Single-ended equivalent circuits of Figure 4.5a
during (a) sampling phase, and (b) holding phase
(a)
(b)
C
S
C
H
v
i
v
o
C
in
C
S
C
H
v
o
C
in
kTC C
S
C
H

2
kTC
S

2
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 90
noise on the sampling capacitor (i.e. ) is transferred to the holding capacitor and
the total charge noise power at the output will be
. ( 4-18 )
The mean squared noise voltage at the output will be
, ( 4-19 )
where is the gain of the SC amplier. In a fully differential SC architecture,
there are twice as many capacitors as in a single-ended SC circuit, thus the noise power is
doubled. Moreover, for a constant power dissipation and speed, capacitor sizes in a fully
differential circuit must be half the size (thus having twice the noise power) of a single-
ended circuit. Therefore, the thermal noise of a fully differential circuit will be four
times higher than that of a single-ended circuit. However, the voltage swing of a fully
differential circuit is twice as high (4 times in power) as that of a single-ended SC circuit.
Thus, for a given speed and power dissipation the SNR will be equal for both a fully
differential and a single-ended SC circuit.
The thermal noise associated with an opamp has a power spectral density of at least
. ( 4-20 )
Assuming a single-pole opamp and using the equivalent noise bandwidth ( )
introduced in [Gray93], the total opamp thermal noise power will be
, ( 4-21 )
where and are given by (4-8) and (4-15) respectively. The input referred overall
voltage noise power of the SC amplier can be expressed as
( 4-22 )
2kTC
S
q
n
2
kT C
H
2C
S
) + ( =
kT C
v
n out ( )
2
q
n
2
C
H
2
--------
kT
C
H
-------- 1 2G + ( ) = =
G C
S
C
H
=
kT C
S
OTA
f ( ) 4kT
2
3
---
1
g
m
------
,
_
=

3dB
4
v
nT ota ( )
2 2
3
---
kT
C
TL
---------- =
C
TL
v
n
2
kT
1 2G +
C
H
-----------------
2
3
---

C
TL
---------- +
,
_
C
H
C
S
--------
,

_
2
=
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 91
In a sample-and-hold circuit where , the RMS value of the
input referred thermal noise voltage is
( 4-23 )
If the above sample-and-hold is changed to a SC amplier with a gain of (by changing
) the input referred thermal noise will be
( 4-24 )
Capacitor Mismatch Error
Another source of gain error is due to capacitor mismatch. Device matching is technology
and layout dependent. Dielectric thickness variation and edge errors across the die
contribute to inaccuracy in capacitance matching. In general, matching is improved as the
size of the devices to be matched is increased. Proximity and having similar geometry also
help to achieve better matching. Typically, poly-to-poly capacitor matching in the order of
1% to 0.1% is readily achievable in many analog CMOS processes.
An efcient architecture for unity gain sample-and-hold exists which is immune to
capacitor mismatch and requires one capacitor to perform both sample and hold
operations, as shown in Figure 4.12.
In this circuit, during input voltage is stored on sampling capacitor and during
C
S
C
H
C
in
C
L
C
u
= = = =
v
n i ,
47
15
----- -
kT
C
u
------ =
0.5
C
H
2C
u
=
v
n i ,
2
7
6
-- -
kT
C
u
------ =
Figure 4.12: One capacitor sample-and-hold circuit
C
S
v
ip
v
in
v
op
v
on
C
S
C
L
C
L

1
C
S

2
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 92
capacitor is switched to the output and plays the role of holding capacitor. Thus, gain
error due to mismatch between sampling capacitor and holding capacitor is irrelevant.
Furthermore, the one-capacitor sample-and-hold structure has other advantages over the
two-capacitor version. In the one-capacitor sample-and-hold circuit, nite opamp gain
still causes gain error and the transfer function is
, ( 4-25 )
where the feedback factor is given by
. ( 4-26 )
Compared to the two-capacitor sample-and-hold circuit, the one-capacitor sample-and-
hold structure has a higher and therefore a lower gain error.
The total load capacitance in this sample-and-hold circuit is
. ( 4-27 )
The value of is less in a single capacitor sample-and-hold circuit (4-27) than in a
two-capacitor sample-and-hold circuit (4-15). From equation (4-14), a lower equivalent
output capacitance results in a higher unity gain frequency . Therefore, the closed loop
time constant (4-12) of the one-capacitor sample-and-hold is smaller than the closed-loop
time constant of a two-capacitor sample-and-hold circuit due to both higher and
higher .
In the one-capacitor sample-and-hold circuit, the sampling capacitor is the only source of
thermal noise. Therefore, the output noise power (which is the same as
input referred noise power) in the one-capacitor sample-and-hold circuit is and is
lower than the two-capacitor sample-and-hold circuit. Again, in a fully differential
structure, the noise power is doubled and is equal to .
Example 4.1: In sample-and-hold circuits of Figure 4.5 and Figure 4.12, if opamp input
C
S
A
H z ( )
V
od
V
id
--------- z ( )
1
1
1
A
------- +
----------------- z
1 2
= =

C
S
C
S
C
in
+
--------------------- =

C
TL
C
L
C
S
C
in
C
S
C
in
+
--------------------- + =
C
TL

kT C kT C
kT C
S

5 dB
2kT C
S

Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 93

capacitance and output load are equal to the sampling capacitor (and holding
capacitor ), the one-capacitor sample-and-hold SC circuit is about times faster
than the two-capacitor sample-and-hold SC circuit.
4.3 Full Delay SC Circuits
The SC amplier of Figure 4.5 performs a half delay operation. A simple full delay SC
circuit is obtained by cascading two of these half delay circuits with alternate and
clock phases as shown in Figure 4.13. This two-stage SC amplier circuit delays the input
signal for a full clock period and scales it. The -domain transfer function of this circuit is
. ( 4-28 )
Both opamps in this conguration are idle for a half clock period. A more efcient full
delay gain stage circuit is achieved by merging the two half delay circuits into a cell using
one opamp [Longo93], as shown in Figure 4.14. The -domain transfer function of this
circuit is
C
in
C
L
C
S
C
H
1.6

1

2
Figure 4.13: A simple cascade SC delay circuit
C
S1
C
H1
v
ip
C
S1
C
H1
C
S2
C
H2
v
op
v
on
C
S2
C
H2
v
in
z
V
od
V
id
--------- z ( )
C
S1
C
H1
-----------
C
S2
C
H2
----------- z
1
=
z
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 94
. ( 4-29 )
Finite opamp gain causes gain and phase error in the full delay circuit of Figure 4-14, as
analyzed below. Single-ended equivalent circuits for the SC delay circuit of Figure 4.14
during and are depicted in Figure 4.15. An opamp gain of causes the virtual
ground node of the opamp to be at with respect to analog ground. The charge
conservation equation before and after yields the following difference equation:
Figure 4.14: A SC delay gain stage
v
ip
v
in
v
op
v
on
C
S
C
S
C
I
C
I
C
H
C
H
H
D
z ( )
V
od
V
id
--------- z ( )
C
S
C
H
-------- z
1
= =

1

2
(a) (b)
Figure 4.15: A single-ended equivalent circuit of Figure 4.14
during (a) and (b) phases
1

2
C
S
C
H
v
i
(n)
v
o
(n)
C
I
C
in
+ -
+ -
+ -
v
vg
C
I
v
o
(n+1/2)
C
S
C
in
+ -
+ -
v
vg
+
-
+
-
A
v
vg
v
o
A

2
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 95
( 4-30 )
In the -domain, the transfer function of the half delay circuit (during in Figure 4-14)
becomes
( 4-31 )
where and are given by
, ( 4-32 )
where . If , the above equations can be simplied to
. ( 4-33 )
The term in the square bracket of equation (4-31) is the error term . The frequency
response of the error term is derived by substituting in , and is given by
. ( 4-34 )
The magnitude and the phase of the above equation are
( 4-35 )
. ( 4-36 )
For , we have and the magnitude and phase of the error term can be
approximated as
C
S
v
i
n ( )
v
o
n 1 2 + ( )
A
------------------------------ C
I
v
o
n ( )
A
------------- v
o
n 1 2 + ( )
v
o
n 1 2 + ( )
A
------------------------------ +
,
_
+
C
in
v
o
n ( )
A
---------------- -
v
o
n 1 2 + ( )
A
------------------------------ + =
z
2
H
HD
z ( )
C
S
C
I
------z
1 2
g
0
1 p
0
z
1 2

----------------------------- =
g
0
p
0
g
0
1
1 1 A +
----------------------- - = p
0
g
0
A
----- 1
C
in
C
I
-------- +
,

_
=
C
I
C
I
C
S
C
in
+ + ( ) = 1 A 1
g
0
1 1 A p
0
1
A
--- 1 C
in
C
I
+ ( )
E z ( )
z e
jT
= E z ( )
E e
jT
( )
g
0
1 p
0
T 2 ( ) j p
0
T 2 ( ) sin + cos
---------------------------------------------------------------------------------------- =
E ( ) E ( )
E ( )
2
g
0
2
1 p
0
T 2 ( ) cos [ ]
2
p
0
T 2 ( ) sin [ ]
2
+
---------------------------------------------------------------------------------------------------- =
E ( )
p
0
T 2 ( ) sin
1 p
0
T 2 ( ) cos
-------------------------------------------- tanh =
A 1 p
0
1
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 96
( 4-37 )
. ( 4-38 )
Therefore, the transfer function of the half delay SC circuit with nite opamp gain will be
. ( 4-39 )
The full delay SC circuit of Figure 4.14 will experience errors during and and the
actual transfer function of the full delay circuit will be
. ( 4-40 )
Substituting in the above equation and assuming and , the
magnitude and the phase of the error term in a full delay circuit due to nite opamp gain
are obtained to be
( 4-41 )
, ( 4-42 )
where and are the feedback factor during and respectively.
The actual transfer function of a full delay circuit is
( 4-43 )
Example 4.2: In the SC full delay circuit of Figure 4.14, opamp DC gain is , signal is
a sinusoid with frequency of and . The gain and phase of the
error term, calculated from (4-41) and (4-42) respectively, are
E ( ) m
HD
1
1
A
-------
T 2 ( ) cos
A
----------------------------- 1
C
in
C
H
-------- +
,

_
+ = =
E ( )
HD
T 2 ( ) sin
A
---------------------------- 1
C
in
C
H
-------- +
,

_
= =
H
HD
z ( )
C
S
C
I
------z
1 2
m
HD
e
j
HD
[ ] =

1

2
H
FD
z ( )
C
S
C
H
--------z
1
g
0
( )

1
1 p
0
( )

1
z
1 2

--------------------------------------
g
0
( )

2
1 p
0
( )

2
z
1 2

-------------------------------------- =
z e
jT
= p
0
( )

1
p
0
( )

2
1
m
FD
1
1
A
---
1

1
-------
1

2
------- +
T 2 ( ) cos
A
----------------------------- 1 C
in
C
I
+ ( ) 1 C
in
C
H
+ ( ) + [ ] + =

FD
T 2 sin
A
----------------------- 1 C
in
C
I
+ ( ) 1 C
in
C
H
+ ( ) + [ ] =

1

2
H
FD
z ( )
C
S
C
H
--------z
1
m
FD
e
j
FD
[ ] =
100
f
S
4 C
S
C
I
C
H
C
in
= = =
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 97
. ( 4-44 )
Therefore, an opamp gain of will cause % gain error in the full delay SC
sample-and-hold circuit. The phase error is % (in the sense that is
% of ).
A Double-Sampled SC Delay Cell
The opamp in the one-capacitor sample-and-hold circuit of Figure 4.12 is idle during the
sampling phase . By duplicating the sampling circuitry and using an alternate clock
phase for it, a two-path SC sample-and-hold is obtained, as shown in Figure 4.16.
In this circuit, the input signal is sampled every half clock period ( ) and appears at
the output with a half-clock period delay. Thus, the transfer function of this cell is
, ( 4-45 )
m
FD
0.968 =
FD
0.028 =
40 dB 3.2
2.8 e
j0.028
e
j0

2.8 e
j0

1
Figure 4.16: A double-sampled SC delay circuit
C
S1
v
ip
v
in
v
op
v
on
C
S1
C
S2
C
S2
T
s
2
V
od
V
id
--------- z ( ) z
1
=
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 98
where .
Therefore, the effective sampling frequency in this two-path sample-and-hold circuit is
twice the clock frequency. This structure is also called a double-sampled SC circuit
[Choi80] [Hurst90]. The factor-of-two improvement in the speed of the double-sampled
SC delay cell is achieved without increasing the clock rate or requiring a faster opamp
settling time. In return, mismatch and uneven clock phases create image errors as we will
discuss later.
Finite opamp gain and opamp input capacitance cause both gain and phase error in the
transfer function of the double-sampled SC delay circuit. Figure 4.17 shows a single-
ended equivalent circuit of the double-sampled delay circuit during and . Charge
conservation on capacitors and before (the non-overlapping phase) and after
yields the following difference equation:
. ( 4-46 )
Here the time indices at the end of and are denoted by and respectively
due to the double sampling property of the circuit. If capacitors , a
similar difference equation would be obtained for the phase and the overall transfer
function in -domain will be
, ( 4-47 )
z e
j T
s
2 ( )
=
(a)
(b)
Figure 4.17: A single-ended equivalent circuit of Figure 4.16
during (a) and (b) phases
1

2
C
S1
C
S2
v
i
(n)
v
o
(n)
C
in
+ -
+ -
+
-
v
vg
(n)
C
S2
C
S1
v
i
(n+1)
v
o
(n+1)
C
in
+ -
+ -
+
-
v
vg
(n+1)

1

2
C
S1
C
in

2

2
C
S1
v
i
n ( ) v
o
n 1 + ( )
v
o
n 1 + ( )
A
---------------------- +
,
_
C
in
v
o
n ( )
A
----------------
v
o
n 1 + ( )
A
---------------------- + =

1

2
n n 1 +
C
S1
C
S2
C
S
= =

1
z
V
od
z ( )
V
id
z ( )
----------------- H
dD
z ( )
g
0
1 p
0
z
1

----------------------- z
1
= =
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 99
where and are given by
( 4-48 )
. ( 4-49 )
Thus, nite opamp gain and non-zero input capacitance modify the transfer function of the
double-sampled delay cell by a damped integrator term from its ideal response. This
change of transfer function causes both gain and phase error in the response of the delay
circuit. The actual transfer function becomes
, ( 4-50 )
where and are magnitude and phase of the error term in the double-sampled
delay circuit. Assuming , the magnitude and phase error are given by
( 4-51 )
. ( 4-52 )
Example 4.3: In Figure 4.16, if the input capacitance of the opamp is equal to the
sampling capacitor and the opamp has DC gain, both gain error and phase error are
% for a signal at one half the clock frequency.
A major limitation of double-sampled SC circuits is due to mismatch in the two paths
[Gregorian86] that causes in-band image of the signal as described later. However, the
double-sampled circuit of Figure 4.16 uses the one-capacitor sample-and-hold architecture
and its gain is not affected (to a rst order) by capacitor mismatch.
Double-sampled SC circuits are a subset of a class of circuits called N-path lters with N
being equal to two. A diagram of a two-path circuit and its corresponding clock phases is
shown in Figure 4.18.
g
0
p
0
g
0
1
1
1
A
---
C
in
C
S
--------
1
A
--- + +
------------------------------------- =
p
0
C
in
C
S
--------
g
0
A
----- =
H
dD
z ( ) m
dD
e
j
dD
[ ] z
1
=
m
dD

dD
A 1
m
dD
1
1
A
-------
T cos
A
-----------------
C
in
C
S
--------
,

_
+

dD
T sin
A
----------------
C
in
C
S
--------
,

_

40 dB
1
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 100
The non-overlapping clock has a frequency of and the effective sampling frequency
( ) of a double-sampled SC circuit is . The sequence of the signals during
(odd samples) is denoted by an superscript and the sequence of the signals during
(even samples) is denoted by an superscript. The odd and even sequences have a
sampling frequency of . The input sequence is a time-interleaved vector
sum of odd ( ) and even ( ) sequences and in the -domain we have
( 4-53 )
Similarly, the output sequence is expressed as
, ( 4-54 )
where odd and even sequences are related by
. ( 4-55 )
If the two paths are not symmetric and, for instance, there is a gain mismatch of
between them, the input-output relation is
. ( 4-56 )
This equation can be expressed as
. ( 4-57 )
Therefore, a mismatch between the two channels is equivalent to having an attenuated
image of the signal being applied at the input along with the real input. Figure 4.19 shows
Figure 4.18: Two-path SC circuit and clock phases
H(z)
V
in
V
out

2
H(z)
f
clock
f
s
f
s
2 f
clock
=

1
o

2
e
f
clock
f
s
2 = v
in
v
in
o
v
in
e
z
V
in
z ( ) V
in
o
z ( ) V
in
e
z ( ) + =
V
out
z ( ) V
out
o
z ( ) V
out
e
z ( ) + =
V
out
o
z ( ) H z ( )V
in
o
V
out
e
z ( ) H z ( )V
in
e
= =

V
out
z ( ) 1 + ( )H z ( )V
in
o
H z ( )V
in
e
+ =
V
out
z ( ) H z ( ) V
in
z ( ) V
in
o
z ( ) + [ ] =
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 101
the periodic spectrum of the input signals and .
In the frequency domain, a sampled input signal with a frequency will have a
periodic spectrum with the signal appearing at . The odd sequence of the signal
has a sampling frequency of and thus attenuated images appear at .
Non-uniform sampling due to uneven and phases has a similar effect [Yang94]. If
phase is longer by an amount compared to the phase, then we can write
, so .
4.4 A SC Bandpass Sigma-Delta Modulator
A fully differential SC resonator using two sample-and-hold delay cells in a negative
feedback loop is illustrated in Figure 4.20.
In this circuit, if all the capacitors have the same size the transfer function of the resonator
is
. ( 4-58 )
Poles of this resonator are at . Capacitor mismatch and nite opamp gain cause
errors in the transfer function.
If the gain error in the unity gain delay cell due to capacitor mismatch is , the resulting
transfer function of the resonator will be
V
in
V
in
o
Figure 4.19: Spectrum of the input signal (solid line) and the
attenuated odd samples of the input signal (dotted line)
V
in
f
f
s
/
2 0
f
s
1

Spectrum
f
B
f
S
/
2
-
f
B
f
S
/
2
+
f
B
f
S

-
f
B
f
S
+
f
B
V
in
f
B
n f
s
f
B
t
f
s
2 n f
s
2 ( ) f
B
t

1

2

1

2
1 + e
s
1 s = s
H
R
z ( )
V
od
V
id
--------- z ( )
z
2
1 z
2
+
----------------- = =
z j t =

Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 102

. ( 4-59 )
The new location of poles are at . Therefore, a percent gain error in the
unity gain delay circuit will cause percent change in the gain of the resonator and
percent change in the location of the poles of the resonator. Note that the poles of the
resonator are still on the -axis.
In section 4.3, it was shown that nite opamp gain causes both gain error and phase error
in the ideal transfer function of a SC delay circuit, and the actual transfer function is given
by (4-43). Using this transfer function for the delay cell, the resonator transfer function
will be
, ( 4-60 )
where and are the gain and phase error of the -th delay cell. Poles of this
Figure 4.20: A SC resonator using two delay cells
v
ip
v
in
v
op
v
on
C
S2
C
S2
C
I2
C
I2
C
H2
C
H2
C
S1
C
S1
C
I1
C
I1
C
H1
C
H1
C
F
C
F
H
R
z ( )
1 ( )
2
z
2
1 1 ( )
2
z
2
+
------------------------------------ - =
z 1 ( ) j t =
2
j
H
R
z ( )
m
FD1
e
j
FD1
( ) m
FD2
e
j
FD2
( ) [ ]z
2
1 m
FD1
e
j
FD1
( ) m
FD2
e
j
FD2
( ) [ ]z
2
+
------------------------------------------------------------------------------------------------------ - =
m
FDi
e
j
FDi
i
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 103
resonator are
. ( 4-61 )
Thus, resonator poles are moved inside the unit circle (because ) and
have a phase lag of . Using the simplied equation of (4-42), the phase shift of the
resonator is
( 4-62 )
Example 4.4: If an resonator is built using two delay cells in a negative feedback
loop and the capacitor sizes in terms of a unit capacitor are and
, an opamp gain of will cause a phase error of radians, almost
% of the nominal frequency.
A resonator with an arbitrary gain is achieved by choosing different values for the
capacitors and in the second delay cell of the resonator of Figure 4.20. During
the transfer function of this circuit is
. ( 4-63 )
If , a resonator with gain of is obtained which is useful for the
implementation of the fourth-order bandpass modulator shown in Figure 4.1.
A fourth-order SC modulator is achieved by cascading two resonators and a quantizer
in a feedback loop as shown in Figure 4.21.
In this circuit all the capacitors are identical ( ) except for the four marked by asterisks
which have a value of . These four capacitors scale the gain of the resonators to the
required value of .
Speed of operation is determined by the closed-loop time constant of the opamps, as
discussed before. Worst case opamp loading for this architecture occurs for the second
opamp (OA2) during , and a single-ended representation of it is shown in Figure 4.22a.
z
p1 p2 ,
j m
FD1
m
FD2
e
j

FD1

FD2
+ ( )
2
---------------------------------
t =
m
FD1
m
FD2
1 <

R0
f
s
4

R0
2
2A
------- 1 C
in
C
I
+ ( ) 1 C
in
C
H
+ ( ) + [ ] =
f
s
4
C
u
C
in
C
I
2C
u
= =
C
H
C
u
= 40 dB 0.035
2.2
C
S2
C
I 2

2
H
R
z ( )
C
S2
C
I 2
---------
z
3 2
1 z
2
+
----------------- =
C
I 2
2C
S2
= 0.5
C
u
2C
u
0.5

1
C
h
a
p
t
e
r

4

H
i
g
h
-
S
p
e
e
d

S
C

F
o
u
r
t
h
-
O
r
d
e
r

B
a
n
d
p
a
s
s

S
i
g
m
a
-
D
e
l
t
a

M
o
d
u
l
a
t
o
r
s
1
0
4
Figure 4.21: A fourth-order SC bandpass sigma-delta modulator
V
rn
V
rp
V
rp
V
rn
* *
*
*
V
ip
V
in
V
op
V
on
V
rp
V
rn
1-bit
D/A
OA2
V
ocm
V
icm
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 105
If the opamp input capacitance is assumed to be equal to the unit capacitance
used in the modulator, the worst case closed-loop time constant is found to be
(from equation (4-12)).
A similar analysis for the fourth-order SC bandpass reported in [Longo93] indicates
that the rst opamp during has the worst case loading, as shown in Figure 4.22b. The
settling time constant of this structure is , which is about % slower than the
circuit presented in this work.
This modulator was simulated in Eldo using near ideal models for switches, capacitors,
opamps, and the quantizer. The DC gain of opamps was set to and switch on-
resistance was set to . Figure 4.23 shows the modulator output spectrum for a
sinusoidal input signal with an amplitude of below full scale. The
C
in
C
u
7C
u
g
m
=

2
9C
u
g
m
28
Figure 4.22: Worst case opamp loading for (a) bandpass of Figure 4.21
(b) bandpass modulator in [Longo93]
C
u
C
u
C
in
3C
u
C
u
C
u
C
in
2C
u
(a) (b)
60 dB
200
24.9 MHz 12 dB
Figure 4.23: Output spectrum from Eldo simulation
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
0 10 20 30 40 50
150
100
50
0
24 24.5 25 25.5 26
150
100
50
0
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 106
sampling rate of is provided by a two-phase non-overlapping clock. Simulated
SNR are and in ( ) and ( )
bandwidths respectively.
4.4.1 Sources of Error
Practical analog circuit realization of bandpass sigma-delta modulators involves errors due
to device and circuit non-idealities. In the following section, some prominent sources of
error, namely capacitor mismatch, nite opamp gain, and thermal noise are considered.
Capacitor Mismatch
Noise shaping is determined by the quality of the resonators used in the forward path of
the modulator. Resonators used in the bandpass modulator have a gain of and their
ideal transfer function is
. ( 4-64 )
A mismatch of between capacitors changes the ideal transfer function of the resonators
to
( 4-65 )
where
. ( 4-66 )
As mentioned earlier, gain of the second resonator is not a critical parameter because it is
followed by a high gain quantizer. Thus, gain error in the second resonator is not going to
affect the ideal behavior of the modulator. Simulations show that changing the gain of the
second resonator by as much as % has virtually no effect on the SNR of the
modulator. However, gain error in the rst resonator will deteriorate the SNR of the
modulator.
The ideal resonator of (4-64) has innite gain at . The gain of the actual resonator of
100 MHz
94.3 dB 58.8 dB 200 kHz OSR 250 = 1 MHz OSR 50 =
0.5
H
R
z ( )
1
2
---
z
2
1 z
2
+
----------------- =

H
R
z ( )
1
2
---
g
0
z
2
1 p
0
z
2
+
----------------------- =
g
0
p
0
1 ( )
2
= =
100 t
f
S
4
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 107
(4-65) at a quarter of the sampling frequency is
. ( 4-67 )
A lower resonator gain causes less attenuation of the quantization noise in the narrow band
around . Performing a bandpass to lowpass transformation, using a
change of variable on the resonator of (4-65), results in
, ( 4-68 )
which is a leaky integrator with DC gain of . From (4-67), we can see
a capacitor mismatch of reduces the DC gain in (4-68) to . The effect of
integrator leakage on the in-band quantization error of a second-order lowpass has
been analyzed in [Boser88] and is given by
. ( 4-69 )
Here, is the power of in-band quantization noise for a leaky integrator, and is the
power of in-band quantization noise for a perfect integrator. If the DC gain of the
integrator (or equivalently, resonator gain at ) is equal to the oversampling ratio
of the modulator, the SNR performance loss is about .
Therefore, matching between capacitors must be better than in a fourth-
order bandpass modulator.
Finite Opamp Gain
Finite opamp gain causes errors in the resonant frequency and the gain of the resonator.
This in turn changes the position of the notch in the noise transfer function of the bandpass
modulator away from , and also increases the in-band quantization noise. The
notch will be shifted to a lower frequency , where
H
R0
H
R
e
jT
( )
f f
S
4 =
g
0
1 p
0

---------------
1
2
------ = =
f
S
4 z
2
z
1

H
I
z ( )
g
0
z
1
1 p
0
z
1

----------------------- =
H
I 0
g
0
1 p
0
( ) =
H
I 0
1 2 =
S
B
S
B0
--------- 1
5

4
------
OSR
H
I 0
-----------
,
_
4
10
3
2
---------
OSR
H
I 0
-----------
,
_
2
+ + =
S
B
S
B0
f
s
4 OSR
1.3 dB
1 2 OSR ( )
f
s
4
f
s
4 f
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 108
. ( 4-70 )
In this equation, is the phase error associated with the poles of the resonator and is
given by (4-62). The frequency shift of the notch can be expressed in terms of the opamp
gain and oversampling ratio of the modulator as
. ( 4-71 )
For a fourth-order bandpass modulator with a quantization noise slope of about
, a shift in the notch frequency will increase the power of in-band
quantization noise by which is approximately
. ( 4-72 )
Substituting (4-62) in the above equation yields
. ( 4-73 )
For an acceptable SNR loss, the minimum opamp gain can be found in terms of .
Example 4.5: In the bandpass modulator of Figure 4.21, the values of different
capacitors in terms of a unit capacitor are: and .
For an oversampling ratio of the minimum required opamp gain is , if a penalty
of SNR loss is acceptable due to notch frequency shift. Note that opamp gain
( ) is higher than the value of , in decibels.
Example 4.6: In the above example, if the opamp gain is and the sampling
frequency is , the phase shift is found to be radians and from
equation (4-70), the notch frequency shift is found to be .Thus, the resonant
frequency will be at , instead of being at . For an , the in-
band quantization noise power (4-72) will increase by about .
The bandpass SC modulator was simulated using opamps with DC gain of , and
f
f
s
2
------
R0
=

R0
f

R0

--------- OSR BW =
15 dB/octave f
S
B
S
B
15
BW ( ) 2
--------------------- f 30

R0

--------- OSR dB = =

R0
S
B
15
2

-------
OSR
A
----------- 2
C
in
C
I
--------
C
in
C
H
-------- + + =
OSR
C
u
C
I
C
in
2C
u
= = C
H
C
S
C
u
= =
40 53 dB
3 dB
53 dB 21 dB OSR
40 dB
100 MHz
R0
0.035
562 kHz
24.44 MHz 25 MHz OSR 50 =
16.7 dB
40 dB
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 109
the parasitic capacitances at the input of the opamp was assumed to be . The input
signal is a sinusoid with an amplitude of below full scale. Figure 4.24
shows the output spectrum of the modulator. The notch frequency is shifted by about
. Simulated SNR are and for bandwidth of and
respectively.
If we neglect the phase error, the effect of nite opamp gain on the transfer function of a
resonator is similar to capacitor mismatch and the actual transfer function of the resonator
will be like equation (4-65), with and being
( 4-74 )
where, is the feedback factor of the th delay circuit during the th clock phase. If
the feedback factors are comparable and assumed to be equal to , the above equation is
simplied to
. ( 4-75 )
The gain of the resonator at its resonant frequency is
. ( 4-76 )
2C
u
24.9 MHz 12 dB
450 kHz 56.5 dB 46.1 dB 200 kHz
1 MHz
Figure 4.24: Output spectrum of the fourth-order bandpass modulator
with an opamp gain of 40 dB and opamp input capacitance of Cin =2Cu
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
(
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
(
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
0 10 20 30 40 50
120
100
80
60
40
20
0
23 24 25 26 27
120
100
80
60
40
20
0
g
0
p
0
g
0
p
0
1
1
A
---
1

1 1 ,
-------------
1

2 1 ,
-------------
1

1 2 ,
-------------
1

2 2 ,
------------- + + +
,
_
= =

j i ,
i
j

g
0
p
0
1
4
A
------- = =
H
R0
e
jT
( )
f f
S
4 =
g
0
1 p
0

---------------
A
4
------- =
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 110
The in-band quantization error as a function of resonator gain can be expressed by an
equation similar to (4-69). Therefore the minimum required opamp DC gain for this
double-resonator SC bandpass modulator is .
In a SC integrator, using an opamp with DC gain of and feedback factor of , the
integrator DC gain is . Thus, the minimum required opamp DC gain in a lowpass
modulator is . Note that for a similar SNR performance, the
opamp used in the sample-and-hold based fourth-order bandpass modulator requires
higher DC gain than the opamp used in the second-order lowpass modulator.
Figure 4.25 shows the SNR loss as a function of . From this gure, one can
nd the requirements on capacitor matching and/or opamp DC gain.
In the bandpass modulator of Example 4.5, if the oversampling ratio is , a capacitor
matching accuracy of at least % is needed for a SNR loss of . Calculating the
during each phase for the two opamps and using equations (4-74) and (4-76), is
found to be equal to . Thus, the minimum opamp DC gain is for the same
SNR loss, i.e. .
A
min bp ( )
4 OSR ( ) =
A
H
0
A
A
min lp ( )
OSR =
12 dB
OSR H
R0

6 4 2 0 2 4 6
0
5
10
15
20
OSR H
R0

I
n
-
b
a
n
d

S
N
R

l
o
s
s

(
d
B
)
Figure 4.25: SNR loss versus OSR / H
R0
from analytical result
(solid line) and from simulation results (o points).
40
1.25 1.5 dB
H
R0
A 16 56 dB
1.5 dB
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 111
Noise
Thermal noise generated by various switches and the two opamps in the rst resonator is
going to limit the accuracy of the bandpass modulator. Thermal noise generated in the
second stage undergoes a second-order band-reject noise shaping, and thus its effect is not
critical.
Using the results obtained earlier in this chapter on the analysis of the noise in a SC
amplier, the total input referred thermal noise power of the rst stage of the single-ended
SC bandpass modulator in Figure 4.21 is
. ( 4-77 )
In this calculation, the input capacitance of the opamp is assumed to be comparable to the
unit capacitor, i.e. . The total noise power for a fully differential SC circuit is
twice as large as (4-77). The in-band noise power is reduced due to the oversampling
process and is given by:
( 4-78 )
4.5 A Double-Sampled SC Bandpass Sigma-Delta Modulator
A double-sampled SC resonator is obtained by cascading two double-sampled delay
circuits as shown in Figure 4.26. The ideal transfer function of this circuit is
. ( 4-79 )
In this conguration, capacitance mismatch (between and ) causes a gain error on
the input signal that is added to the feedback signal using a two-capacitor
sample-and-hold architecture. If the error due to capacitor mismatch is , the transfer
function of the double-sampled resonator will be
. ( 4-80 )
v
nT
2 14.75kT
C
u
-------------------- =
C
in
C
u
=
v
nT
2
in band
29.5
OSR
-----------
kT
C
u
------ =
H z ( )
C
I
C
S1
---------
z
2
1 z
2
+
----------------- =
C
I
C
S1
v
id
v
ip
v
in
=

H z ( ) 1 + ( )
C
I
C
S1
---------
z
2
1 z
2
+
----------------- =
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 112
Therefore, the location of resonator poles is not affected by the capacitor mismatch.
However, nite opamp gain ( ) causes errors in the ideal transfer function of a double-
sampled SC delay circuit (given by (4-50)) and the transfer function of a double-sampled
resonator becomes
. ( 4-81 )
Poles of this resonator are
. ( 4-82 )
The poles are inside the unit circle, close to the intersection of -axis and the unit circle.
The phase error of the poles of this resonator in radians is
. ( 4-83 )
Figure 4.26: A double-sampled SC resonator
v
ip
v
in
v
op
v
on
C
I
C
I
C
I
C
1
C
S1
C
S1
C
S1
C
S1
C
S2
C
S2
C
S2
C
S2
A
H
dR
z ( )
C
I
C
S1
---------
m
dD1
e
j
dD1
( ) m
FD2
e
j
dD2
( ) [ ]z
2
1 m
dD1
e
j
dD1
( ) m
dD2
e
j
dD2
( ) [ ]z
2
+
----------------------------------------------------------------------------------------------------- =
z
p1 p2 ,
j m
dD1
m
dD2
e
j

dD1

dD2
+ ( )
2
--------------------------------
t =
j

dR
T sin
2A
----------------
C
in1
C
S1
-----------
C
in2
C
S2
----------- + =
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 113
Both magnitude and phase errors are inversely proportional to the DC gain of the opamp.
A double-sampled double-resonator SC bandpass modulator is constructed using two
double-sampled resonators and a quantizer in a feedback loop, as shown in Figure 4.27.
All the capacitors are unit size capacitors ( ), except for the eight marked by asterisks
which have a value of , and are made of two unit size capacitors in parallel. The gain
of resonators is set by the eight capacitors to the required value of .
The functionality of this double-sampled SC bandpass modulator was veried in Eldo
using ideal components. The on-resistance of the switches was set to and the DC
gain of opamps was assumed to be . Figure 4.28 shows the output spectrum of the
modulator for a sinusoid input signal of . The amplitude of the signal was
below full scale and the clock frequency was .
Simulated SNR is about and for bandwidths of and
respectively. For the same clock frequency and signal bandwidth, the oversampling ratio
of this modulator is twice as large as the single-sampled modulator. Thus, the SNR of this
modulator is higher than that of a single-sampled counterpart.
4.5.1 Sources of Error
Performance of the double-sampled modulator is affected by circuit non-idealities. In
the following, effects of some prominent non-idealities such as capacitor mismatch, nite
opamp gain, and noise on the SNR of the double-sampled modulator are described.
C
u
2C
u
0.5
200
60 dB
50.1 MHz
12 dB 100 MHz
0 20 40 60 80 100
150
100
50
0
48 49 50 51 52
150
100
50
0
Figure 4.28: Output spectrum from Eldo simulation
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
(
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
(
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
108 dB 72.8 dB 200 kHz 1 MHz
15 dB
C
h
a
p
t
e
r

4

H
i
g
h
-
S
p
e
e
d

S
C

F
o
u
r
t
h
-
O
r
d
e
r

B
a
n
d
p
a
s
s

S
i
g
m
a
-
D
e
l
t
a

M
o
d
u
l
a
t
o
r
s
1
1
4
Figure 4.27: A double-sampled SC fourth-order bandpass sigma-delta modulator
V
rn1
V
ip
V
rn2
V
rp1
V
rp2
V
in
V
rp1
V
rp2
V
rn1
V
rn2
V
rn1
V
rp1
V
out
V
rp2
V
rn2
*
*
*
*
*
*
*
*
V
ocm
V
icm
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 115
Capacitor Mismatch
As mentioned before, double-sampled SC circuits are sensitive to path mismatch and any
mismatch between the two channels will produce image problems. Mismatch in the
second stage of the modulator is noise shaped (second-order noise-shaping) and will not
cause a noticeable image signal. Simulations were carried out using different capacitor
mismatches to verify the above argument. A path mismatch of % in the second stage will
produce an image below full scale. However, mismatch in the rst stage of the
modulator is critical and must be avoided.
A path mismatch of % on the input in the rst stage of the modulator will produce an
image signal which is only below the signal. Figure 4.29 shows the output
spectrum of the modulator with a capacitor mismatch of % between the input sampling
capacitors (during and ). Using layout techniques such as common-centroid, good
capacitor matchingin the order of %can be achieved. A capacitor mismatch of
% will reduce the power of image signal to about below the signal power. This
kind of accuracy, ten bits, is acceptable for some high-speed wide-band applications, such
as cable modems and PCS basestations.
Other methods of overcoming mismatch error, which have previously been applied to
lowpass modulators, include a four-phase clocking scheme proposed by Ribner
5
45 dB
1
40 dB
1

1

2
48 49 50 51 52
150
100
50
0
0 20 40 60 80 100
150
100
50
0
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
(
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
(
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
Figure 4.29: Output spectrum of the double-sampled bandpass sigma-delta
modulator with 1% capacitor mismatch between the two paths. Note that
the image power is 40 dB below the signal power.
0.1
0.1 60 dB
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 116
[Ribner91], a switching scheme that converts the capacitive mismatch into an additive out
of band noise [Hurst92] [Burmas95], and a method of using bilinear integrator [Yang94].
Finite Opamp Gain
Finite opamp gain causes both phase and gain errors in the ideal transfer function of a
double-sampled resonator. The resonant frequency of the double-sampled SC resonator
due to nite opamp gain is shifted by an angle from the -axis. If the same opamp
is used in both delay cells and , using (4-83) the phase error in the
location of the poles of the double-sampled SC resonator is
. ( 4-84 )
Thus, increasing the opamp DC gain and/or reducing the opamp input capacitance reduces
the phase error. The frequency of the notch lter (for noise transfer function) will be
shifted by where
. ( 4-85 )
In a fourth-order bandpass modulator, the quantization noise slope is ,
reaching its minimum at the resonant frequency. If the resonant frequency is shifted by
, the in-band noise will be increased by approximately
. ( 4-86 )
For a penalty in SNR, the opamp gain must be larger than the oversampling ratio
by a factor of (about ), if the input capacitance of the opamp is equal to the
sampling capacitor.
Noise
The RC thermal noise associated with the different capacitors and switches in a double-
sampled is less than the simple SC modulator because fewer capacitors are
involved. Using the result of noise analysis in section 4.2, the total input referred thermal

dR0
j
C
S1
C
S2
C
S
= =

dR0
C
in
C
S
--------
1
A
--- =
f
f
2 f
s
2
--------
dR0

C
in
C
S
--------
OSR
A
-----------
2BW

------------ = =
15 dB/octave
f
S
B
15
BW ( ) 2
--------------------- f
60

----- -
C
in
C
S
--------
OSR
A
----------- = =
1.5 dB
12.7 22 dB
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 117
noise associated with switches and opamp in a fully differential double-sampled SC
modulator is
. ( 4-87 )
Compared to the total noise of a simple SC bandpass modulator, this is smaller by a
factor of times. The in-band input referred thermal noise will be
. ( 4-88 )
4.6 Implementation
Fourth-order bandpass modulators in Figure 4.21 and Figure 4.27 were designed and
fabricated in a m double-poly CMOS process (HCMOS5a from SGS-Thomson).
Chip microphotographs of the simple SC bandpass and the double-sampled bandpass
modulator are shown in Figure 4.30 and Figure 4.31 respectively. The active chip area of
both modulators is about mm
2
.
HCMOS5a technology offers MOSFETs with a channel length of m and a high
quality poly-to-poly capacitor, with a capacitance per unit area of fF/m
2
. Some
v
nT
2 17.8kT
C
u
----------------- =
1.65
v
nT
2 17.8
OSR
-----------
kT
C
u
------ =
0.5
1.1
Figure 4.30: Chip microphotograph of the fourth-order SC bandpass
sigma-delta modulator
0.5
1.1
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 118
MOSFET parameters in this technology are listed in Table 4.1.
The main objective of the design was to demonstrate high-speed SC capabilities in
submicron CMOS technologies. In [Singor94], it is shown that SC circuits operating at
are feasible in a m BiCMOS process. Here, the target clock frequency was
set to be . Therefore the IF frequency was at .
An interesting application of the bandpass modulator is in A/D conversion of narrow-
band ( - ) signals in high-speed RF modems. The required dynamic range
of these A/D converter depends on the specic system architecture. Typically, a SNDR of
about is needed.
The target specication for the bandpass modulator is given in Table 4.2.
Parameters nMOSFET pMOSFET
Vt (10 m/0.5 m) 600 mV 600 mV
Isat (@ Vg=Vd=3.3 V) 0.33 mA/m 0.15 mA/m
120 A/V
2
31 A/V
2
Table 4.1: Some MOSFET parameters in HCMOS5a process
Figure 4.31: Chip microphotograph of the fourth-order double-sampled SC
bandpass sigma-delta modulator
C
ox
40 MHz 0.8
80 MHz 20 MHz
200 kHz 1 MHz
60 dB
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 119
The oversampling ratio of this modulator is . An ideal fourth-order bandpass
modulator with an OSR of can achieve a maximum SNR of .
To achieve high speed at moderate power, the unit capacitors are chosen to be as low as
. The total in-band noise of the single-sampled modulator (4-78) with
is calculated to be less than relative to a peak-to-peak signal. In
the following, the design of switches, opamp, and comparator circuits is described.
Switch Design
In stray insensitive SC circuits, typically the signal is sampled on a capacitor by means of
two turned-on MOSFET switches. For example in the SC amplier of Figure 4.5a, during
the input is sampled on through and switches. The on-resistance of the
switches along with the sampling capacitor constitutes an RC circuit. The sampled signal
on has the following exponential behavior:
. ( 4-89 )
Therefore, at the end of the sampling phase ( ), the input voltage is sampled on
with a settling error given by the term in the parentheses of (4-89). For a % settling
error in (the sampling period), the on-resistance of each MOSFET switch must be
less than . For a better xed charge cancellation, equal size pMOSFET and
nMOSFET switches are utilized. Eldo simulations were carried out to nd the exact value
of the MOSFET aspect ratios. Figure 4.32 shows the simulated on-resistance of a parallel
nMOSFET and pMOSFET switches with . The worst case on-
resistance is about .
Parameter Specication
IF frequency 20 MHz
Bandwidth 1 MHz
SNDR ~ 60 dB
Power < 100 mW
Table 4.2: Target specication for the bandpass modulator
40
40 62 dB
300 fF kT C
OSR 40 = 76 dB 2 V

1
C
s
S1 S2
C
s
v
C
s
v
ip
1 e
t RC
s

( ) =
t T
s
2 =
C
s
0.1
4.5 ns
560
W L 40 m 0.5 m =
333
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 120
Operational Transconductance Amplier Design
For high-speed SC operation, the unity gain frequency of the opamp must be 5 to 10 times
greater than the clock frequency [Gregorian86]. For a % settling error in half a clock
period, the unity gain frequency of the opamp (with the worst case capacitive load) must
be 7 times greater than the clock frequency. The worst case opamp load in our design is
about . Thus, for clock frequency the unity-gain frequency of the opamp
driving a load must be greater than .
The required DC gain of the opamp depends on the oversampling ratio of the modulator.
In section 4.4.1, it was shown that for a penalty in SNR at an oversampling ratio of
, the opamp DC gain must be at least .
For large input signals, slewing response of the opamp determines the maximum speed of
operation. During the non-overlapping phase, the opamp is in an open-loop conguration
and its output levels are typically clipped to a voltage close to the rails. A fast slew rate of
is chosen to bring the output voltages quickly to the workable levels of and
. For the worst case opamp load of , a bias current of at each output
stage is required.
A single stage cascode opamp (also called a telescopic opamp [Senderow94]) is used to
0 0.5 1 1.5 2 2.5 3
0
50
100
150
200
250
300
350
Figure 4.32: Transmission gate switch on-resistance vs. signal level
Input voltage (V)
O
n
-
r
e
s
i
s
t
a
n
c
e

(
O
h
m
)
0.1
1 pF 80 MHz
1 pF 560 MHz
3 dB
40 53 dB
1 V/ns 1.4 V
2.4 V 1 pF 1 mA
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 121
achieve the high speed and adequate DC gain needed for the opamp. The schematic of a
fully differential cascode opamp designed to fulll these requirements is shown in Figure
4.33. A continuous time common-mode feedback circuit sets the output common mode to
the desired value. Resistors in the common-mode feedback circuit have a high value of
to ensure the opamp DC gain does not drop below . The capacitors in the
common mode feedback circuit have a value of .
Dimensions of all the transistors used in the opamp are listed in Table 4.3, and transistor
sizes for the common mode feedback are given in Table 4.4.
MOSFET N0 N1 N2 N3 N4 P1 P2 P3 P4 P5 P6
W (m) 400 200 200 200 200 360 360 240 240 120 120
L (m) 0.7 0.5 0.5 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7
Table 4.3: Transistors sizes used in the opamp
MOSFETs NC0 NC1 NC2 PC1 PC2 PC3 PC4
W (m) 133 80 80 120 120 120 120
L (m) 0.7 0.5 0.5 0.7 0.7 0.7 0.7
Table 4.4: Transistor sizes used in the CMFB circuit
68 k 54 dB
400 fF
V
ip V
in
V
on
V
op
V
b1
V
b3
V
b4
V
b5
V
cm
V
cm
N0
N1 N2
N3 N4
P1 P2
P5 P3
P4
P6
V
ocm
V
b1
V
b3
V
b4
NC0
NC1 NC2
NC3
NC4
PC1 PC2
PC3
PC4
V
cm
V
op
V
on
C1
R1
R2
C2
Figure 4.33: Fully differential cascode opamp
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 122
This opamp was simulated in Eldo using SPICE level 3 MOSFET models. Output
conductance of transistors is poorly modeled in SPICE level 3 models. Therefore,
simulations typically predict an optimistically high DC gain for the opamp. A safety
margin of was added to the required simulated opamp DC gain (not including the
loading by resistor divider in the CMFB circuit) because of this modelling error. The
opamp was simulated by itself and the DC gain was about . The resistor divider in
the CMFB circuit reduces the DC gain to .
Simulated characteristics of the complete opamp at 3.3V power supply, bias current
and output load are summarized in Table 4.5.
The settling time of the delay circuit was simulated in Eldo using the schematic of Figure
4.35. In the modulator of Figure 4.21, the worst case settling time happens when
, , and . Settling time to % of the full scale in this
conguration is about , as shown in Figure 4.36.
Comparator
In a modulator circuit, the required specication of the comparator is relatively easy to
achieve. The comparator hysteresis can be modelled as an additive white noise at the input
12 dB
Figure 4.34: Simulated open loop gain (solid line) and phase (dotted line) of
the cascode opamp for 1 pF load capacitance
Frequency (Hz)
G
a
i
n

(
d
B
)

a
n
d

P
h
a
s
e

(
d
e
g
r
e
e
)
10
0
10
5
150
100
50
0
50
66 dB
54 dB
2 mA
1 pF
C
S
2C
u
= C
H
C
u
= C
L
C
u
= 0.1
4.9 ns
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 123
of the comparator. Both the input referred noise and comparator hysteresis are noise-
shaped (similarly to quantization noise) by the feedback loop and will be band-rejected
around the center frequency ( ). Eldo SC simulations of the fourth-order
modulators show that for a hysteresis voltage of % of the full scale (reference levels),
the in-band noise power is increased by about .
The schematic of a fully differential comparator used in the design of both modulators is
shown in Figure 4.37. The rst stage is a preamplier with a gain of and a unity
gain bandwidth of . The second stage is a cross-coupled latch reset by . Gain
and unity gain bandwidth of the second stage are and respectively. This
C
S
C
H
V
in
V
op
V
on
C
H
C
S
C
L
C
L
Figure 4.35: Test structure for settling time simulation
0 1 2 3 4
x 10
8
1.5
1
0.5
0
0.5
1
1.5
Figure 4.36: Worst case settling time simulation in Eldo.
Time (ns)
D
i
f
f
e
r
e
n
t
i
a
l

i
n
p
u
t

(
s
o
l
i
d

l
i
n
e
)

a
n
d
d
i
f
f
e
r
e
n
t
i
a
l

o
u
t
p
u
t

(
d
o
t
t
e
d

l
i
n
e
)
f
s
4
10
1.5 dB
22 dB
650 MHz N5
28 dB 620 MHz
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 124
comparator is followed by a cross-coupled NAND latch.
The transistor dimensions in this circuit are listed in Table 4.6.
In both fourth-order bandpass modulators, this comparator is followed by a latch.
Thus, the outputs of the comparator have to drive a single logic gate with an input
capacitance of . For a differential input signal, the delay time (clock going
Parameter Value
DC gain 54 dB
Unity gain frequency 650 MHz
Phase Margin
Slew rate 1000 V/s
Differential Output swing 2 V
Power dissipation
(including CMFB circuit)
8.8 mW
Table 4.5: Simulated characteristics of opamp for 1 pF load capacitance
v
IP
v
IN
V
b1
N0
N1 N2
P1 P2
P3
P4
N3 N4
N5
P5 P6 P7 P8
v
ON
v
OP
ck
Figure 4.37: Fully differential comparator
70
25 fF 2 mV
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 125
low and output becoming ready) of the comparator driving capacitor loads is about
. The power consumption of the comparator at is about .
4.7 Measurement Results
This section describes measured results for the fourth-order bandpass modulator and
the double-sampled fourth-order bandpass modulator. Both modulators were packaged
in a 60-pin high speed metal package and were tested separately. A PCB was designed for
testing the modulator. All the reference voltages, and reference currents needed for the
modulators were generated on the PCB board using voltage regulators and resistors.
4.7.1 Fourth-Order Bandpass Sigma-Delta Modulator
The fourth-order SC bandpass modulator was tested at a clock frequency of
using a supply voltage of 3.3V. Measured output spectrum for this modulator for a
sinusoid signal, with an amplitude of below full scale, is shown in
Figure 4.38.
This output spectrum is generated in Matlab, by performing an FFT on bits of the
modulator output captured by a logic analyzer. Measured maximum SNR for this
modulator is in a bandwidth of . This value is less than the expected
theoretical value of .
Such a low SNR can be caused by a number of circuit imperfections, including capacitor
mismatch and low opamp gain. In this process, poly-poly capacitors have good matching
properties and unit capacitors used in this modulator are expected to match within
%. For an oversampling ratio of , this capacitor mismatch reduces the SNR by only
.
Unfortunately, a stand alone opamp circuit was not included in the test chip due to the
MOSFET N0 N1 N2 N3 N4 N5 P1 P2 P3 P4 P5 P6 P7 P8
W (m) 200 200 200 4 4 8 50 50 50 50 10 1.2 1.2 10
L (m) 1 0.5 0.5 1 1 0.5 2 2 2 2 0.5 1 1 0.5
Table 4.6: Comparator transistor sizes
50 fF
2 ns 3.3 V 3 mW
80 MHz
20.1 MHz 10 dB
65536
42 dB 1 MHz 20 dB
62 dB
300 fF
1 40
1 2 dB
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 126
limited chip area available. Therefore, opamp gain can not be measured by itself. Four
indirect methods used to estimate the opamp gain consistently indicate a low DC gain of
about .
First, the output conductances of a number of m MOSFETs were measured. The
measured output conductance was typically lower than the simulated value by a factor of 3
to 3.5. Since a cascode architecture is employed in this opamp, the DC gain of the
amplier is reduced by about (DC gain is proportional to ). The estimated
opamp DC gain is .
Second, expanding the view of the output spectrum around the resonant frequency
indicates that the notch is shifted by about , as shown in Figure 4.39.
In section 4.4.1, it was shown that a low opamp gain can cause a shift in the notch
frequency. For a bandwidth of , the shift in notch frequency is , and thus
according to (4-72), SNR is reduced by at least . Using equation (4-73), the opamp
gain is estimated to be .
Third, a low opamp gain reduces the gain of the resonator. Using equation (4-76) and
, the gain of the resonator at resonance is about . For an
0 10 20 30 40
100
80
60
40
20
0
Figure 4.38: Measured output spectrum of the fourth-order bandpass
sigma-delta modulator for an input signal of 10 dB below full scale.
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
(
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
40 46 dB
0.7
20 dB r
o
2
46 dB
500 kHz
1 MHz BW 2
15 dB
40 dB
A 40 dB = H
R0
6.25 =
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 127
oversampling ratio of , the ratio of the oversampling ratio to resonator gain is
. From Figure 4.25, in-band quantization noise increases by about
. That is in agreement with the measured SNR of which is lower than
the expected .
The fourth method of estimating the opamp gain indicates an opamp gain of and is
discussed in the next section.
4.7.2 Double-Sampled Fourth-Order SC Bandpass Sigma-Delta Modulator
The double-sampled bandpass SC modulator was tested at a clock frequency of
. Thus, the effective sampling rate is . Figure 4.40 shows the output
spectrum of the modulator for an input sinusoid at with an amplitude of
below full scale.
The output bit-stream was captured by a logic analyzer for 16384 clock cycles. In Matlab,
a 16384-point FFT was carried out to compute the output spectrum. The image signal is at
and is below the signal. This suggests that the capacitor mismatch is
about %. The SNDR of this modulator is limited to for a bandwidth.
Just as for the simple SC modulator, low opamp gain has shifted the notch frequency to a
17 18 19 20 21 22 23
120
100
80
60
40
20
0
Figure 4.39: Expanded view of the output spectrum around the notch. Note that
the notch frequency is shifted by about 500 kHz to the left (lower frequency)
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
(
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
40
OSR ( ) H
R0
6.4 =
20 dB 42 dB 20 dB
62 dB
40 dB
80 MHz 160 MHz
40.8 MHz 6 dB
39.2 MHz 39 dB
1 30 dB 5 MHz
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 128
lower value than the expected . Figure 4.41 illustrates an expanded view of the
output spectrum around .
0 20 40 60 80
100
80
60
40
20
0
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
(
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
Figure 4.40: Measured output spectrum of the double-sampled fourth-order SC
bandpass sigma-delta modulator for an input signal of 10 dB below full scale. Note
that image signal is about 39 dB below the fundamental signal.
40 MHz
40 MHz
36 38 40 42 44
100
80
60
40
20
0
Frequency (MHz)
M
a
g
n
i
t
u
d
e

(
d
B
)
(
R
e
l
a
t
i
v
e

t
o

s
i
g
n
a
l

p
o
w
e
r
)
Figure 4.41: Expanded view of the output spectrum around the notch.
Note that the notch frequency is shifted by about 1 MHz.
Chapter 4 High-Speed SC Fourth-Order Bandpass Sigma-Delta Modulators 129
As we can observe in Figure 4.41, the notch frequency of the modulator is shifted to about
, which is below the expected value of .
Using equation (4-84), the opamp DC gain is calculated to be . This is consistent
with the estimated opamp DC gain obtained in the previous section.
4.8 Summary
This chapter considered a -domain architecture for a fourth-order bandpass
modulator. This modulator is a direct map of a second-order lowpass modulator to
bandpass by transforming integrators to resonators.
In SC technology, an efcient method of implementing a resonator is to use two delay
cells in a negative feedback loop. Half delay and full delay SC circuits were described and
impacts of circuit non-idealities on the performance of these circuits were analyzed.
Specically, it was shown that nite opamp gain causes both a gain error and a phase error
in the operation of a SC delay circuit. In a SC resonator, nite opamp gain causes a change
in the resonant frequency.
Two fourth-order SC bandpass modulators were presented. The rst one is a single-
sampled SC circuit and is shown to be faster than a previously reported one. The second is
a double-sampled SC circuit. Results of Eldo simulations for these modulators were
presented.
Finally, the two bandpass modulators were designed and fabricated in a m CMOS
process. Both modulators operate at a clock frequency of . The SNR of the
single-sampled modulator is in the bandwidth of . This is about less
than the expected value of . A low opamp DC gain appears to be responsible for the
reduced SNR. Three indirect methods of estimating the opamp DC gain indicate a low
opamp DC gain of to . A SC amplier circuit that is insensitive to low
opamp gain such as [Martin87], would be a better choice for the next implementation. The
double-sampled modulator exhibits an image signal as low as relative to the
signal. This is probably caused by capacitor mismatch in the rst stage.
39 MHz 1 MHz 40 MHz
40 dB
z
0.5
80 MHz
42 dB 1 MHz 20 dB
62 dB
40 dB 46 dB
40 dB
130
Chapter 5
SC Bandpass Sigma-Delta Modulator
Design In a Digital CMOS Process
As we discussed in Chapter 2, to be cost effective it is desirable to implement analog SC
circuits in standard digital CMOS processes where linear poly-to-poly capacitors are not
available. In a single-poly process, a relatively low specic value linear capacitor is
formed using poly and metal as electrodes and eld oxide as insulator. Another option is
to use MOSFET gate capacitors in the strong inversion or accumulation regime.
In this chapter, the linearity of MOSFET gate capacitors in strong inversion and
accumulation is studied rst. Measured CV-plots in a m CMOS technology will
show that MOSFETs biased in strong inversion are more linear than MOSFETs biased in
the accumulation regime due to a gate-poly depletion effect. Distortion caused by non-
linearity of capacitors in a SC amplier is then analyzed and some simulation results are
presented. Finally, the design of a fourth-order bandpass modulator, using a
pMOSFET transistor as a linear capacitor, is described.
5.1 MOS Capacitor
A MOS capacitor uses polysilicon and semiconductor as the two parallel plates and silicon
dioxide as insulator. In a CMOS process, gate poly and device well are used as electrodes
and the thin gate oxide serves as the insulating layer. Figure 5.1a shows the structure of a
MOS capacitor with p-well as the bottom plate. A MOSFET transistor is made by adding
source and drain to the sides of the MOS capacitor, as shown in Figure 5.1b.
0.5
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 131
MOS capacitance is dependent on the gate to bulk voltage and is strongly non-linear. For a
negative gate voltage , holes will be attracted to the surface (Si-SiO
2
interface) of
the p-type semiconductor. This mode is called accumulation and the MOS capacitor
resembles a parallel plate capacitor with a capacitance per unit area of
( 5-1 )
where is the oxide dielectric constant and is the oxide thickness. When the
applied gate voltage is , the holes are repelled from the surface and a negative
depletion layer is formed near the surface. In this regime, called depletion, the MOS
capacitor has two dielectrics (the gate oxide and the depleted silicon) in series. Thus, the
MOS capacitance in depletion mode is given by the series combination of the gate
capacitance ( ) and the depletion capacitance,
. ( 5-2 )
Here, is the semiconductor dielectric constant and is the depletion layer width. As
gate voltage is increased, the depletion layer width increases and hence the gate to bulk
capacitance decreases.
If the gate voltage is increased beyond the threshold voltage , the concentration of
attracted electrons at the surface will be greater than the concentration of the holes at the
P-type substrate
v
G
gate poly
gate oxide
Figure 5.1: Structure of (a) a MOS capacitor and (b) an nMOSFET transistor
P-type Bulk
n
+
n
+
Drain Gate
Source
(a) (b)
v
G
0 <
C
GB
C
ox

ox
t
ox
------- = =

ox
t
ox
0 v
G
V
t
< <
C
ox
C
GB
t
ox

ox
-------
d

si
------ +
,

_
1
=

si
d
v
G
V
t
>
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 132
surface. This condition is called strong inversion. The inversion layer below the oxide
provides the bottom plate of the capacitor, and the gate to bulk capacitance is given by the
oxide capacitance ( ). In the two-terminal MOS capacitor, the inversion layer is formed
by the thermal generation of carriers, which is a slow process. In a MOSFET capacitor, the
source terminal will provide carriers for the formation of the inversion layer. Thus, the
characteristic of a MOSFET capacitor at high frequency will be the same as the low
frequency C-V characteristic of the two-terminal MOS capacitor.
The theoretical C-V characteristic of an nMOSFET, using analytical results in
[Tsividis87], is shown in Figure 5.2.
As we can observe in the C-V plot, Figure 5.2, the MOSFET capacitance is relatively
linear (or weakly non-linear) in the accumulation and strong inversion regimes.
The capacitance of a voltage-dependent non-linear capacitor can be expressed in Taylor
series form by
. ( 5-3 )
Typically, voltage coefcients of the cubic and higher terms are small and the capacitance
can be approximated by the rst three terms in equation (5-3).
C
ox
5 0 5
0
0.2
0.4
0.6
0.8
1
Figure 5.2: Analytical C-V characteristics of an nMOSFET transistor
(Volts) v
GB
(
N
o
r
m
a
l
i
z
e
d

g
a
t
e
-
s
u
b
s
t
r
a
t
e

c
a
p
a
c
i
t
a
n
c
e
)
C
G
B
C
o
x

Accumulation Strong inversion

Depletion
C v ( ) C
0
1
1
v
2
v
2
+ + + ( ) =
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 133
The voltage coefcients of a MOSFET capacitance in strong inversion are given by
[Behr92]
( 5-4 )
and
. ( 5-5 )
Here, is the thermal voltage and is the bias voltage. In accumulation, the voltage
coefcients are given by similar expressions with being substituted with the at-band
voltage ( ). Therefore, the non-linearity of the MOSFET capacitor in strong inversion
and accumulation regions are theoretically almost identical.
In the above analysis, it is assumed that the poly gate is degenerately doped. In some
advanced processes, the poly gate is doped along with the source and drain diffusion. In
this case, the gate is not doped degenerately. A positive voltage on the gate electrode will
pull the electrons in the polysilicon to the top, and the bottom of the poly gate will be
depleted. Therefore, the effective dielectric thickness of the capacitor will increase. This
phenomenon, known as poly depletion, will cause a slight roll-off in the C-V curve in
the strong inversion region near the supply voltage.
Figure 5.3 illustrates C-V characteristics for an nMOSFET transistor in a m CMOS
technology obtained from silicon measurement (solid line) and simulation (dashed line)
using the MISNAN model. Note the negative slope in strong inversion of the measured
(solid line) C-V curves. As we can observe in this gure, poly-depletion is not modelled
by MISNAN and linearity of a MOSFET in the accumulation regime is optimistically
predicted to be high. Similarly, linearity of a MOSFET in the strong inversion regime is
predicted pessimistically to be low by the MISNAN model. Gate-poly depletion appears to
largely compensate the non-linearity of MOSFET capacitors in the strong inversion
regime.
The C-V characteristic of pMOSFET is shown in Figure 5.4.

1
2
t
V
R
V
t

2
------------------------ - =

2
2
t
V
R
V
t

3
------------------------ - =

t
V
R
V
t
V
FB
0.5
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 134
Figure 5.3: Measured (solid line) and simulated (dashed line)
C-V plot of an nMOSFET
(Volts) v
GB
(
N
o
r
m
a
l
i
z
e
d

g
a
t
e
-
s
u
b
s
t
r
a
t
e

c
a
p
a
c
i
t
a
n
c
e
)
C
G
B
C
o
x

4 2 0 2 4
0
0.2
0.4
0.6
0.8
1
Accumulation Strong inversion
Depletion
Figure 5.4: Measured (solid line) and simulated (dashed line)
C-V plot of a pMOSFET
(Volts) v
GB
(
N
o
r
m
a
l
i
z
e
d

g
a
t
e
-
s
u
b
s
t
r
a
t
e

c
a
p
a
c
i
t
a
n
c
e
)
C
G
B
C
o
x

4 2 0 2 4
0
0.2
0.4
0.6
0.8
1
Accumulation Strong inversion
Depletion
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 135
Both nMOSFET and pMOSFET are strongly non-linear in the range
and only weakly non-linear when MOSFETs are biased by more than in either
accumulation or strong inversion regimes. From the measured C-V plots, we can see that
both MOSFETs exhibit a better linearity in the strong inversion regime than in the
accumulation regime. This has been veried in Matlab and will be discussed below.
Using the polyt feature in Matlab (least squares algorithm), the rst ( ) and second
( ) order voltage coefcients of measured MOSFET capacitance are found for different
ranges of . Table 5.1 and Table 5.2 summarize the results for the nMOSFET and
pMOSFET transistors respectively.
For similar gate to substrate voltages, MOSFETs biased in strong inversion consistently
have a signicantly better linearity than MOSFETs operating in accumulation regime.
For low-voltage linear SC circuits, it is desirable to extend the linear portions of the C-V
Condition
Measured Simulated
Strong Inversion ( ) 0.0279 0.0050 0.0327 0.0045
Accumulation ( ) 0.125 0.0177 0.1457 0.0251
Strong Inversion ( ) 0.005 0.0012 0.0162 0.0016
Accumulation ( ) 0.045 0.0049 0.0114 0.0014
Table 5.1: nMOSFET capacitance voltage coefcients
Condition
Measured Simulated
Strong Inversion ( ) 0.0427 0.0077 0.0534 0.0079
Accumulation ( ) 0.1264 0.0180 0.1079 0.0182
Strong Inversion ( ) 0.0162 0.0027 0.0499 0.0064
Accumulation ( ) 0.0403 0.0036 0.0134 0.0017
Table 5.2: pMOSFET capacitance voltage coefcients
2 V v
GB
2 V < <
2 V

2
v
GS

1
V
1
( )
2
V
2
( )
1
V
1
( )
2
V
2
( )
2 V v
GS
3 V < <
3 V v
GS
2 V < <
3 V v
GS
4 V < <
4 V v
GS
3 V < <

1
V
1
( )
2
V
2
( )
1
V
1
( )
2
V
2
( )
3 V v
GS
2 V < <
2 V v
GS
3 V < <
4 V v
GS
3 V < <
3 V v
GS
4 V < <
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 136
curve closer to the axis, so that less bias voltage will be required to operate the
MOSFET in the strong inversion (or accumulation) regime. Low- natural MOSFETs
are suited very well for this purpose. Due to their low threshold voltage, natural
MOSFETs have a wider linear range in the strong inversion regime. Figure 5.5 shows the
C-V plots for both a natural MOSFET and a threshold adjusted MOSFET transistor.
Note that the linear range of natural nMOSFET capacitance is increased (compared to that
of the threshold adjusted nMOSFET) in the strong inversion region at the expense of a
reduced linear range in accumulation.
5.2 Distortion in SC Amplier Caused by Non-linear Capacitors
Non-linear capacitors cause distortion in SC circuits. Consider a single-ended SC
amplier as shown in Figure 5.6. Capacitors are assumed to have a similar non-linearity
and their capacitances are approximated by
( 5-6 )
v
GB
0 =
V
t
4 2 0 2 4
0
0.2
0.4
0.6
0.8
1
Figure 5.5: Simulated C-V characteristics of a low-V
t
natural nMOSFET
(dashed line) and a threshold adjusted nMOSFET (solid line)
(Volts) v
GB
(
N
o
r
m
a
l
i
z
e
d

g
a
t
e
-
s
u
b
s
t
r
a
t
e

c
a
p
a
c
i
t
a
n
c
e
)
C
G
B
C
o
x

C
S
C
S0
1
1
v
2
v
2
+ + ( ) =
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 137
and
. ( 5-7 )
Assuming an ideal opamp, charge conservation on the sampling capacitor ( ) and the
holding capacitor ( ) during and yields
. ( 5-8 )
If the capacitors are linear, the output of the SC amplier is a scaled version of the input
signal delayed by a half-clock period.
For non-linear capacitors, substituting (5-6) and (5-7) into (5-8), the above difference
equation becomes
. ( 5-9 )
For and , the input-output difference equation can be approximated by
. ( 5-10 )
The above transfer characteristic indicates that a non-linear capacitor causes non-linear
C
H
C
H0
1
1
v
2
v
2
+ + ( ) =
C
S
C
H
v
ip
v
op
C
L
Figure 5.6: A single-ended SC amplier
+ -
+ -
C
S
C
H

1

2
v
op
n
1
2
--- +
,
_
C
S
C
H
-------- v
ip
n ( ) =
v
op
n
1
2
--- +
,
_
C
S0
C
H0
-----------
1
1
v
ip
n ( )
2
v
ip
2
n ( ) + +
1
1
v
op
n 1 2 + ( )
2
v
op
2
n 1 2 + ( ) + +
---------------------------------------------------------------------------------------------- - v
ip
n ( ) =

1
1
2
1
v
op
n
1
2
--- +
,
_
C
S0
C
H0
----------- v
ip
n ( )
1
v
ip
n ( ) v
op
n
1
2
--- +
,
_
v
ip
n ( )
2
v
ip
2
n ( ) v
op
2
n
1
2
--- +
,
_
v
ip
n ( ) + +

' ;

=
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 138
errors at the output of the SC amplier.
Let us assume that the input signal is a sampled sinusoid given by
( 5-11 )
If the non-linear coefcients are small, the output of the amplier in the error terms of
equation (5-10) can be approximated to the rst order by the output of an ideal SC
amplier,
. ( 5-12 )
Substituting (5-11) and (5-12) into (5-10) and using the following trigonometric identities
, ( 5-13 )
equation (5-10) becomes
( 5-14 )
The second term in the brace brackets on the RHS of the above equation is the output at
the fundamental frequency. The rst term is an offset, the third and fourth terms are the
error terms containing the second and third harmonics of the signal. Using the following
denition for -th harmonics,
( 5-15 )
the second and third harmonics for the SC amplier circuit are found to be approximately
( 5-16 )
and
v
ip
n ( ) V
ip
nT ( ) cos =
v
op
n
1
2
--- +
,
_
C
S0
C
H0
----------- V
ip
nT ( ) cos =
A cos ( )
2 1 2A cos +
2
------------------------- and A cos ( )
3 3 A cos 3A cos +
4
-------------------------------------- = =
v
op
n
1
2
--- +
,
_
C
S0
C
H0
-----------

1
2
------ 1
C
S0
C
H0
-----------
,

_
V
ip
1
3
2
4
---------- 1
C
S0
2
C
H0
2
-----------
,


_
V
ip
2
+ V
ip
nT ( ) cos

1
2
------ 1
C
S0
C
H0
-----------
,

_
V
ip
2
2nT ( ) cos

2
4
------ 1
C
S0
2
C
2
-----------
,


_
V
ip
3
3nT ( ) cos
+
+ +

'
;

=
k
HD
k
Signal Amplitude at k ( )
Signal Amplitude at Fundamental ( )
------------------------------------------------------------------------------------------- - =
HD
2

1
2
------ 1
C
S0
C
H0
-----------
,

_
V
ip

Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 139

. ( 5-17 )
In a fully differential circuit, the second harmonic component is rejected at the output.
Example 5.1: In the SC amplier of Figure 5.6, the gain of the circuit is , opamp and
switches are ideal, and capacitors are poly-poly capacitors with voltage coefcients of
and . For a peak-to-peak input sinusoid, the
second and the third harmonics are calculated from (5-16) and (5-17) respectively to be
and . If capacitors are implemented with
pMOSFETs in strong inversion with voltage coefcients of and
, the distortions will be and for
a input signal.
5.3 A SC Delay Circuit Using pMOSFET Capacitors
In section 5.1, it was shown that pMOSFETs biased in strong inversion ( )
exhibit a weakly non-linear behavior over a small gate-substrate voltage range. For
instance, measured C-V characteristics show that for a signal swing in the range of
, the voltage coefcients of the MOSFET capacitor are
and . The schematic of a fully differential SC gain
stage with unity gain during and a gain of half during , using pMOSFET capacitors,
is shown in Figure 5.7. The differential structure cancels even-order harmonics, reducing
the importance of .
Transistors and are equal size pMOSFETs and is made of two pMOSFETs
identical to . All pMOSFET capacitors are biased to operate in strong inversion by
means of different input and output common mode voltages. The gates of the pMOSFETs
are connected to the input common-mode level and the bulk terminals (which is shorted to
the drain and the source) are connected to the (higher) output common-mode level. For a
signal swing of with respect to , the operating gate-to-substrate of the
pMOSFET voltage is
HD
3

2
12
------ 1
C
S0
C
H0
-----------
,

_
2
V
ip
2

0.5

1
10 ppm/V =
2
10 ppm/V
2
= 2 V
HD
2
102.5 dB = HD
3
110 dB =

1
42 kppm/V =

2
7.7 kppm/V
2
= HD
2
45.6 dB = HD
3
78.4 dB =
1 Vpp
v
GB
V
tp
<
1 V
3 V v
GB
2 V < <

1
42 kppm/V =
2
7.7 kppm/V
2
=

1

2

1
M1 M3 M2
M1
v
pp
V
ocm
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 140
. ( 5-18 )
If the input common mode voltage is set to and the output common-mode is set to
, then with a peak-to-peak signal the pMOSFET will operate in the strong
inversion regime with a gate-to-bulk voltage of .
For a sinusoid input signal, the output signal will be during , with a
delay of a half-clock period. Due to the weak non-linearity of the pMOSFETs in strong
inversion, a third harmonic is also generated. The voltage coefcient that is
responsible for the third harmonics was calculated (Table 5.1) to be in the
operating regime of . The third harmonic distortion is calculated from
(5-17) to be .
This circuit was simulated in Eldo using an ideal opamp with a gain of , ideal
switches with an on-resistance of , and a pMOSFET as
unit capacitor. The non-overlapping clock had a frequency of and the input
signal was a sinusoid with a frequency of . The output spectrum, Figure
Figure 5.7: SC delay cell using pMOSFET capacitors
v
ip
v
in
v
op
v
on
M1
M2
M2
M3
M3
V
icm
V
ocm

2
M1
V
icm
V
ocm
v
pp
2
-------- +
,
_
v <
GB
V
icm
V
ocm
v
pp
2
--------
,
_
<
1 V
3.5 V 1 V
3 V v
GB
2 V < <
1 Vpp 0.5 Vpp
2

2
7.7 kppm/V
3 V v
GB
2 V < <
78.4 dB
100 dB
1 W L 30 m 10 m =
100 MHz
1 Vpp 9.99 MHz
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 141
5.8, has a tone at the input frequency (its fundamental frequency) and a third harmonic
whose power is below the output power at the fundamental frequency.
As we can see in Figure 5.8, no second harmonic is generated at the output due to fully
differential implementation of this circuit. In a real implementation, mismatches and
offsets would cause a non-zero .
During , the output is ideally an exact replica of the input delayed by a full clock
period. Since the gate to source voltage of the pMOSFET capacitors and are the
same, no distortion should appear at the output. This argument is veried by simulation
and Figure 5.9 illustrates the output spectrum during .
5.4 A Fourth-Order SC Bandpass Sigma-Delta Modulator Using
pMOSFET Capacitors
The fourth-order bandpass of Figure 4.21 can be implemented in a standard digital
CMOS process by replacing all the poly-poly capacitors with pMOSFET capacitors. The
modied schematic is shown in Figure 5.10, where pMOSFET capacitors are biased in
strong inversion. In this circuit all the pMOSFET capacitors are identical with a gate area
of , except for the two marked by asterisk which have a gate area of .
80 dB
0 10 20 30 40 50
160
140
120
100
80
60
40
20
0
Frequency (MHz)
A
m
p
l
i
t
u
d
e

(
d
B
)
R
e
l
a
t
i
v
e

t
o

o
u
t
p
u
t

p
o
w
e
r
a
t

f
u
n
d
a
m
e
n
t
a
l

f
r
e
q
u
e
n
c
y
Figure 5.8: Output spectrum of the fully differential SC gain stage,
Figure 5.7, during .
2
HD
2

1
M1 M3

1
WL 2WL
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 142
As was mentioned in the previous section, a unity gain operation (not involving
summation) does not produce any harmonics. Thus, operations involving distortion
include transitions from to in the rst and second delay cells, as well as transition
from to in the third delay cell. The fourth delay cell has a unity gain (in both
phases) and is not used in a summing conguration, and therefore is free from any
distortions.
This circuit was simulated in the Eldo analog simulator using nearly ideal opamps (DC
gain of ), ideal switches ( on-resistance), and the pessimistic MISNAN model
for pMOSFET capacitors. All pMOSFET capacitors are biased into in strong
inversion by selecting input and output common mode levels to be at and
respectively. Figure 5.11 shows the output spectrum of the modulator for an input sinusoid
of below full scale amplitude and a frequency of . The non-overlapping
clock frequency was set to . Simulated SNR is and for
bandwidths of and respectively.
Design Considerations
In order to properly bias pMOSFET capacitors in the strong inversion regime, an opamp
0 10 20 30 40 50
160
140
120
100
80
60
40
20
0
Frequency (MHz)
A
m
p
l
i
t
u
d
e

(
d
B
)

r
e
l
a
t
i
v
e

t
o

o
u
t
p
u
t

p
o
w
e
r

a
t
f
u
n
d
a
m
e
n
t
a
l

f
r
e
q
u
e
n
c
y
Figure 5.9: Output spectrum of the fully differential SC unity gain
stage, Figure 5.7, during
1

1

2

2

1
60 dB 1
2.5 V
1 V 3.5 V
6 dB 24.9 MHz
100 MHz 97 dB 63 dB
200 kHz 1 MHz
C
h
a
p
t
e
r

5

S
C

B
a
n
d
p
a
s
s

M
o
d
u
l
a
t
o
r

D
e
s
i
g
n

i
n

a

D
i
g
i
t
a
l

C
M
O
S

P
r
o
c
e
s
s
1
4
3
Figure 5.10: A fourth-order bandpass sigma-delta modulator using pMOSFET capacitors
V
rn
V
rp
V
rp
V
rn
* *
*
*
V
ip
V
in
V
op
V
on
V
rp
V
rn
1-bit
D/A
V
icm
V
ocm
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 144
with different input and output common mode levels is required. An efcient opamp
architecture having different input and output common mode voltages is a non-folded
cascode opamp, as discussed in section 4.6. The schematic of the opamp (not including
the CMFB circuit) is repeated in Figure 5.12. The input common-mode level is and
the output common mode voltage is at . The output signal swing range is
with respect to the output common-mode voltage. Simulated characteristics of the opamp
Frequency (MHz)
A
m
p
l
i
t
u
d
e

(
d
B
)

r
e
l
a
t
i
v
e

t
o

o
u
t
p
u
t
p
o
w
e
r

a
t

f
u
n
d
a
m
e
n
t
a
l

f
r
e
q
u
e
n
c
y
Figure 5.11: Output spectrum of the fourth-order SC bandpass sigma-delta
modulator of Figure 5.10 for an input signal of 6dB below full scale
Frequency (MHz)
A
m
p
l
i
t
u
d
e

(
d
B
)

r
e
l
a
t
i
v
e

t
o

o
u
t
p
u
t
p
o
w
e
r

a
t

f
u
n
d
a
m
e
n
t
a
l

f
r
e
q
u
e
n
c
y
0 10 20 30 40 50
140
120
100
80
60
40
20
0
24 24.5 25 25.5 2
140
120
100
80
60
40
20
0
V
ip V
in
V
on
V
op
V
b1
V
b3
V
b4
V
b5
V
cm
V
cm
N0
N1 N2
N3 N4
P1 P2
P5 P3
P4
P6
Figure 5.12: A fully differential cascode opamp
1 V
3.5 V 0.5 V t
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 145
designed in the option of the HCMOS5a process ( m CMOS from SGS-
thompson) are given in Table 5.3.
Power supply voltage was and the tail current was .
The design considerations for capacitor size and switch on-resistance are similar to those
described in section 4.6 of the previous chapter.
If low threshold natural MOSFETs are available in the process, they can be used as
switches, pMOSFET capacitors, and as input differential pair transistors ( and in
Figure 5.12) to further optimize the circuit. A lower threshold voltage helps reduce the on-
resistance of switches, increases the linear region of the pMOSFET capacitor in strong
inversion, and reduces the input common-mode level.
5.4.1 Linear Charge Processor Viewpoint
In section 2.5.3, it was shown that SC circuits are linear charge processors from input to
output. To a rst-order approximation, linearity of SC circuits in the charge domain is
independent of the non-linearity of the capacitors. However, since external signals are
typically in the voltage domain, a linear input and output converter are
required.
The output of a SC modulator is a digital bit stream and as such no linear
converter is needed at the output. Input capacitors are the only critical components that
Parameter Value
DC gain 61 dB
Unity gain frequency 360 MHz
Phase Margin
Slew rate 500 V/s
Differential Output swing 2 V
Power dissipation
(not including CMFB circuit)
5 mW
Table 5.3: Simulated characteristics of opamp for 1pF load capacitance
5 V 0.5
63
5 V 1 mA
N1 N2
V Q Q V
Q V
Chapter 5 SC Bandpass Modulator Design in a Digital CMOS Process 146
must be linear.
A metal-metal capacitor seems to be a good choice for input capacitors. Mismatch
between a metal-metal capacitor and a MOSFET capacitor is expected to be large,
however, that causes a gain error which is not important in a modulator.
Our unity gain delay circuit is a special case of this charge domain principle where the
circuit is also linear in the voltage domain.
5.5 Summary
In this chapter, non-linearity of MOSFET capacitors in a m CMOS process was
studied. It was shown that MOSFETs biased in the strong inversion regime have a better
linearity than MOSFET capacitors biased in the accumulation regime because gate-poly
depletion partially compensate the non-linearity in strong inversion. The voltage
coefcients of a pMOSFET biased in strong inversion are measured to be
and , for a voltage swing of . The impact
of capacitor non-linearity on the performance of SC delay circuit was then analyzed.
Finally, the design of a fourth-order bandpass sigma-delta modulator tolerant to MOSFET
capacitors was presented along with Eldo simulation results.
0.5
2.5 V

1
42.7 kppm/V =
2
7.7 kppm/V
2
= 0.5 V t
147
Chapter 6
Conclusions and Future Work
The rapid advance of CMOS technology into the deep submicron regime continues to
improve the speed and packing density of integrated circuits. Device miniaturization, in
deep submicron geometries, requires supply voltage down-scaling to ensure reliability. In
the rst part of this thesis, low-voltage circuits were considered in detail.
In deep submicron CMOS technologies, velocity saturation causes circuit speed
improvement to slow down from 1.4X to about 1.2X every generation. Low voltage is also
known to compromise circuit speed. The second part of this thesis therefore focused on
high-speed SC circuit techniques.
Low cost implementation of a mainly digital mixed-signal circuit requires analog circuits
to be implemented in a standard digital CMOS process where double-poly is not available.
In the last part of this thesis, linear SC circuit techniques in a digital CMOS process were
investigated.
6.1 Summary
In Chapter 2, CMOS scaling in deep submicron was reviewed. In deep submicron
technologies, the supply voltage is being scaled down to assure device reliability. In
conjunction with the supply voltage, threshold voltage of MOSFETs is scaling down to
attain circuit speed. Low voltage analog and digital circuit techniques were reviewed. For
low-voltage analog circuits, SC and SI circuits were compared and it was shown that the
SC technique has advantages over the SI technique from a signal-to-noise ratio point of
view.
Chapter 6 - Conclusions and Future Work 148
Chapter 3 described low-voltage SC design techniques using low threshold voltage
MOSFETs. Two methods for achieving low- MOSFETs in current CMOS processes
were discussed. In the rst scheme, natural threshold voltage MOSFETs fabricated in a
dual poly gate CMOS processes (with ) were proposed for low-
voltage mixed-signal circuits. The second method took advantage of short-channel effects
and used short-channel MOSFETs as low-voltage analog switches.
Low threshold voltage MOSFETs are leaky and a detailed analysis of the effects of leaky
switches on the accuracy of SC circuits was provided. Methods of reducing the off-current
through MOSFET switches were described. These methods are (1) limiting the signal
swing, (2) adjusting the by back bias, and (3) using novel low-leakage series
transmission gate and composite switches.
Two experimental low-voltage SC sigma-delta modulators were presented. In the rst
design, an existing second-order modulator in a m BiCMOS process was
modied to operate at . The modication involved reducing the channel length for
all the switches from m to m. The new design operates at a clock frequency of
and achieves a SNDR of for an oversampling ratio of . In the second
design, a rst-order SC sigma-delta modulator using low threshold voltage natural
MOSFETs was reported. This modulator was tested at a clock frequency of . For
an oversampling ratio of the measured SNDR is about .
In Chapter 4, high-speed SC bandpass modulators were discussed. In the sampled-data
domain, a direct implementation of resonators for bandpass sigma-delta modulator
requires an efcient sample-and-hold circuit. A SC delay circuit was described and a novel
double-sampled SC delay circuit was introduced. The impacts of circuit non-idealities on
the performance of a simple SC delay cell and the double-sampled delay cell were
analyzed. Two SC implementations for a fourth-order bandpass modulator were
presented. The rst design was a high-speed SC modulator based on a SC delay circuit
and the second design was a double-sampled SC modulator, based on the double-
sampled SC delay cell. Both designs were implemented in a m CMOS process. The
single-sampled modulator was tested at an clock frequency. For an oversampling
ratio of the measured SNDR is about . The modulator consumes from a
V
t
V
t
200 300 mV
V
t
3.3 V 0.8
2.25 V
0.8 0.6
2 MHz 92 dB 256
1 V
1 MHz
128 54 dB
0.5
80 MHz
40 42 dB 50 mW
Chapter 6 - Conclusions and Future Work 149
power supply. The double-sampled modulator was also tested at . The
effective sampling frequency for this modulator is . Due to capacitor mismatch,
the image signal was about below the input signal. Measured SNDR is
(limited by the image) for an oversampling ratio of (bandwidth of ).
Chapter 5 explored the feasibility of using MOSFETs as linear capacitors in a SC circuit.
It was shown that in a m CMOS process, MOSFETs biased in strong inversion are
more linear than MOSFETs biased in the accumulation regime. An analysis of distortion
due to non-linearity of MOSFET capacitor in a SC delay cell was presented. Finally,
design of a SC fourth-order bandpass sigma-delta modulator using pMOSFET capacitor
was described.
6.2 Conclusions
Through analyses, simulations, and measurements of some experimental circuits, we
demonstrated that mixed-signal linear SC circuits
will scale down to at least .
can operate up to in a m CMOS using a double-sampled SC
technique.
are realizable in a standard digital CMOS process using MOSFET capacitors in strong
inversion or accumulation.
6.3 Future Work
High-performance SC design from the perspective of this thesis, namely at low voltages,
high speeds, and implemented in a digital CMOS process, needs further development.
Some promising areas of research are as follows:
Low-Voltage SC
In this thesis, we showed that low threshold voltage MOSFETs are suitable for
mixed-signal application. The next step is to integrate a second-order sigma-delta
modulator with the decimation lter in order to demonstrate high resolution at and
see if noise coupling from digital circuit will degrade the SNR performance.
3.3 V 80 MHz
160 MHz
40 dB 30 dB
16 5 MHz
0.5
1 V
160 MHz 0.5
1 V
1 V
Chapter 6 - Conclusions and Future Work 150
High-Speed SC
A major limitation of a double-sampled SC circuit is image problems caused by mismatch
between the two channels as well as non-uniform sampling. Architectures that are immune
to mismatch would be an interesting area for research. In a modulator, the effect of
channel mismatch might be compensated for by an LMS algorithm in DSP.
Linear SC in a Digital CMOS Process
In this dissertation, it was shown that poly-depletion causes MOSFETs to behave more
linearly in strong inversion than in accumulation regime. Further investigation and
implementation of some SC test circuits are required to verify this property.
In summary, analog SC circuit techniques remain viable and vital in the design of high-
performance mixed-signal circuits in deep submicron CMOS technologies.
151
Appendix A
MOSFET Equations
The I
DS
-V
DS
characteristic of MOSFET in strong inversion ( ) can be
approximated by an -power law [Sakurai90] as follows:
( A-1 )
is the threshold voltage of the MOSFET, is the velocity saturation index which is a
number less than 2, and is:
( A-2 )
In this equation, is the carrier mobility, is the gate oxide capacitance, is the
MOSFET channel width, and is the MOSFET channel length.
The delay time of an inverter (using results in [Burns64]) is then approximately
, ( A-3 )
where is the load capacitance.
For , nMOSFETs operate in weak inversion (or subthreshold regime) with an
exponential relationship as follows:
( A-4 )
v
GS
V
t
>

i
DS
v
GS
V
t
( )

=
V
t

1
2
-- -C
ox
W
L
----- =
C
ox
W
L

D
C
L
V
DD
V
DD
V
t
( )

----------------------------------- =
C
L
v
GS
V
t
<
i
DS
v
GS

i
DS
I
D0
W
L
-----e
v
GS
V
t

n
t
-------------------
1 e
v
DS

t
--------

,


_
=
Appendix A - MOSFET Equations 152
Here, is the thermal voltage and the MOSFET specic current (the value of the
drain current for unit transistor ( ) with gate to source voltage biased at
threshold voltage), and is the subthreshold slope factor. The equations for thermal
voltage, the specic current, and subthreshold slope factor are:
( A-5 )
( A-6 )
( A-7 )
Here, is the Boltzman constant, is temperature in degree Kelvin, and is the
depletion layer capacitance.

t
I
D0
W L 1 =
n

t
kT
q
------ =
I
D0
C
ox

t
2
=
n 1
C
D
C
ox
--------- + =
k T C
D
153
Appendix B
Natural MOSFET Characteristics
Low- natural threshold voltage transistors can be fabricated as an option in a dual poly
gate CMOS process. A process designed for 1V operation may be further simplied by
eliminating the steps required for hot-carrier reduction i.e., LDD (Lightly doped Drain)
implant and formation.
Natural threshold voltage MOSFETs were fabricated in a m CMOS process by
removing the threshold adjust masks and implants. Figure B.1 and Figure B.2 show the
measured I
D
and G
m
versus gate voltage for a nMOSFET and a
pMOSFET biased at respectively. For m channel
length, the threshold voltages are measured to be and for nMOSFET
and pMOSFET respectively and subthreshold slopes are about .
Measured I
DS
-V
DS
characteristics for natural threshold nMOSFET and pMOSFET are
illustrated in Figure B.3 and Figure B.4 respectively. In this technology, for an
nMOSFET is and for a pMOSFET is .
V
t
0.5
20 m /0.5 m
20 m /0.5 m v
DS
0.1 V = 0.5
202 mV 197 mV
80 mV/decade

1.27 1.32
Appendix B - Natural MOSFET Characteristics 154
0 1 2 3 4
0
0.5
1
1.5
2
2.5
3
3.5
4
x 10
4
Figure B.1: Measured I
D
(A) and G
m
(A/V) versus V
GS
(V) for
natural nMOSFET
I
D
G
m
V
GS
(V)
I
D

(
A
)
,

G
m
(
A
/
V
) V
DS
=0.1 V
4 3 2 1 0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
x 10
4
Figure B.2: Measured |I
D
(A)| and G
m
(A/V) versus V
GS
(V)
for natural pMOSFET
V
GS
(V)
I
D
G
m
|
I
D

(
A
)
|
,

G
m
(
A
/
V
)
V
DS
=-0.1 V
Appendix B - Natural MOSFET Characteristics 155
Figure B.3: Measured nMOSFET I
DS
-V
DS
characteristics. I
DS
~ (V
GS
-V
t
)
1.27
V
DS
(V)
I
D
S

(
A
m
p
)
W/L =
0 0.2 0.4 0.6 0.8 1
0.5
0
0.5
1
1.5
2
2.5
3
x 10
3
W/L = 10 um/0.5 um
0 0.2 0.4 0.6 0.8 1
2
0
2
4
6
8
10
12
x 10
4
Figure B.4: Measured pMOSFET I
DS
-V
DS
characteristics. I
DS
~ (V
GS
-V
t
)
1.32
|V
DS
| (V)
I
D
S

(
A
m
p
)
W/L = 10 um/0.5 um
156
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