EEE 2213 Digital Electronics I

Contact hours/week: 3 Credits:3

Analysis and Synthesis of Digital Logic Circuits:

1. Number system, codes, and conversion.
2. Boolean algebra
3. De Morgan’s law
4. Logic gates and truth tables
5. Combinational logic design, minimization techniques
6. Implementation of basic static logic gates in CMOS and BiCMOS.
7. Arithmetic and data handling logic circuits
8. Decoders and encoders
9. Multiplexers and combinational circuit design.
Programmable Logic Devices:
1. Logic arrays
2. Field Programmable Logic Arrays and Programmable Read Only Memory.
Sequential Circuits:
1. Different types of latches
2. Flip-flops and their design using ASM approach
3. Timing analysis
4. Timing analysis and power optimization of sequential circuits.
Modular sequential logic circuit design:
1. Shift registers
2. Counters and their applications.

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CT-4
➢ Johnson mod-6 ring counter
➢ Controlled buffer
➢ Ring counter using JK flipflop
➢ Controlled Shift Register
➢ Moris - 265,267,268
➢ 4-bit bidirection shift register
➢ Analysis of clocked sequential circuit( Mano 6.4)
➢ Moris- 6.5 ( State Reduction and Assignment)
➢ Mealy, Moore machine
➢ Magnitude comparator
➢ Parity Generator/ Checker
➢ Odd parity Error function

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 SET A (Mainly)
Analysis and Synthesis of Digital Logic Circuits:
1. Number system, codes, and conversion.
i. Convert the following numbers: (i) (225.15)8 = (? )2 (ii) (93.375)10 = (? )𝐵𝐶𝐷
ii. If 𝐴 = 1 0 0 0 0 1 1 and 𝐵 = 1 0 1 0 1 1 1, then find 𝐴 − 𝐵 using 1’s & 2’s
complement methods. [20]
iii. Design a 2’s complement Adder-subtractor that can subtract 1010 from 1000.
[19]
2. Boolean algebra
i. Express the Boolean function, 𝐸 = 𝐴 + 𝐵̅𝐶
(i) In a sum of minterms, & in a product of maxterm form.
3. De Morgan’s law
i. Prove De Morgan’s theorems. [20]
ii. State De-Morgan’s theorems. How do you prove the theorems in the
laboratory? [19]
4. Logic gates and truth tables
i. What are universal gates? Why are they called so? [20,19]
ii. Design Ex-NOR gate by using universal gates only. [19]
iii. Prove that “A positive logic AND gate is the same physical gate as a negative
logic OR gate”. [20]
5. Combinational logic design, minimization techniques
i. Find the SOP and POS forms of the following expression:
ii. Draw the logic circuit diagram for the following Boolean function using NAND
gates only.
𝑓(𝐴, 𝐵, 𝐶, 𝐷) = 𝐴𝐵̅𝐶̅ 𝐷
̅ + 𝐴𝐵𝐶𝐷̅ + 𝐴̅𝐶̅ 𝐷
̅ + 𝐴𝐵̅
iii. Design a combinational circuit that accepts a three-bit number and generate
an output binary number equal to the square of the input. [20]
6. Implementation of basic static logic gates in CMOS and BiCMOS.
i. Draw and explain NAND and NOR gates using CMOS logic. [20]
7. Arithmetic and data handling logic circuits
8. Adder & Subtractor
i. Show how a full adder can be converted to full subtractor with the addition of
an inverter circuit. [20]
ii.
9. Decoders and encoders [set B]
i. Construct 4 × 16 decoder by using two 3 × 8 decoders. [20]
10.Multiplexers and combinational circuit design.
i. Write some applications of MUX(Multiplexer). [19]
ii. Show how to extend a 3 × 8 MUX in a 5 × 32 MUX. [19]

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 iii. Using Multiplexer, realize the Boolean function 𝐹(𝐴, 𝐵, 𝐶, 𝐷) =
∑(0,1,3,4,8,9,15). [20]
iv.
v. Write down the advantages and disadvantages of digital techniques over
analog techniques.

SET B (Mainly)
Sequential Circuits:
1. Different types of latches
i. Distinguish between latch and a flip-flop. [20]
2. Flip-flops and their design using ASM approach
i. What is master slave flip-flop? [17]
ii. Explain the working of JK flip-flop. [20]
iii. Draw the logic circuit diagram, characteristics table of a J-K flip-flop. Derive its
characteristics equation. [19]
iv. What is race around condition? How is it overcome? [20]
v. What do you mean by flip-flop excitation table? [19]
vi. Draw the excitation table of J-K, T and D flip-flops. [20,19]
vii. How can S-R flip-flop can be converted to J-K flip-flop? [19]
viii. Convert a D flip-flop to JK flip-flop. [17]
3. Timing analysis
4. Timing analysis and power optimization of sequential circuits.

Modular sequential logic circuit design:

1. Shift registers
2. Counters and their applications.
i. What is meant by sequential logic? [17]
ii. Design a modulo-8 ripple down counter. [17]
iii. How can a ring counter be converted to a Johnson counter? [17]
iv. Write the difference between asynchronous and synchronous counter. [19]
v. Draw two cascaded asynchronous counter circuit that act as a divide by 32
counter. [19]
vi. Design a counter which counts according to the following state diagram. [20]

ii. Design the following counter using T flip-flops. [19]

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 iii. Briefly explain how an up-counter can be modified to use as a down-counter.
[19]
iv. Design a 2-bit up-down counter to count upward when the control line c=1 ,
and count downward when the control line c=0.
v.
vi. What do you understand by the modulus (MOD) of a digital counter? [19]
vii. Draw the Johnson mod-6 ring counter and determine the output state using
timing diagram. [19]
viii. Draw a MOD-16 counter and show its output-timing diagram. [19]
ix. Design a pulse train generator which can generate the following waveform.
[20]

x. Design a pulse train generator which can generate the following waveform.
[19]

xi.
Programmable Logic Devices:
1. Logic arrays
i. Implement the following functions with PLA (programmable logic Array).
𝐹1 (𝐴, 𝐵, 𝐶) = ∑𝑚(3,5,6,7) and 𝐹2 (𝐴, 𝐵, 𝐶) = ∑𝑚(0,2,4,7)
2. Field Programmable Logic Arrays and Programmable Read Only Memory.
i. Distinguish between EPROM and EEPROM. [19]
ii. Distinguish between memory size and memory capacity. [19]

What is Parity?
Parity Bit is a simple form of error detecting code, where the additional bit is added along
with the data bits.

There are two types of Parity:

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1) Odd Parity
2) Even Parity

Odd Parity:
In Odd parity, the parity bit is set in such a way that the total number of 1s in the code,
including the parity bit is Odd.

Even Parity:
In Even parity, the parity bit is set in such a way that the total number of 1s in the code,
including the parity bit is Even.

For error detection, the parity bit is appended with data bits, and the code is sent to the
receiver.
At the receiver, the parity checker circuit checks the parity of the received code and detects
the error.

Limitations of Parity Bit:

The Parity bit can detect only odd numbers of errors. If there are even a number of errors in
the received code, it will remain undetected.
Moreover, the Parity bit can just detect the error in the code (if the number of errors in the
received code is odd) but it can't correct the error.

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