CYBER SECURITY

Unit 4:MEMORY
ONE SHOT
Today’s Target
 MOST IMPORTANT TOPICS
By PRAGYA RAJVANSHI
 AKTU PYQs
B.Tech, M.Tech( C.S.E.)
 Result Oriented

PDF notes are available in the App (Link in Description)

 Cache Mapping- The line number of cache to which a particular block can
Cache mapping is a technique by which the contents of map is given by
Cache line number
main memory are brought into the cache memory. = ( Main Memory Block Address ) Modulo (Number of lines
Cache Mapping Techniques- in Cache)
Direct Mapping Consider cache memory is divided into ‘n’ number of
Fully Associative Mapping lines.Then, block ‘j’ of main memory can map to line
K-way Set Associative Mapping number (j mod n) only of the cache.
. There is no need of any replacement algorithm. This is
because a main memory block can map only to a particular
line of the cache. Thus, the new incoming block will always
replace the existing block (if any) in that particular line.

Direct Mapping-
In direct mapping, A particular block of main memory can
map only to a particular line of the cache.

. . .Within that set, block ‘j’ can map to any cache line that is
Division of Physical Address- K-way Set Associative Mapping-
freely available at that moment.
Cache lines are grouped into sets where each set contains k
If all the cache lines are occupied, then one of the existing
number of lines.
blocks will have to be replaced
A particular block of main memory can map to only one
particular set of the cache.
However, within that set, the memory block can map any
2. Fully Associative Mapping- cache line that is freely available.
A block of main memory can map to any line of the cache The set of the cache to which a particular block of the main
A replacement algorithm is required.
that is freely available at that moment. memory can map is given by-
Replacement algorithm suggests the block to be replaced Cache set number
This makes fully associative mapping more flexible than
if all the cache lines are occupied. = ( Main Memory Block Address ) Modulo (Number of sets in
direct mapping. Cache)
Thus, replacement algorithm like FCFS Algorithm, LRU
All the lines of cache are freely available. k = 2 suggests that each set contains two cache lines.
Thus, any block of main memory can map to any line of Since cache contains 6 lines, so number of sets in the cache =
the cache. Had all the cache lines been occupied, then one 6 / 2 = 3 sets.Block ‘j’ of main memory can map to set
of the existing blocks will have to be replaced. number (j mod 3) only of the cache
Q-1 What are Proxy Servers? Write advantages and disadvantages.
RAM CHIP
 MEMORY ADDRESS MAP
ROM CHIP
 2D and 2.5D Memory organization One of the output lines selects the row by the address 2.5D Memory organization – cell which is addressed by the memory address register
contained in the MAR and the word which is represented In 2.5D Organization the scenario is the same but we have (MAR).
The internal structure of Memory either RAM or ROM is
by that row gets selected and is either read or written two different decoders one is a column decoder and another With the help of the select line, we can select the desired
made up of memory cells that contain a memory bit. A
through the data lines is a row decoder. Column decoder is used to select the data and we can perform read and write operations on it.
group of 8 bits makes a byte. The memory is in the form of
column and a row decoder is used to select the row. The
a multidimensional array of rows and columns. In which,
address from the MAR goes as the decoders’ input. Decoders
each cell stores a bit and a complete row contains a word. A
will select the respective cell through the bit outline, then
memory simply can be divided into this below form.
the data from that location will be read or through the bit,
2n = Nwhere n is the no. of address lines and N is the total
inline data will be written at that memory location.
memory in bytes. There will be 2n words.
Read and Write Operations –
2D Memory organization –
If the select line is in Reading mode then the Word/bit
In 2D organization, memory is divided in the form of rows
which is represented by the MAR will be available to the
and columns(Matrix). Each row contains a word, now in this
data lines and will get read.
memory organization, there is a decoder. A decoder is a
If the select line is in write mode then the data from the
combinational circuit that contains n input lines and
memory data register (MDR) will be sent to the respective
2n output lines.

Associative memory or Content Addressable Memory Associative memory is access simultaneously and in ARGUMRENT REGISTER(A)  the argument word in parallel
(CAM).
parallel on the basis of data content rather by specific It contains the words to be searched It consists of m words with n bits per words
 An associative memory can be considered as a memory
address location It has n bits (one for each bit of word)
unit whose stored data can be identified for access by
Because of its organization the associative memory is KEY REGISTER(K)
the content of the data itself rather than by an address
uniquely entitled to do parallel search by data association The key register (K) provides a mask for choosing a
or memory location.
An associative memory is more expensive than RAM particular field or key in the argument word.
because each cell have storage capacity as well as logic If the key register contains a binary value of all 1's, then the
 When a write operation is performed on associative
circuit for matching its content with an external arguments entire argument is compared with each memory word.
memory, no address or memory location is given to the
An associative memory consists of a memory array and Otherwise, only those bits in the argument that have 1's in
word. The memory itself is capable of finding an empty
logic for 'm' words with 'n' bits per word. their corresponding position of the key register are
unused location to store the word.
The functional registers like the argument register A and compared. Thus, the key provides a mask for identifying a
 , when the word is to be read from an associative
key register K each have n bits, one for each bit of a word. piece of information which specifies how the reference to
memory, the content of the word, or part of the word, is
The match register M consists of m bits, one for each memory is made.
specified. The words which match the specified. The
memory word Associative memory array and logic
words which match the specified content are located by
the memory and are marked for reading It contain the word that are to be compared with the
 Match logic(M)  AUXILLARY MEMORY MAGNETIC TAPE Memory interleaving(memory module)
 It has m bits, one bits corresponding to each word in the memory An Auxiliary memory is known as the  Magnetic tape is a storage medium that allows data A single memory module cause sequential access,
array. lowest-cost, highest-capacity and slowest- archiving, collection, and backup for different kinds of data. only one memory access is possible a time so
 After the matching process, the bits corresponding to matching words access storage in a computer system. It is The magnetic tape is constructed using a plastic strip coated throughput is low
in match register are set to 1 .Searching done in parallel manner where programs and data are kept for long- with a magnetic recording medium. Memory interleaving is the technique to increase the
 Reading is accomplished by the sequential access in memory for these term storage or when not in immediate use.  The bits are recorded as magnetic spots on the tape along throughput Here system is divided into a number of
words whose match bits set one 1.Magnetic Disks several tracks. Usually, seven or nine bits are recorded independent modules which answer read and write
A magnetic disk is a type of memory simultaneously to form a character together with a parity request independently in parallel.
constructed using a circular plate of metal or bit. Interleaved memory is designed to compensate for
plastic coated with magnetized materials. FLASH MEMORY the relatively slow speed of dynamic random-access
Usually, both sides of the disks are used to  Flash memory is a long-life and non-volatile storage chip that memory (DRAM) or core memory by spreading memory
carry out read/write operations. However, is widely used in embedded systems. It can keep stored data addresses evenly across memory banks. In this way,
several disks may be stacked on one spindle and information even when the power is off. It can be contiguous memory reads and writes use each memory
with read/write head available on each electrically erased and reprogrammed. bank, resulting in higher memory throughput due to
surface.  Flash memory was developed from EEPROM (electronically reduced waiting for memory banks to become ready for
erasable programmable read-only memory the operation

two types of memory interleaving ADVANTAGES ADVANTAGES

Higher order interleaving  easy memory extension by addition of one or more Faster access to a block of data and higher utilization of
 Consecutive address are stored within in a same module memory module the memory system as whole
 It uses higher order bits(MSB) as the module address and  Provides better reliability since failed module affect only Disadvantage
lower order bits as word within each module a localized area of the address space. A failure of single module cause whole system fail
DISADAVANTAGES
 When a consecutive location are accessed only one
module is involved other sir idle
 Scheme will cause conflicts in case of pipelined vector
processing due to sequentially of instruction
 This sequence is useful in single user system
 Lower order interleaving
 Consecutive address stored in a consecutive module
 It uses low order bit as a module address and higher order
bit as word address within each module
 PAGING one or more page frames to the process and maps  The mapping from virtual to physical address is done
 Paging is a memory management scheme that eliminates the process’s logical pages to the physical page frames by the Memory Management Unit (MMU) which is a
the need for a contiguous allocation of physical memory. The mapping between logical pages and physical page hardware device and this mapping is known as the paging
The process of retrieving processes in the form of pages frames is maintained by the page table, which is used by technique.
from the secondary storage into the main memory is the memory management unit to translate logical  The Physical Address Space is conceptually divided into a
known as paging. The basic purpose of paging is to addresses into physical addresses. The page table maps number of fixed-size blocks, called frames.
separate each procedure into pages. Additionally, frames each logical page number to a physical page frame number.  The Logical Address Space is also split into fixed-size
will be used to split the main memory. This scheme blocks, called pages.
permits the physical address space of a process to be non  Page Size = Frame Size
– contiguous  Let us consider an example:
 In paging, the physical memory is divided into fixed-size  Physical Address = 12 bits, then Physical Address Space =
blocks called page frames, which are the same size as the 4 K words
pages used by the process. The process’s logical address  Logical Address = 13 bits, then Logical Address Space = 8
space is also divided into fixed-size blocks called pages, K words
which are the same size as the page frames. When a  Page size = frame size = 1 K words (assumption)
process requests memory, the operating system allocates

VIRTUAL MEMORY
 Virtual memory is a memory
management technique used by
operating systems to expand the
available memory of a computer
beyond its physical RAM. It allows a
computer to compensate for shortages
of physical memory by temporarily
transferring data from RAM to disk
storage. When the data is needed
again, it is transferred back from the
disk to RAM. This process is transparent
to the user and allows programs to run
as if they have more memory than is
actually available.
 Demand Paging The required page will be brought from logical address
 . The process of loading the page into memory on demand space to physical address space. The page replacement
(whenever a page fault occurs) is known as demand algorithms are used for the decision-making of replacing
paging. The process includes the following steps are as the page in physical address space.
follows: The page table will be updated accordingly.
 If the CPU tries to refer to a page that is currently not The signal will be sent to the CPU to continue the
available in the main memory, it generates an interrupt program execution and it will place the process back into
indicating a memory access fault. the ready state.
 The OS puts the interrupted process in a blocking state.
For the execution to proceed the OS must bring the
required page into the memory.
 The OS will search for the required page in the logical
address space.