Microelectronics and Semiconductor Devices

Module III

Microcontrollers
Microcontroller Overview
8051 Architecture
 Microcontrollers
MIcrocontrollers
Microprocessor, memory and I/O devices are build on a single chip is came to known
as microcontroller.
It is a general purpose device like microprocessor, but it meant to read data, perform
limited calculations and control its environment based on that data.
It is used to control the operation of a machine using a fixed program stored in ROM.
It uses limited set of instructions to move data and code.
It’s pins are programmable.
It can handle data in bit, byte and word size.
Block Diagram of Microcontroller
Comparing Microprocessors and Microcontrollers

Microprocessors Microcontrollers

They have many operational They have one or two operational

codes for movement of data codes for movement of data
from external memory to CPU. from external memory to CPU.
They have only one or two bit They have many bit handling
handling instructions. instructions.
They are concerned with rapid They are concerned with rapid
movement of code & data from movement of code & data within
external addresses to chip. the chip.
Microprocessor needs many Microcontroller can function as a
additional parts to be function as computer with no external digital
a computer. parts.
Eg: Z80 Eg: 8051
Comparison of
Z80 & 8051
8051 is a 40 pin DIP NMOS or CMOS microcontroller.
The 8051 architecture consists of these specific features

The 8051 architecture

The 8051 architecture

It consists of 8 bit and 16 bit registers and 8 bit memory locations.

These registers and memory locations are operated using software
instructions.
More number of registers makes 8051 model a complicated one.
Registers having specific function are occupied in an individual block with
symbolic name, Eg : A, TH0, PC
Registers which are generally indistinguishable from each other are grouped in
larger block, Eg: ROM, RAM
Each register except Program counter, has an internal 1 byte address
Software instructions specify a register by its address or by its symbolic name
or both.
The 8051 architecture

8051
Block diagram
The 8051 architecture

8051 Oscillator & Clock

The oscillator circuit is considered as the heart of 8051 that generates the clock pulses by
which all internal operations are synchronized.
Pins XTAL1 and XTAL2 are provided for connecting a resonant network to form an oscillator.
The circuit consists of a quartz crystal and capacitors

The frequency of the crystal is the basic internal

frequency of microcontroller.
8051 can run at specified maximum frequency (16 MHz)
and minimum frequency (1 MHz)
Ceramic resonators are low cost alternative to crytal
oscillator. But has low frequency stability and accuracy.
The 8051 architecture

8051 Oscillator & Clock

Pulse:
The smallest time interval in the microcontroller is called Pulse.
The corresponding clock frequency is f.

State:
It is the basic time interval for discrete operations such as
fetching opcode, decoding opcode, executing opcode...

Machine Cycle:
The smallest time interval to accomplish any simple instruction

A machine cycle consists of 6 states. Each state consists of 2 oscillator pulses.

Time taken to execute an instruction is given by

C - No. of machine cycles

There are 2 ALE (Address Latch Enable) pulses per machine cycle and it is used to access
external memory.
In one machine cycle, 2 bytes of a single instruction is fetched and executed.
The 8051 architecture

8051
Programming Model
The 8051 architecture

Program Counter (PC)

PC is a 16 bit register.
It contains the address of the next instruction to be executed
The program ROM may be on the chip at addresses 0000h to 0FFFh, external to the chip for
the addresses that exceeds 0FFFh or totally external for all addresses from 0000h to FFFFh.
PC is automatically incremented after every instruction byte is fetched.
PC is the only register that does not have an internal address.

Data Pointer ( DPTR)

DPTR is made up of two 8 bit registers: DPH & DPL
Used for furnish memory addresses for internal and external code access and
external data access.
DPTR does not have a single internal address; DPH & DPL are each assigned an
address
The 8051 architecture

A & B CPU Registers

8051 contains 34 general purpose or working registers.
Two of these registers ‘A’ and ‘B’, hold the results of many instructions, particularly math and
logical operations.
Other 32 registers are arranged as part of internal RAM in four banks

A Register B Register

It is the most versatile of the two Used with ‘A’ register for
registers. multiplication and division
It is used for many operations operations
such as arithmetic, logic and bit For other instructions, it can be
manipulations. used as an 8 bit general purpose
Used for all data transfer register (ie, storing data)
between the 8051 and any
external memory.
The 8051 architecture

Flags
These are 1 bit registers provide to store the results of certain program instructions.
Other instructions can test the condition of flag and make decision based on the flag states.
flags are grouped inside the Program Status Word (PSW) & Power Control registers (PCON).
There are 4 Math flags and 3 General purpose user flags

Math Flags User Flags

Auxiliary Carry (AC) F0

Overflow (OV) GF0
Carry (C) GF1
Parity (P)

Among the 3 user flags, GF0 & GF1 are stored in PCON and all the others are in PSW.
General purpose user flags are used by the programmer to record some event in the program.
All the flags can be set or reset by the user but math flags are also affected by math operations
The 8051 architecture

Program Status Word (PSW)

It contains math flags, User program flag F0 and register select bit (for identifying which
register bank is currently using) .
The 8051 architecture

Internal Memory
It consists of internal ROM & internal RAM
They are also referred as Program Memory and Data Memory

Program Memory Data Memory

Used for the permanent saving of the Used for the temporary storing of
code that is to be executed in intermediate results and variables
Program Counter (PC)

For a CPU to process information, it should be stored in either RAM or ROM.

So these memories are referred to as primary memory
The 8051 architecture

Internal RAM
There are 128 bytes of RAM in 8051.
The 128 bytes are divided into 3 different groups

32 bytes from address 00h to 1Fh, that make up 32 working registers.

The 4 register banks are numbered 0 to 3 and are made of 8 registers
named R0 to R7.
Bits RS0 and RS1 in PSW determine which reg. bank is currently using
Reg. banks that are not using can be used as general purpose RAM.
bank 0 is selected on Reset

16 bytes of bit addressable area from address 20h to 2Fh forms a total of
128 addressable bits.
An addressable bit can be specified by its bit address of 00h to 7Fh or by
its byte address from 20h to 2Fh

Eg: Bit address = 4Fh ; Byte address = 29h

80 bytes of general purpose RAM address from 30h to 7Fh, which

are above bit addressable area and can be addressed as bytes
The 8051 architecture

The Stack & Stack Pointer

The Stack refers to an area of internal RAM to store and retrieve data quickly.
8 bit Stack Pointer (SP) register used to hold the address of the stack top.
The address held in SP register is the location in internal RAM.
when data to be placed on stack, the SP increments before storing, so that the stack grows up as
data is stored.

When data retrieve from stack, SP decrements.

The SP is set to 07h when 8051 is reset and can be
changed to any internal RAM address by the programmer.
The stack is limited in height to the size of internal RAM.
The stack has teh potential to overwrite valuable data in
register banks, bit addressable RAM and general purpose
areas if the programmer is not careful to limit its growth.
The 8051 architecture

Special function Registers (SFR)

The SFR registers are located within the internal memory address range 80h to
FFh.
But not all addresses from 80h to FFh are used for SFR.
Some SFR’s are bit addressable, as is the for the bit area of RAM.
CPU and internal peripheral modules use SFR for controlling the desired
operation of the device.
The 8051 architecture

Internal ROM

Internal ROM consists of internal program code which occupies code address space 0000h to
0FFFh.
The Program Counter (PC) is used to address program code bytes from address 0000h to FFFFh.
Code bytes can also be fetched from an external memory.
If the program address is greater than 0FFFh, then 8051 automatically fetch code bytes from external
program memory.
The PC does not care where the code is; the circuit designer decides whether the code is found
totally in Internal ROM, External ROM or in a combination of internal or external ROM.