EXPERIMENT NO: DATE:

REALIZATION OF COMBINATIONAL LOGIC CIRCUITS -

4 BIT ARRAY MULTIPILER USING STRUCTURAL MODELLlING

AIM:
To write a Verilog code to implement a 4 bit array using structural modelling and verify
the results in MODELSIM software

ALGORITHM:
1. Start the program.
2. Declare modules for basic logic gates such as AND gates (for partial product generation)
and full adders (for summation). Generate partial products using AND gates.
3. Use full adders to perform the required bitwise additions in a row-wise manner,
handling carry propagation.
4. Connect the partial products and full adders structurally to form the 4-bit array
multiplier circuit.
5. End the module. Compile and simulate the design in ModelSim to verify
its functionality.
PROGRAM:
module half_adder(
input a, b,
output sum, carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule

module full_adder(
input a, b, cin,
output sum, carry
);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (b & cin) | (a & cin);
endmodule

module multiplier_4bit(
input [3:0] A, B,
output [7:0] P
);
wire [3:0] pp0, pp1, pp2, pp3;
wire [3:0] s1, s2, s3;
wire c1, c2, c3;

assign pp0 = A & {4{B[0]}};

assign pp1 = A & {4{B[1]}};
assign pp2 = A & {4{B[2]}};
assign pp3 = A & {4{B[3]}};
assign P[0] = pp0[0];

half_adder ha1(pp0[1], pp1[0], s1[0], c1);

full_adder fa1(pp0[2], pp1[1], pp2[0], s1[1], c2);
full_adder fa2(pp0[3], pp1[2], pp2[1], s1[2], c3);
half_adder ha2(pp1[3], pp2[2], s1[3], c3);

half_adder ha3(s1[1], c1, s2[0], c2);

full_adder fa3(s1[2], pp2[3], pp3[0], s2[1], c3);
full_adder fa4(s1[3], pp3[1], c2, s2[2], c3);
half_adder ha4(pp3[2], c3, s2[3], c3);

half_adder ha5(s2[1], c2, s3[0], c3);

full_adder fa5(s2[2], pp3[3], c3, s3[1], c3);
full_adder fa6(s2[3], c3, 1'b0, s3[2], c3);
full_adder fa7(c3, 1'b0, 1'b0, s3[3], c3);

assign P[1] = s1[0];

assign P[2] = s2[0];
assign P[3] = s3[0];
 assign P[4] = s3[1];
assign P[5] = s3[2];
assign P[6] = s3[3];
assign P[7] = c3;

endmodule

SIMULATION OUTPUT:

RESULT:
The Verilog code for 4 bit array multiplier were implemented in Structural Modelling
and the functionality of the design was verified in the MODELSIM software.
EXPERIMENT NO: DATE:

REALIZATION OF COMBINATIONAL LOGIC CIRCUITS -

4 BIT ARRAY ADDER MULTIPLIER USING STRUCTURAL

MODELLING

AIM:
To write a Verilog code to implement a 4 bit array adder using structural modelling
and verify the result in MODELSIM software.

ALGORITHM:
1. Start the program.
2. Declare modules for basic logic gates such as half adder (for first-bit addition) and full
adders (for summation with carry propagation).
3. Perform bitwise addition using a half adder for the least significant bit and full
adders for the remaining bits.
4. Connect the adders structurally to form the 4-bit array adder circuit.
5. End the module.
6. Compile and simulate the design in ModelSim to verify its functionality.
PROGRAM:
module half_adder(
input a, b,
output sum, carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule

module full_adder(
input a, b, cin,
output sum, carry
);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (b & cin) | (a & cin);
endmodule

module array_adder_4bit(
input [3:0] A, B,
input cin,
output [3:0] S,
output cout
);
wire c1, c2, c3;

half_adder ha1(A[0], B[0], S[0], c1);

full_adder fa1(A[1], B[1], c1, S[1], c2);
full_adder fa2(A[2], B[2], c2, S[2], c3);
full_adder fa3(A[3], B[3], c3, S[3], cout);

endmodule
SIMULATION OUTPUT:

RESULT:
Thus, the Verilog code for 4 bit array adder using structural were implemented in
Structural Modelling and the functionality of the design was verified in the MODELSIM
software
EXPERIMENT NO: DATE:
REALIZATION OF COMBINATIONAL LOGIC CIRCUITS -

IMPLEMENTATION OF DECODERS

AIM:
To write a Verilog code to implement the following:

i) 3:8 Decoder using Behavioural Modelling.

ii) 4:16 Decoder using Behavioural Modelling.

ALGORITHM:
1. Start the Program.
2. Declare the module with input and output ports.
3. Declare the module with input and output ports.
4. Use a case statement to design the 3x8 decoder using Behavioral Modelling.
5. End the module.
6. Declare another module for the 4x16 decoder with input, output ports, and wires.
7. Instantiate two 3x8 decoders and construct the 4x16 decoder using Structural
Modelling.
8. End the module.
9. Compile and simulate the design in ModelSim and verify the
functionality of the design.
PROGRAM:
i) 3:8 DECODER:
module decoder_3to8(i, e, y);
input [2:0] i;
input e;
output reg [7:0] y;
always @(i or e)
begin
if (e == 1)
begin
case (i)
3'b000: y = 8'b00000001;
3'b001: y = 8'b00000010;
3'b010: y = 8'b00000100;
3'b011: y = 8'b00001000;
3'b100: y = 8'b00010000;
3'b101: y = 8'b00100000;
3'b110: y = 8'b01000000;
3'b111: y = 8'b10000000;
endcase
end
else
begin
y = 8'b00000000;
end
end
endmodule

ii) 4:16 DECODER:

module decoder_4to16(i, y);
input [3:0] i;
output [15:0] y;
decoder_3to8 d1(i[2:0], ~i[3], y[7:0]);
decoder_3to8 d2(i[2:0], i[3], y[15:8]);
endmodule
SIMULATION OUTPUT:

RESULT:
The Verilog code for implementation of 4:16 decoder using two 3:8 Decoders using
structural modelling and the functionality of the design was verified in the MODELSIM
software