SIDDARTHA INSTITUTE OF SCIENCE AND TECHNOLOGY: PUTTUR

(AUTONOMOUS)
IV B.Tech. – I Sem. L T P
3 3

(20EC0442) VLSI DESIGN

Professional Elective Course (PEC) –V

COURSE OBJECTIVES
The objectives of this course:

1. Learn the operation of MOS Transistor and also fabrication of Various MOS transistors.
2. Come across to understand basic electrical properties of MOSFET.
3. Understand Basic MOS Transistors Inverter operation.
4. Apply CMOS technology-specific layout rules in the placement and routing of transistors
andinterconnect and to verify the functionality, timing, power and parasitic effects.
5. Learn MOS Transistor fabrication metrics.
6. Learn semiconductor integrated circuit architectures and CMOS testing.

COURSE OUTCOMES (COs)

On successful completion of this course, the student will be able to

1. Remember the basic concepts of MOS transistor and history of Integrated Circuit.
2. Understand Fabrication steps of MOS transistor and their electrical properties.
3. Understand stick diagram and layout design rules.
4. Learn MOS transistor designing at gate level and physical level.
5. Understand various PLD structures and testing principles of Integrated circuits.
6. Apply layout design rules to design logic gates and digital subsystems.

UNIT – I
Introduction: The Future of Microelectronics, Metal Oxide semiconductor VLSI Technology, Basic
MOS transistors, Basic steps of IC fabrication: nMOS, CMOS & BiCMOS.
Basic Electrical Properties of MOS And BICMOS Circuits: Drain to Source Current Ids Versus
Voltage Vds Relationships, Threshold Voltage Vt, Transconductance gm and Output conductance gds,
Figure of merit ω0, various pull ups loads, Bi-CMOS Inverters.

UNIT – II
VLSI Circuit Design Processes: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and
Layout, 2μm CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and
CMOS Inverters and Gates.

UNIT – III
Gate Level Design: Logic gates and other complex gates, Switch logic, Alternate gate circuits.
Physical Design: Floor-Planning, Placement, routing, Power delay estimation, Clock and Power routing.

UNIT– IV
Subsystem Design: Shifters, Adders, ALUs, Multipliers, Parity generators, Comparators, zero/one
detectors, Counters, High Density Memory Elements.
UNIT – V
Semiconductor Integrated Circuit Design: Gate-arrays: PLDs, FPGAs, CPLDs and
Standard Cells. CMOS Testing: Need for testing, Testing during the VLSI Life cycle,
test principles, design strategiesfor test.

TEXT BOOKS
1. Kamran Eshraghian, Eshraghian Douglas and A. Pucknell, Essentials
of VLSI circuits andSystems, PHI, 2013 Edition.
2. Lal Kishore and V.S.V. Prabhakar, VLSI Design, IK Publishers.
3. Weste and Eshraghian, Principles of CMOS VLSI Design, Pearson Education, 1999.

REFERENCES
1. Wayne Wolf, Modern VLSI Design, Pearson Education, 3rd Edition, 1997.
2. John P. Uyemura, Chip Design for Submicron VLSI: CMOS layout and
Simulation, ThomsonLearning.
 UNIT-I

Introduction to VLSI Technology

Introduction:

The invention of the transistor by William B. Shockley, Walter H. Brattain and John
Bardeen of Bell Telephone Laboratories drastically changed the electronics industry and
paved the way for the development of the Integrated Circuit (IC) technology. The first IC
was designed by Jack Kilby at Texas Instruments at the beginning of 1960 and since that
time there have already been four generations of ICs .Viz SSI (small scale integration), MSI
(medium scale integration), LSI (large scale integration), and VLSI (very large scale
integration). Now we are ready to see the emergence of the fifth generation, ULSI (ultra large
scale integration) which is characterized by complexities in excess of 3 million devices on a
single IC chip. Further miniaturization is still to come and more revolutionary advances in the
application of this technology must inevitably occur.

Over the past several years, Silicon CMOS technology has become the dominant
fabrication process for relatively high performance and cost effective VLSI circuits. The
revolutionary nature of this development is understood by the rapid growth in which the
number of transistors integrated in circuits on a single chip.

METAL-OXIDE-SEMICONDUCTOR (MOS) AND RELATED VLSI

TECHNOLOGY:

The MOS technology is considered as one of the very important and promising
technologies in the VLSI design process. The circuit designs are realized based on PMOS,
NMOS, CMOS and BiCMOS devices.
The PMOS devices are based on the p-channel MOS transistors. Specifically, the
PMOS channel is part of a n-type substrate lying between two heavily doped p+ wells
beneath the source and drain electrodes. Generally speaking, a PMOS transistor is only
constructed in consort with an NMOS transistor.
The NMOS technology and design processes provide an excellent background for
other technologies. In particular, some familiarity with NMOS allows a relatively easy
transition to CMOS technology and design.
The techniques employed in NMOS technology for logic design are similar to GaAs
technology.. Therefore, understanding the basics of NMOS design will help in the layout of
GaAs circuits

In addition to VLSI technology, the VLSI design processes also provides a new
degree of freedom for designers which helps for the significant developments. With the rapid
advances in technology the size of the ICs is shrinking and the integration density is
increasing.
The minimum line width of commercial products over the years is shown in the graph below.

The graph shows a significant decrease in the size of the chip in recent years which implicitly
indicates the advancements in the VLSI technology.

BASIC MOS TRANSISTORS:

The MOS Transistor means, Metal-Oxide-Semiconductor Field Effect Transistor
which is the most basic element in the design of a large scale integrated circuits(IC).
These transistors are formed as a ``sandwich'' consisting of a semiconductor layer, usually a
slice, or wafer, from a single crystal of silicon; a layer of silicon dioxide (the oxide) and a
layer of metal. These layers are patterned in a manner which permits transistors to be formed
in the semiconductor material (the ``substrate''); a diagram showing a MOSFET is shown
below in Figure .
 Silicon dioxide is a very good insulator, so a very thin layer, typically only a few
hundred molecules thick, is used. In fact , the transistors which are used do not use metal for
their gate regions, but instead use polycrystalline silicon (poly). Polysilicon gate FET's have
replaced virtually all of the older devices using metal gates in large scale integrated circuits.
(Both metal and polysilicon FET's are sometimes referred to as IGFET's (insulated gate field
effect transistors), since the silicon dioxide under the gate is an insulator.
MOS Transistors are classified as n-MOS, p-MOS and c-MOS Transistors based on
the fabrication .
NMOS devices are formed in a p-type substrate of moderate doping level. The source
and drain regions are formed by diffusing n- type impurities through suitable masks into
these areas to give the desired n-impurity concentration and give rise to depletion regions
which extend mainly in the more lightly doped p-region . Thus, source and drain are isolated
from one another by two diodes. Connections to the source and drain are made by a deposited
metal layer. In order to make a useful device, there must be the capability for establishing and
controlling a current between source and drain, and .this is commonly achieved in one of two
ways, giving rise to the enhancement mode and depletion mode transistors.

Enhancement Mode Transistors:

In an enhancement mode device a polysilicon gate is deposited on a layer of
insulation over the region between source and drain. In the diagram below channel is not
established and the device is in a non-conducting condition, i.e VD = Vs = Vgs = 0. If this
gate is connected to a suitable positive voltage with respect to the source, then the electric
field established between the gate and the substrate gives rise to a charge inversion region in
the substrate under the gate insulation and a conducting path or channel is formed between
source and drain.

ENHANCEMENT MODE TRANSISTOR ACTION :

 To understand the enhancement mechanism, let us consider the enhancement mode
device. In order to establish the channel, a minimum voltage level called threshold voltage
(Vt) must be established between gate and source. Fig. (a) Shows the existing situation where
a channel is established but no current flowing between source and drain (Vds = 0 ).

Let us now consider the conditions when current flows in the channel by applying a
voltage Vds between drain and source. The IR drop = Vds along the channel. This develops a
voltage between gate and channel varying with distance along the channel with the voltage
being a maximum of Vgs at the source end. Since the effective gate voltage is Vg= Vgs - Vt,
(no current flows when Vgs < Vt) there will be voltage available to invert the channel at the
drain end so long as Vgs - Vt ~ Vds· The limiting condition comes when Vds= Vgs - Vt. For
all voltages Vds < Vgs - Vt, the device is in the non-saturated region of operation which is
the condition shown in Fig. (b) below.
 Let us now consider the situation when Vds is increased to a level greater than Vgs -
Vt. In this case, an IR drop equal to Vgs – Vt occurs over less than the whole length of the
channel such that, near the drain, there is insufficient electric field available to give rise to an
inversion layer to create the channel. The .channel is, therefore, 'pinched off as shown in Fig.
(c). Diffusion current completes the path from source to drain in this case, causing the
channel to exhibit a high resistance and behave as a constant current source. This region,
known as saturation, is .characterized by almost constant current for increase of Vds above
Vds = Vgs - Vt. In all cases, the channel will cease to exist and no current will flow when
Vgs < Vt. Typically, for enhancement mode devices, Vt = 1 volt for VDD = 5 V or, in general
terms, Vt = 0.2 VDD.
DEPLETION MODE TSANSISTOR ACTION
N-MOS Depletion mode mosfets are built with P-type silicon substrates, and P-
channel versions are built on N-type substrates. In both cases they include a thin gate oxide
formed between the source and drain regions. A conductive channel is deliberately formed
below the gate oxide layer and between the source and drain by using ion-implantation. By
implanting the correct ion polarity in the channel region during fabrication determines the
polarity of the threshold voltage (i.e. -Vt for an N channel transistor, or +Vt for an P-channel
transistor). The actual concentration of ions in the substrate-to-channel region is used to
adjust the threshold voltage (Vt) to the desired value. Depletion-mode devices are a little
more difficult to manufacture and their characteristics harder to control than enhancement
types, which do not require ion implantation. In depletion mode devices the channel is
established, due to the implant, even when Vgs = 0, and to cause the channel to cease a
negative voltage Vtd must be applied between gate and source.
Vtd is typically < - 0.8 VDD, depending on the implant and substrate bias, but, threshold
voltage differences apart, the action is similar to that of the enhancement mode transistor.

CMOS FABRICATION :
CMOS fabrication is performed based on various methods , including the p-well, the
n-well, the twin-tub, and the silicon-on-insulator processes .Among these methods the p-well
process is widely used in practice and the n-well process is also popular, particularly as it is
an easy retrofit to existing NMOS lines.
(i) The p-well Process:
The p-well structure consists of an n-type substrate in which p-devices may be formed by
suitable masking and diffusion and, in order to accommodate n-type devices, a deep p-well is
diffused into the n-type substrate as shown in the Fig.below.

This diffusion should be carried out with special care since the p-well doping
concentration and depth will affect the threshold voltages as well as the breakdown voltages
of the n-transistors. To achieve low threshold voltages (0.6 to 1.0 V) either deep-well
diffusion or high-well resistivity is required. However, deep wells require larger spacing
between the n- and p-type transistors and wires due to lateral diffusion and therefore a larger
chip area. The p-wells Act as substrates for the n-devices within the parent n-substrate, and,
the two areas are electrically isolated.
Except this in all other respects- like masking, patterning, and diffusion-the process is similar
to NMOS fabrication.

P-well fabrication process(Figs 1,2,3 & 4)

The diagram below shows the CMOS p-well inverter showing VDD and Vss substrate
connections

The n-well Process : Though the p-well process is widely used in C-MOS fabrication the n-
well fabrication is also very popular because of the lower substrate bias effects on transistor
threshold voltage and also lower parasitic capacitances associated with source and drain
regions.
The typical n-well fabrication steps are shown in the diagram below.

Fig. n-well fabrication steps

The first mask defines the n-well regions. This is followed by a low dose phosphorus
implant driven in by a high temperature diffusion step to form the n-wells. The well depth is
optimized to ensure against-substrate top+ diffusion breakdown without compromising then-
well to n+ mask separation. The next steps are to define the devices and diffusion paths, grow
field oxide, deposit and pattern the poly silicon, carry out the diffusions, make contact cuts,
and finally metalize as before. Lt will be seen that an n+ mask and its complement may be
used to define the n- and p-diffusion regions respectively. These same masks also include the
VDD and Vss contacts (respectively). It should be noted that, alternatively, we could have
used a p+ mask and its complement since the n + and p + masks are generally
complementary.
The diagram below shows the Cross-sectional view of n-well CMOS Inverter.
 Due to the differences in charge carrier mobilities, the n-well process creates non-
optimum p-channel characteristics. However, in many CMOS designs (such as domino-logic
and dynamic logic structures), this is relatively unimportant since they contain a
preponderance of n-channel devices. Thus then-channel transistors are mainly those used to
form1ogic elements, providing speed and high density of elements.
However, a factor of the n-well process is that the performance of the already poorly
performing p-transistor is even further degraded. Modern process lines have come to grips
with these problems, and good device performance may be achieved for both p-well and n-
well fabrication.
BICMOS Technology:

A Bi-CMOS circuit of both bipolar junction transistors and MOS transistors on a

single substrate. The driving capability of MOS transistors is less because of limited current
sourcing and sinking capabilities of the transistors. To drive large capacitive loads Bi-CMOS
technology is used. As this technology combines Bipolar and CMOS transistors in a single
integrated circuit, it has the advantages of both bipolar and CMOS transistors. Bi-CMOS is
able to achieve VLSI circuits with speed-power-density performance previously not possible
with either technology individually. The diagram given below shows the cross section of the
Bi-CMOS process which uses an NPN transistor

Fig.Cross section of Bi-CMOS process

The lay-out view of Bic-MOS transistor is shown in the figure below. The fabrication
of Bi-CMOS is similar to CMOS but with certain additional process steps and additional
masks are considered. They are (i) the p+ base region; (ii) n+ collector area; and (iii) the
buried sub collector (BCCD).

IDS-VDS characteristics of MOS Transistor:

The graph below shows the ID Vs VDS characteristics of an n- MOS transistor for
several values of VGS .It is clear that there are two conduction states when the device is ON.
The saturated state and the non-saturated state. The saturated curve is the flat portion and
defines the saturation region. For Vgs < VDS + Vth, the NMOS device is conducting and ID
is independent of VDS. For Vgs > VDS + Vth, the transistor is in the non-saturation region
and the curve is a half parabola. When the transistor is OFF (Vgs < Vth), then ID is zero for
any VDS value.
 The boundary of the saturation/non-saturation bias states is a point seen for each
curve in the graph as the intersection of the straight line of the saturated region with the
quadratic curve of the non-saturated region. This intersection point occurs at the channel
pinch off voltage called VDSAT. The diamond symbol marks the pinch-off voltage VDSAT for
each value of VGS. VDSAT is defined as the minimum drain-source voltage that is required to
keep the transistor in saturation for a given VGS .In the non-saturated state, the drain current
initially increases almost linearly from the origin before bending in a parabolic response.
Thus the name ohmic or linear for the non- saturated region.
The drain current in saturation is virtually independent of VDS and the transistor acts
as a current
Source. This is because there is no carrier inversion at the drain region of the channel.
Carriers are pulled into the high electric field of the drain/substrate pn junction and ejected
out of the drain terminal.

Drain-to-Source Current IDS versus Voltage VDS Relationships:

The working of a MOS transistor is based on the principle that the use of a voltage on
the gate induce a charge in the channel between source and drain, which may then be caused
to move from source to drain under the influence of an electric field created by voltage Vds
applied between drain and source. Since the charge induced is dependent on the gate to
source voltage Vgs then Ids is dependent on both Vgs and Vds.
Let us consider the diagram below in which electrons will flow source to drain .So,
the drain current is given by

Charge induced in channel (Qc)

 Ids =-Isd = _____________________
Electron transit time(τ)
Length of the channel
Where the transit time is given by τsd = ------------------------------
Velocity (v)

But velocity v= µeds

Where µ =electron or hole mobility and Eds = Electric field

Also , Eds = Vds/L

So, v = µ.Vds/L
And τds = L2 / µ.Vds

The typical values of µ at room temperature are given below.

The Non-saturated Region:

Let us consider the Id vs Vd relationships in the non-saturated region .The charge
induced in the channel due to due to the voltage difference between the gate and the channel,
Vgs (assuming substrate connected to source). The voltage along the channel varies linearly
with distance X from the source due to the IR drop in the channel .In the non-saturated state
the average value is Vds/2. Also the effective gate voltage Vg = Vgs – Vt where Vt, is the
threshold voltage needed to invert the charge under the gate and establish the channel.

Hence the induced charge is Qc = Eg εins εow. L

Where
 Eg = average electric field gate to channel
Εins = relative permittivity of insulation between gate and channel
Εo = permittivity of free space.
So, we can write that

Here D is the thickness of the oxide layer. Thus

So, by combining the above two equations ,we get

Or the above equation can be written as

In the non-saturated or resistive region where Vds < Vgs – Vt and

Generally ,a constant β is defined as

So that ,the expression for drain –source current will become

The gate /channel capacitance is

Hence we can write another alternative form forthe drain current as

Some time it is also convenient to use gate –capacitance per unit area ,Cg
So,the drain current is
This is the relation between drain current and drain-source voltage in non-saturated region.

The Saturated Region

Saturation begins when Vds = Vgs - V, since at this point the IR drop in the channel
equals the effective gate to channel voltage at the drain and we may assume that the current
remains fairly constant as Vds increases further. Thus

Or we can also write that

Or it can also be written as

Or

The expressions derived above for Ids hold for both enhancement and depletion mode
devices. Here the threshold voltage for the NMOS depletion mode device (denoted as V td) is
negative.
MOS Transistor Threshold Voltage Vt :
The gate structure of a MOS transistor consists, of charges stored in the dielectric
layers and in the surface to surface interfaces as well as in the substrate itself. Switching an
enhancement mode MOS transistor from the off to the on state consists in applying sufficient
gate voltage to neutralize these charges and enable the underlying silicon to undergo an
inversion due to the electric field from the gate. Switching a depletion mode NMOS transistor
from the on to the off state consists in applying enough voltage to the gate to add to the stored
charge and invert the 'n' implant region to 'p'.
The threshold voltage Vt may be expressed as:

Where QD = the charge per unit area in the depletion layer below the oxide
Qss = charge density at Si: sio2 interface
 Co =Capacitance per unit area.
Φns = work function difference between gate and Si
Φfn = Fermi level potential between inverted surface and bulk Si
For polynomial gate and silicon substrate, the value of Φns is negative but negligible and the
magnitude and sign of Vt are thus determined by balancing the other terms in the equation.
To evaluate the Vt the other terms are determined as below.

Body Effect :
Generally while studying the MOS transistors it is treated as a three terminal device.
But ,the body of the transistor is also an implicit terminal which helps to understand the
characteristICs of the transistor. Considering the body of the MOS transistor as a terminal is
known as the body effect. The potential difference between the source and the body (Vsb)
affects the threshold voltage of the transistor. In many situations, this Body Effect is
relatively insignificant, so we can (unless otherwise stated) ignore the Body Effect. But it is
not always insignificant, in some cases it can have a tremendous impact on MOSFET circuit
performance.

Body effect - NMOS device

Increasing Vsb causes the channel to be depleted of charge carriers and thus the
threshold voltage is raised. Change in Vt is given by δvt = γ.(Vsb)1/2 where γ is a constant
which depends on substrate doping so that the more lightly doped the substrate, the smaller
will be the body effect
The threshold voltage can be written as
Where Vt(0) is the threshold voltage for Vsd = 0
For n-MOS depletion mode transistors ,the body voltage values at different VDD voltages are
given below.
VSB = 0 V ; Vsd = -0.7VDD (= - 3.5 V for VDD =+5V )
VSB = 5 V ; Vsd = -0.6VDD (= - 3.0 V for VDD =+5V )

The NMOS INVERTER :

An inverter circuit is a very important circuit for producing a complete range of logic
circuits. This is needed for restoring logic levels, for Nand and Nor gates, and for sequential
and memory circuits of various forms .
A simple inverter circuit can be constructed using a transistor with source connected
to ground and a load resistor of connected from the drain to the positive supply rail VDD· The
output is taken from the drain and the input applied between gate and ground .

But, during the fabrication resistors are not conveniently produced on the silicon
substrate and even small values of resistors occupy excessively large areas .Hence some
other form of load resistance is used. A more convenient way to solve this problem is to use a
depletion mode transistor as the load, as shown in Fig. Below.

The salient features of the n-MOS inverter are

 For the depletion mode transistor, the gate is connected to the source so it is always
on .

 In this configuration the depletion mode device is called the pull-up (P.U) and the
enhancement mode device the pull-down (P.D) transistor.
  With no current drawn from the output, the currents Ids for both transistors must be
equal.
NMOS Inverter transfer characteristic.
The transfer characteristic is drawn by taking Vds on x-axis and Ids on Y-axis for
both enhancement and depletion mode transistors. So,to obtain the inverter transfer
characteristic for Vgs = 0 depletion mode characteristic curve is superimposed on the family
of curves for the enhancement mode device and from the graph it can be seen that ,
maximum voltage across the enhancement mode device corresponds to minimum voltage
across the depletion mode transistor.

From the graph it is clear that as Vin(=Vgs p.d. Transistor) exceeds the Pulldown
threshold voltage current begins to flow. The output voltage Vout thus decreases and the
subsequent increases in Vin will cause the Pull down transistor to come out of saturation
and become resistive.
CMOS Inverter :
The inverter is the very important part of all digital designs. Once its operation and
properties are clearly understood, Complex structures like NAND gates, adders, multipliers,
and microprocessors can also be easily done. The electrical behavior of these complex
circuits can be almost completely derived by extrapolating the results obtained for inverters.
As shown in the diagram below the CMOS transistor is designed using p-MOS and n-MOS
transistors.
 In the inverter circuit ,if the input is high .the lower n-MOS device closes to discharge
the capacitive load .Similarly ,if the input is low,the top p-MOS device is turned on to
charge the capacitive load .At no time both the devices are on ,which prevents the DC current
flowing from positive power supply to ground. Qualitatively this circuit acts like the
switching circuit, since the p-channel transistor has exactly the opposite characteristICs of the
n-channel transistor. In the transition region both transistors are saturated and the circuit
operates with a large voltage gain.
The C-MOS transfer characteristic is shown in the below graph.
Considering the static conditions first, it may be Seen that in region 1 for which Vi,. =
logic 0, we have the p-transistor fully turned on while the n-transistor is fully turned off. Thus
no current flows through the inverter and the output is directly connected to VDD through the
p-transistor.
 Hence the output voltage is logic 1 . In region 5 , Vin = logic 1 and the n-transistor
is fully on while the p-transistor is fully off. So, no current flows and a logic 0 appears at the
output.
In region 2 the input voltage has increased to a level which just exceeds the threshold
voltage of the n-transistor. The n-transistor conducts and has a large voltage between source
and drain; so it is in saturation. The p-transistor is also conducting but with only a small
voltage across it, it operates in the unsaturated resistive region. A small current now flows
through the inverter from VDD to VSS. If we wish to analyze the behavior in this region, we
equate the p-device resistive region current with the n-device saturation current and thus
obtain the voltage and current relationships.

Region 4 is similar to region 2 but with the roles of the p- and n-transistors
reversed.However, the current magnitudes in regions 2 and 4 are small and most of the
energy consumed in switching from one state to the other is due to the larger current which
flows in region 3.
Region 3 is the region in which the inverter exhibits gain and in which both transistors
are in saturation.
 The currents in each device must be the same ,since the transistors are in series.
So,we can write that

Since both transistors are in saturation, they act as current sources so that the
equivalent circuit in this region is two current sources in series between VDD and Vss with the
output voltage coming from their common point. The region is inherently unstable in
consequence and the changeover from one logic level to the other is rapid.
Determination of Pull-up to Pull –Down Ratio (Zp.u}Zp.d.)For an NMOS Inverter
driven by another NMOS Inverter :

Let us consider the arrangement shown in Fig.(a). In which an inverter is driven from
the output of another similar inverter. Consider the depletion mode transistor for which Vgs =
0 under all conditions, and also assume that in order to cascade inverters without
degradation the condition

Fig.(a).Inverter driven by another inverter.

For equal margins around the inverter threshold, we set Vinv = 0.5VDD · At this point both
transistors are in saturation and we can write that
Where Wp.d , Lp.d , Wp.u. And Lp.u are the widths and lengths of the pull-down and pull-up
transistors respectively.
So,we can write that

The typical, values for Vt ,Vinv and Vtd are

Substituting these values in the above equation ,we get

Here

So,we get

This is the ratio for pull-up to pull down ratio for an inverter directly driven by another
inverter.
Pull -Up to Pull-Down ratio for an NMOS Inverter driven through one or more Pass
Transistors

Let us consider an arrangement in which the input to inverter 2 comes from the
output of inverter 1 but passes through one or more NMOS transistors as shown in Fig.
Below (These transistors are called pass transistors).

The connection of pass transistors in series will degrade the logic 1 level / into
inverter 2 so that the output will not be a proper logic 0 level. The critical condition is , when
point A is at 0 volts and B is thus at VDD. But the voltage into inverter 2at point C is now
reduced from VDD by the threshold voltage of the series pass transistor. With all pass
transistor gates connected to VDD there is a loss of Vtp, however many are connected in
series, since no static current flows through them and there can be no voltage drop in the
channels. Therefore, the input voltage to inverter 2 is
Vin2 = VDD- Vtp
Where Vtp = threshold voltage for a pass transistor.

Let us consider the inverter 1 shown in Fig.(a) with input = VDD· If the input is at
VDD , then the pull-down transistor T2 is conducting but with a low voltage across it;
therefore, it is in its resistive region represented by R1 in Fig.(a) below. Meanwhile, the pull
up transistor T1 is in saturation and is represented as a current source.
For the pull down transistor

Since Vds is small, Vds/2 can be neglected in the above expression.

So,

Now, for depletion mode pull-up transistor in saturation with Vgs = 0

The product I1R1 = Vout1

So,

Let us now consider the inverter 2 Fig.b .when input = VDD- Vtp.

Whence,
If inverter 2 is to have the same output voltage under these conditions then Vout1 = Vout2. That
is

I1R1=I2R2 , therefore

Considering the typical values

Therefore

From the above theory it is clear that, for an n-MOS transistor

(i). An inverter driven directly from the output of another should have a Zp.u/ Zpd. Ratio
Of ≥ 4/1.
(ii).An inverter driven through one or more pass transistors should have a Zp.u./Zp.d ratio of
≥8/1

ALTERMTIVE FORMS OF PULL –UP

Generally the inverter circuit will have a depletion mode pull-up transistor as its load.
But there are also other configurations .Let us consider four such arrangements.
(i).Load resistance RL : This arrangement consists of a load resistor as apull-up as shown in
the diagram below.But it is not widely used because of the large space requirements of
resistors produced in a silicon substrate.
2. NMOS depletion mode transistor pull-up : This arrangement consists of a depletion
mode transistor as pull-up. The arrangement and the transfer characteristic are shown
below.In this type of arrangement we observe
(a) Dissipation is high , since rail to rail current flows when Vin = logical 1.
(b) Switching of output from 1 to 0 begins when Vin exceeds Vt, of pull-down device.

NMOS depletion mode transistor pull-up and transfer characteristic

(c) When switching the output from 1 to 0, the pull-up device is non-saturated initially and
this presents lower resistance through which to charge capacitive loads .
3. NMOS enhancement mode pull-up :This arrangement consists of a n-MOS enhancement
mode transistor as pull-up. The arrangement and the transfer characteristic are shown below.
 NMOS enhancement mode pull-up and transfer characteristic
The important features of this arrangement are
(a) Dissipation is high since current flows when Vin =logical 1 (VGG is returned to VDD) .

(b) Vout can never reach VDD (logical I) if VGG = VDD as is normally the case.
(c) VGG may be derived from a switching source, for example, one phase of a clock, so that
Dissipation can be greatly reduced.

(d) If VGG is higher than VDD then an extra supply rail is required.
4. Complementary transistor pull-up (CMOS) : This arrangement consists of a C-MOS
arrangement as pull-up. The arrangement and the transfer characteristic are shown below

The salient features of this arrangement are

(a) No current flows either for logical 0 or for logical 1 inputs.
(b) Full logical 1 and 0 levels are presented at the output.
(c) For devices of similar dimensions the p-channel is slower than the n-channel device.

THE BiCMOS INVERTER :

A BiCMOS inverter, consists of a PMOS and NMOS transistor ( M2 and M1), two
NPN bipolar junction transistors,( Q2 and Q1), and two impedances which act as loads( Z2
and Z1) as shown in the circuit below.

When input, Vin, is high (VDD), the NMOS transistor ( M1), turns on, causing Q1 to
conduct,while M2 and Q2 are off, as shown in figure (b) . Hence , a low (GND) voltage is
translated to the output Vout. On the other hand, when the input is low, the M2 and Q2 turns
on, while m1and Q1 turns off, resulting to a high output level at the output as shown in
Fig.(b).
In steady-state operation, Q1 and Q2 never turns on or off simultaneously, resulting to
a lower power consumption. This leads to a push-pull bipolar output stage. Transistors
m1and M2, on the other hand, works as a phase-splitter, which results to a higher input
impedance.

The impedances Z2 and Z1 are used to bias the base-emitter junction of the bipolar
transistor and to ensure that base charge is removed when the transistors turn off. For
example when the input voltage makes a high-to-low transition, M1 turns off first. To turn off
Q1, the base charge must be removed, which can be achieved by Z1.With this effect,
transition time reduces. However, there exists a short time when both Q1 and Q2 are on,
making a direct path from the supply (VDD) to the ground. This results to a current spike that
is large and has a detrimental effect on both the noise and power consumption, which makes
the turning off of the bipolar transistor fast .
Comparison of BiCMOS and C-MOS technologies

The BiCMOS gates perform in the same manner as the CMOS inverter in terms of
power consumption, because both gates display almost no static power consumption.
When comparing BiCMOS and CMOS in driving small capacitive loads, their performance
are comparable, however, making BiCMOS consume more power than CMOS. On the other
hand, driving larger capacitive loads makes BiCMOS in the advantage of consuming less
power than CMOS, because the construction of CMOS inverter chains are needed to drive
large capacitance loads, which is not needed in BiCMOS.
The BiCMOS inverter exhibits a substantial speed advantage over CMOS inverters,
especially when driving large capacitive loads. This is due to the bipolar transistor‘s
capability of effectively multiplying its current.
For very low capacitive loads, the CMOS gate is faster than its BiCMOS counterpart
due to small values of Cint. This makes BiCMOS ineffective when it comes to the
implementation of internal gates for logic structures such as alus, where associated load
capacitances are small.
BiCMOS devices have speed degradation in the low supply voltage region and also BiCMOS
is having greater manufacturing complexity than CMOS.
 UNIT II

VLSI CIRCUIT DESIGN PROCESSES

In this chapter we will be studying how to get the schematic into stick diagrams or layouts.

MOS circuits are formed on four basic layers:

N-diffusion
P-diffusion
Poly silicon
Metal

These layers are isolated by one another by thick or thin silicon dioxide insulating
layers. Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel.

Stick diagrams:

Stick diagrams may be used to convey layer information through the use of a color code.

For example:

N-diffusion -green
poly -- red
Blue -- metal
yellow --implant
Black --contact area
Encodings for NMOS process:

Figure shows the way of representing different layers in stick diagram notation and
mask layout using nmos style.

Figure1 shows when a n-transistor is formed: a transistor is formed when a green line
(n+ diffusion) crosses a red line (poly) completely. Figure also shows how a depletion
mode transistor is represented in the stick format.
Encodings for MOS process:
figure 2 shows when a n-transistor is formed: a transistor is formed when a green line
(n+ diffusion) crosses a red line (poly) completely.

Figure 2 also shows when a p-transistor is formed: a transistor is formed when a yellow
line (p+ diffusion) crosses a red line (poly) completely.

Encoding for BJT and MOSFETs:

There are several layers in an nMOS chip:
Paths of metal (usually aluminum) a further thick layer of silicon dioxide with contact cuts
through the silicon dioxide where connections are required.

The three layers carrying paths can be considered as independent conductors that only
interact where polysilicon crosses diffusion to form a transistor. These tracks can be drawn
as stick diagrams with

Diffusion in green

Polysilicon in red

Metal in blue

Using black to indicate contacts between layers and yellow to mark regions of implant in the
channels of depletion mode transistors. With CMOS there are two types of diffusion: n-type
is drawn in green and p-type in brown. These are on the same layers in the chip and must not
meet. In fact, the method of fabrication required that they be kept relatively far apart. Modern
CMOS processes usually support more than one layer of metal. Two are common and three
or more are often available. Actually, these conventions for colors are not universal; in
particular, industrial (rather than academic) systems tend to use red for diffusion and green
for polysilicon. Moreover, a shortage of colored pens normally means that
both types of diffusion in CMOS are colored green and the polarity indicated by drawing a
circle round p-type transistors or simply inferred From the context. Colorings for
multiple layers of metal are even less standard.

There are three ways that an nMOS inverter might bedrawn:

Figure 4 shows schematic, stick diagram and corresponding layout of nMOS depletion
Load inverter
Figure 7 shows the stick diagram nMOS implementation of the function f=[(xy)+z]
 Figure 8: stick diagram of CMOS NAND and NOR

Figure 8 shows the stick diagram CMOS NOR and NAND, where we can see that the p
diffusion line never touched the n diffusion directly, it is always joined using a blue color
metal line.
NMOS and CMOS Design style:
In the NMOS style of representing the sticks for the circuit, we use only NMOS transistor, in
CMOS we need to differentiate n and p transistor, that is usually by the color or in
monochrome diagrams we will have a demarcation line. Above the demarcation line are the
p transistors and below the demarcation are the n transistors.
Following stick shows CMOS circuit example in monochrome where we utilize the
demarcation line.

Figure 9 shows the stick diagram of dynamic shift register using CMOS style. Here the output of
the TG is connected as the input to the inverter and the same chain continues depending the
number of bits.
Design Rules:

Design rules include width rules and spacing rules. Mead and Conway developed a set of
simplified scalable λ -based design rules, which are valid for a range of fabrication
technologies. In these rules, the minimum feature size of a technology is characterized as 2 λ
. All width and spacing rules are specified in terms of the parameter λ . Suppose we have
design rules that call for a minimum width of 2 λ , and a minimum spacing of 3 λ . If

we select a 2 um technology (i.e., λ = 1 um), the above rules are translated to a

minimum width of 2 um and a minimum spacing of 3 um. On the other hand, if a 1 um
technology (i.e., λ = 0.5 um) is selected, then the same width and spacing rules are now
specified as 1 um and 1.5 um, respectively.
Figure 10 shows the design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n and
p diffusion lines is having a minimum width of 2λand a minimum spacing of 3λ. Similarly
we are showing for other layers
.

Figure shows the design rule for the transistor, and it also shows that the poly should
extend for a minimum of 2λbeyond the diffusion boundaries.(gate over hang distance)
What is Via?

It is used to connect higher level metals from metal1 connection. The cross section and
layout view given figure 13 explain via in a betterway.

Figure shows the design rules for contact cuts and Vias. The design rule for contact
is minimum 2λx2λand same is applicable for a Via.
Buried contact: The contact cut is made down each layer to be joined and it is shown
in figure 14.

Butting contact: The layers are butted together in such a way the two contact cuts become
contiguous. We can better under the buttingcontact from figure
CMOS LAMBDA BASED DESIGN RULES:

Till now we have studied the design rules wrt only NMOS , what are the rules to be followed
if we have the both p and n transistor on the same chip will be made clear with the diagram.
Figure 16 shows the rules to be followed in CMOS well processes to accommodate both n
and p transistors.

Orbit 2µm CMOS process:

In this process all the spacing between each layersand dimensions will be in terms
micrometer. The 2µm here represents the feature size. All the design rules what ever we have
seen will not have lambda instead it will have the actual dimension in micrometer.

In one way lambda based design rules are better compared micrometer based design
rules, that is lambda based rules are feature size independent.
Figure 17 shows the design rule for BiCMOS process using orbit 2um process.

The following is the example stick and layout for 2way selector with enable (2:1 MUX).
 UNIT-3
GATE LEVEL DESIGN
Introduction

The module (integrated circuit) is implemented in terms of logic gates and interconnections between these
gates. Designer should know the gate-level diagram of the design. In general, gate-level modeling is used
for implementing lowest level modules in a design like, full-adder, multiplexers, etc.

Boolean algebra is used to represent logical(combinational logic) functions of digital circuits. A

combinational logic expression is a mathematical formula which is to be interpreted using the laws of
Boolean algebra. Now the goal of logic design or optimization is to find a network of logic gates that
together compute the combinational logic function we want.

For example, given the expression a+b , we can compute its truth value for any given values of a and b ,
and also we can evaluate relationships such as a+b = c. but logic design is difficult for many reasons:

• We may not have a logic gate for every possible function, or even for every function of n
inputs.
• Not all gate networks that compute a given function are alike-networks may differ greatly
in their area and speed.
• Thus combinational logic expressions are the specification,
Logic gate networks are the implementation,
Area, delay, and power are the costs.
• A logic gate is an idealized or physical device implementing a Boolean function, that is,
it performs a logical operation on one or more logic inputs and produces a single logic
output.
• Logic gates are primarily implemented using diodes or transistors acting as electronic
switches, but can also be constructed using electromagnetic relays (relay logic), fluidic
logic, pneumatic logic, optics, molecules, or even mechanical elements.
• With amplification, logic gates can be cascaded in the same way that Boolean functions
can be composed, allowing the construction of a physical model of all of Boolean logic.
• simplest form of electronic logic is diode logic. This allows AND and OR gates to be
built, but not inverters, and so is an incomplete form of logic. Further, without some kind
of amplification it is not possible to have such basic logic operations cascaded as required
for more complex logic functions.
• To build a functionally complete logic system, relays, valves (vacuum tubes), or
transistors can be used.
• The simplest family of logic gates using bipolar transistors is called resistor-transistor
logic (RTL). Unlike diode logic gates, RTL gates can be cascaded indefinitely to produce
more complex logic functions. These gates were used in early integrated circuits. For
1
higher speed, the resistors used in RTL were replaced by diodes, leading to diode-transistor logic
(DTL).
• Transistor-transistor logic (TTL) then supplanted DTL with the observation that one
transistor could do the job of two diodes even more quickly, using only half the space.
• In virtually every type of contemporary chip implementation of digital systems, the
bipolar transistors have been replaced by complementary field-effect transistors
(MOSFETs) to reduce size and power consumption still further, thereby resulting in
complementary metal–oxide–semiconductor (CMOS) logic that can be described with
Boolean logic.

CMOS logic gates and other complex gates

General logic circuit Any Boolean logic function (F) has two possible values, either logic 0 or
logic 1. For some of the input combinations, F = 1 and for all other input combinations, F = 0. So
in general, any Boolean logic function can be realized using a structure as shown in figure.

• The switch S1 is closed and switch S2 is open for input combinations that produces F = 1.
• The switch S1 is open and switch S2 is closed for input combinations that produces F = 0.

Thus the output (F) is either connected to VDD or the ground, where the logic 0 is represented by
the ground and the logic 1 is represented by VDD. So the requirement of digital logic design is to
implement the pull-up switch(S1) and the pull-down switch(S2).

CMOS static logic

A generalized CMOS logic circuit consists of two transistor nets nMOS and pMOS. The pMOS
transistor net is connected between the power supply and the logic gate output called as pull-up
network , Whereas the nMOS transistor net is connected between the output and ground called as
pull-down network. Depending on the applied input logic, the PUN connects the output node to
VDD and PDN connects the output node to the ground.

2
The transistor network is related to the Boolean function with a straight forward design
procedure:

• Design the pull down network (PDN) by realizing AND(product) terms using series-
connected nMOSFETs. OR (sum) terms using parallel-connected nMOSFETS.

• Design the pull-up network by realizing,

AND(product) terms using parallel-connected nMOSFETs. OR

(sum) terms using series-connected nMOSFETS.
• Add an inverter to the output to complement the function. Some functions are inherently
negated, such as NAND, NOR gates do not need an inverter at the output terminal.

CMOS inverter
A CMOS inverter is the simplest logic circuit that uses one nMOS and one pMOS transistor. The
nMOS is used in PDN and the pMOS is used in the PUN as shown in figure.

3
Working operation

1) When the input Vin is logic HIGH, then the nMOS transistor is ON and the pMOS
transistor is OFF. Thus the output Y is pulled down to ground (logic 0) since it is
connected to ground but not to source VDD.

2) When the input Vin is logic LOW, then nMOS transistor is OFF and the pMOS
transistor is ON, Thus the output Y is pulled up to VDD(logic 1) since it is connected
to source via pMOS but not to ground.

CMOS NAND gate

The two input NAND function is expressed by Y=A.B

Step 1 Take complement of Y

Y= A.B = A.B

Step 2 Design the PDN

In this case, there is only one AND term, so there will be two nMOSFETs in series as shown in
figure.
Step 3 Design the PUN. In PUN there will be two pMOSFETs in parallel , as shown in figure

4
Finally join the PUN and PDN as shown in figure which realizes two –input NAND gate. Note
that we have realized y, rather tat Y because the inversion is automatically provided by the
nature of the CMOS circuit operation,

Working operation

1) Whenever at least one of the inputs is LOW, the corresponding pMOS transistor will
conduct while the corresponding nMOS transistor will turn OFF. Subsequently, the
output voltage will be HIGH.
2) Conversely, if both inputs are simultaneously HIGH, then both pMOS transistors will
turn OFF, and the output voltage will be pulled LOW by the two conducting nMOS
transistors.
CMOS NOR gate
The two input NOR function is expressed by Y=A+B

Step 1 Take complement of Y

Y= A+B = A+B

Step 2 Design the PDN

In this case, there is only one OR term, so there will be two nMOSFETs connected in parallel, as
shown in figure.
Step 3 Design the PUN

In PUN there will be two pMOSFETs in series , as shown in figure

5
Finally join the PUN and PDN as shown in figure which realizes two –input NAND gate. Note
that we have realized y, rather tat Y because the inversion is automatically provided by the
nature of the cMOS circuit operation,
Working operation

1) Whenever at least one of the inputs is LOW, the corresponding pMOS transistor will
conduct while the corresponding nMOS transistor will turn OFF. Subsequently, the
output voltage will be HIGH.
2) Conversely, if both inputs are simultaneously HIGH, then both pMOS transistors will
turn OFF, and the output voltage will be pulled LOW by the two conducting nMOS
transistors.

6
Complex gates in CMOS logic

A complex logic gate is one that implements a function that can provide the basic NOT, AND
and OR operation but integrates them into a single circuit. CMOS is ideally suited for creating
gates that have logic equations by exhibiting the following,

1)AND-OR-INVERT -AOI form

2)OR-AND-INVERT -OAI form

An AOI logic equation is equivalent to a complemented SOP from, while an AOI equation is
equivalent to a complemented POS structure. In CMOS, output always produces NOT operation
acting on input variable.

1) AOI Logic Function (OR) Design of XOR gate using CMOS logic.

AND-OR-INVERT logic function(AOI) implements operation in the order AND,OR,NOT. For

example ,
let us consider the function Y = AB+CD i.e., Y = NOT((A AND B)OR (C AND D)) The

AOI logic gate implementation for Y

CMOS implementation for Y

Step 1: Draw A.B (AND) function first by connecting 2 nMOS transistors in series.

7
Step 2: Draw C.D implementation, by using 2 nMOS transistors in series.

Step 3: Y = A.B+C.D , In this function A.B and C.D are added, for addition , we have to draw
parallel connection. So, A.B series connected in parallel with C.D as shown in figure.

Step 4: Draw pMOS connection,

I. In nMOS A,B connected in series. So, in pMOS side, A.B should be connected in
parallel.
II. In nMOS C,D connected in series. So, in pMOS side, C.D should be connected in
parallel.
III. A.B and C.D networks are connected in parallel in nMOS side. So, in pMOS side,
A.B and C.D networks should be connected in series.
IV. In pMOS multiplication should be drawn in parallel, then addition should be
drawn in series as shown in figure.

8
Step 5: Take output at the point in between nMOS and pMOS networks.

1) OAI Logic Function (OR) Design of XNOR gate using CMOS logic.

OR-AND-INVERT logic function(AOI) implements operation in the order OR,AND,NOT. For

example ,
let us consider the function Y = (A+B).(C+D) i.e., Y = NOT((A OR B)AND (C OR D)) The

OAI logic gate implementation for Y

9
CMOS implementation for Y

SWITCH LOGIC
1) Switch logic is mainly based on pass transistor or transmission gate.

2) It is fast for small arrays and takes no static current from the supply, V DD. Hence
power dissipation of such arrays is small since current only flows on switching.

3) Switch (pass transistor) logic is analogous to logic arrays based on relay contacts,
where in path through each switch is isolated from the logic levels activating the
switch.

PASS TRANSISTOR

10
 1) This logic uses transistors as switches to carry logic signals from node to node instead
of connectiong output nodes directly to VDD or ground(GND)
2) If a single transistor is a switch between two nodes, then voltage degradation.equal to
vt (threshold voltage) for high or low level depends up on nMOS or pMOS logic.

3) When using nMOS switch logic no pass transistor gate input may be driven through
one or more pass transistors as shown in figure.

4) Since the signal out of pass transistor T1 does not reach a full logic 1 by threshold
voltage effects signal is degraded by below a true logic 1, this degraged voltage
would not permit the output of T2 to reach an acceptable logic 1 level.

Advantages

They have topological simplicity.

1) Requires minimum geometry.

2) Do not dissipate standby power, since they do not have a path from supply to ground.

Disadvantages

1) Degradation in the voltage levels due to undesirable threshold voltage effects.

2) Never drive a pass transistor with the output of another pass transistor.
TRANSMISSION GATE

1) It is an electronic element, good non-mechanical relay built with CMOS technology.

2) It is made by parallel combination of an nMOS and pMOS transistors with the input
at gate of one transistor being complementary to the input at the gate of the other as
shown in figure.

3) Thus current can flow through this element in either direction.

4) Depending on whether or not there is a voltage on the gate, the connection between
the input and output is either low resistance or high-resistance, respectively Ron = 100Ω and Roff
> 5 MΩ.

Operation

• When the gate input to the nMOS transistor is ‗0‘ and the complementary ‗1‘ is gate input
to the pMOS , thus both are turned off.
• When gate input to the nMOS is ‗1‘ and its complementary ‗0‘ is the gate input to the
pMOS , both are turned on and passes any signal ‗1‘ and ‗0‘ equally without any
degradation.
• The use of transmission gates eliminates the undesirable threshold voltage effects which
give rise to loss of logic levels in pass-transistors as shown in figure.

Advantages

1) Transmission gates eliminates the signal degradation in the output logic levels.
2) Transmission gate consists of two transistors in parallel and except near the positive and
negative rails.

Disadvantages

1) Transmission gate requires more area than nMOS pass circuitry.

2) Transmission gate requires complemented control signals.

“ Transmission gate logic can be used to design multiplexers(selector functions)”.

Design a 2-input multiplexer using CMOS transmission gates.

Figure shows a 2-input multiplexer circuit using CMOS transmission gate.

If the control input S is low, the TG0 conducts and the output F is equal to A. On the other hand,
if the control input S is high the TG1 conducts and the output F is equal to B.

ALTERNATIVE GATE CIRCUITS

CMOS suffers from increased area and correspondingly increased capacitance and delay, as the
logic gates become more complex. For this reason, designers developed circuits (Alternate gate
circuits) that can be used to supplement the complementary type circuits . These forms are not
intended to replace CMOS but rather to be used in special applications for special purposes.

PSEUDO nMOS Logic

Pseudo nMOS logic is one type of alternate gate circuit that is used as a supplement for the
complementary MOS logic circuits. In the pseudo-nMOS logic, the pull up network (PUN) is
realized by a single pMOS transistor. The gate terminal of the pMOS transistor is connected to
the ground. It remains permanently in the ON state. Depending on the input combinations, output
goes low through the PDN. Figure shows the general building block of logic circuits that follows
pseudo nMOS logic.

13
Here, onlu the nMOS logic (Qn) is driven by the input voltage, while the gate of p-transistor(Qp)
is connected to ground or substrate and Qp acts as an active load for Qn. Except for the load
device, the pseudo-nMOS gate circuit is identical to the pull-down network(PDN) of the
complementary CMOS gate.

The realization of logic circuits using pseudo-nMOS logic is as shown in figure.

Advantages
14
 1) Uses less number of transistors as compared to CMOS logic.

2) Geometrical area and delay gets reduced as it requires less transistors.

3) Low power dissipation.

Disadvantages

1) The main drawback of using a pseudo nMOS gate instead of a CMOS gate is that the
always on PMOS load conducts a steady current when the output voltage is lower than
VDD.

2) Layout problems are critical.

DYNAMIC CMOS LOGIC

A dynamic CMOS logic uses charge storage and clocking properties of MOS transistors to
implement logic operations. Figure shows the basic building block of dynamic CMOS logic.
Here the clock ø drives nMOS evaluation transistor and pMOS precharge transistor. A logic is
implemented using an nFET array connected between output node and ground.

The gate (clock ø) defines two phases, evaluation and precharge phase during each clock cycle.

Working

15
 • When clock ø = 0 the circuit is in precharge phase with the pMOS device Mp ON and the
evaluation nMOS Mn OFF. This establishes a conducting path between VDD and the
output allowing Cout to charge to a voltage Vout = VDD. Mp is often called the precharge
FET.

• When clock ø = 1 the circuit is in evaluation phase with the pMOS device Mp OFF and
the evaluation nMOS Mn ON. If the logic block acts like a closed switch the Cout can
discharge through logic array and Mn, this gives a final result of Vout = VDD, logically
this is an output of F = 1. Charge leakage eventually drops the output to Vout = 0 Vwhich
could be an incorrect logic value.

The logic formation is formed by three series connected FETs (3-input NAND gate) is shown in
figure.

The dynamic CMOS logic circuit has a serious problem when they are cascaded. In the
precharged phase (ø = 0) , output of all the stages are pre-charged to logic high. In the evaluation
phase (ø = 1), the output of all stages are evaluated simultaneously. Suppose in the first stage, the
inputs are such that the output is logic low after the evaluation. In the second stage, the output of
the first stage is one input and there are other inputs. If theouther inputs of the second stage are
such that output of it discharges to logic low, then the evaluated output of the first stage can
never make the output of the second stage logic high. Ths is because, by the time the first stage is
being evaluated, output of the second. Stage is discharged, since evaluation happens
simultaneously. Remember that the output cannot be charged to logic high in the evaluation
phase (ø = 1, pMOSFET in PUN is OFF), it can only be retained in the logic high depending on
the inputs.

16
Advantages

1) Low power dissipation.

2) Large noise margin.

3) Small area due to less number of transistors.\

CMOS DOMINO LOGIC

Standard CMOS logic gates need a PMOS and an NMOS transistor for each logic input. The
pMOS transistors require a greater area tan the nMOS transistors carrying the same current. So, a
large chip area is necessary to perform complex logic operations. The package density in CMOS
is improved if a dynamic logic circuit, called the domino CMOS logic circuit, is used.

Domino CMOS logic is slightly modified version of the dynamic CMOS logic circuit. In this
case, a static inverter is connected at the output of each dynamic CMOS logic block. The
addition of the inverter solves the problem of cascading of dynamic CMOS logic circuits.

The circuit diagram of domino CMOS logic structures as shown in figure as follows

A domino CMOS AND-OR gate that realizes the function y = AB + CD is depicted in fugure .
The left hand part of the circuit containing Mn,Mp, T1,T2,,T3,and T4 forms and AND-OR-
INVERTER (AOI) gate. It derives the static CMOS inverter formed by N2 and P2 in the right-

17
hand part of the circuit. The domino gate is activated by the single phase clock ø applied to the
NMOS (Mn) and the PMOS (Mp) transistors. The load on the AOI part of the circuits is the
parasitic load capacitance.

Working

• When ø = 0, is ON and Mn is OFF, so that no current flows in the AND-OR paths of the
AOI. The capacitor CL is charged to VDD through Mp since the latter is ON. The input to
the inverter is high, and drives the output voltage V0 to logic-0.

• When ø = 1, Mp is turned OFF and Mn is turned ON. If either (or both) A and B or C and
D is at logic-1, CL discharges through either T2,T1 and Mn or T3,T4 and Mp. So , the
inverter input is driven to logic-0 and hence the output voltage V0 to logic-1. The
Boolean expression for the output voltage is Y = AB + CD.

Note : Logic input can change only when ø = 0. No changes of the inputs are permitted when ø =
1 since a discharge path may occur.

Advantages

1) Smaller areas compared to conventional CMOS logic.

2) Parasitic capacitances are smaller so that higher operating speeds are possible.

3) Operation is free of glitches since each gate can make one transition.

disadvantages

1) Non inverting structures are possible because of the presence of inverting buffer.

2) Charge distribution may be a problem.

CLOCKED CMOS LOGIC

2
The clocked CMOS logic is also referred as C MOS logic. Figure shows the general
2
arrangement of a clocked CMOS (C MOS) logic. A pull-up p-block and a complementary n-
block pull-down structure represent p and n-transistors respectively and are used as implement
clocked CMOS logic shown in figure. However, the logic in this case is connected to the output
only during the ON period of the clock. Figure shows a clocked inverter circuit which is also
belongs to clocked CMOS logic family. The slower rise times and fall times can be expected due
to owing of extra transistors in series with the output.

18
Working

• When ø = 1 the circuit acts an inverter , because transistors Q3 and Q4 are ‗ON‘ . It is
said to be in the ―evaluation mode‖. Therefore the output Z changes its previous value.

• When ø = 0 the circuit is in hold mode, because transistors Q3 and Q4 becomes ‗OFF‘ . It
is said to be in the ―precharge mode‖. Therefore the output Z remains its previous value.

n-p CMOS LOGIC

Figure shows the another variation of basic dynamic logic arrangement of CMOS logic called as
n-p CMOS logic. In this, logic the actual logic blocks are alternatively ‗n‘ and ‗p‘ in a cascaded
-
structure. The clock ø and ø are used alternatively to fed the precharge and evaluate transistors.
However, the functions of top and bottom transistors are also alternate between precharge and
evaluate transistors.

19
Working

• During the pre charge phase ø = 0 , the output of the n-tree gate, OUT 1 OUT3 , are
charged to VDD, while the output of the p-tree gate OUT2 is pre discharged to 0V. Since
the n-tree gate connects pMOS pull-up devices, the PUN of the p-tree is turned off at that
time.

• During the evaluation phase ø = 1, the outputs (OUT1,OUT3) of the n-tree gate can only
make a 1- 0 transition, conditionally turning on some transistors in the p-tree. This
ensures that no accidental discharge of OUT 2 can occur.

• Similarly n-tree blocks can follow p-tree gates without any problems, because the inputs
to the n-gate are pre charged to 0.

Disadvantages

Here, the p-tree blocks are slower than the n-tree modules, due to the lower current drive of the
pMOS transistors in the logic network.

20
PHYSICAL DESIGN

In integrated circuit design, physical design is a step in the standard design cycle
which follows after the circuit design. At this step, circuit representations of the components
(devices and interconnects) of the design are converted into geometric representations of
shapes which, when manufactured in the corresponding layers of materials, will ensure the
required functioning of the components. This geometric representation is called integrated
circuit layout. This step is usually split into several sub-steps, which include both design and
verification and validation of the layout.[1][2]

Modern day Integrated Circuit (IC) design is split up into

Front-end design using HDLs, Verification, and Back-end Design or Physical Design.
The next step after Physical Design is the Manufacturing process or Fabrication Process that
is done in the Wafer Fabrication Houses. Fab-houses fabricate designs onto silicon dies
which are then packaged into ICs.

Each of the phases mentioned above has Design Flows associated with them. These
Design Flows lay down the process and guide-lines/framework for that phase. Physical
Design flow uses the technology libraries that are provided by the fabrication houses. These
technology files provide information regarding the type of Silicon wafer used, the standard-
cells used, the layout rules (like DRC in VLSI), etc.

Physical design steps within the IC design flow

1 Divisions

Typically, the IC physical design is categorized into Full custom & Semi-Custom Design.

Full-Custom: Designer has full flexibility on the lay-out design, no predefined cells are
used.

Semi-Custom: Pre-designed library cells (preferably tested with DFM) are used,
designer has flexibility in placement of the cells & routing.[3]

One can refer ASIC for Full Custom design and FPGA for Semi-Custom design flows.
The reason being that one has the flexibility to design/modify design blocks from Vendor
provided libraries in ASIC.[4] This flexibility is missing for Semi-Custom flows like FPGA
(e.g. Altera).

2 ASIC Physical Design Flow

A typical ASIC back-end flow

The main steps in the ASIC physical design flow are:

 Floor planning

 Partitioning & Placement

 Clock-tree Synthesis (CTS) Routing

 PhysicalVerification
Physical Design Steps:

Floor planning

The first step in the physical design flow is Floorplanning. Floorplanning is the
process of identifying structures that should be placed close together, and allocating space for
them in such a manner as to meet the sometimes conflict-ing goals of available space (cost of
the chip), required performance, and the desire to have everything close to everything else.
Based on the area of the design and the hierarchy, a suit-able floorplan is decided upon.
Floorplanning takes into account the macros used in the design, memory, other IP cores and
their placement needs, the routing possibilities and also the area of the entire design.
Floorplanning also decides the IO structure, aspect ratio of the design. A bad floorplan will
lead to waste-age of die area and rout-ing congestion.

In many design methodologies, Area and Speed are con-sidered to be things that
should be traded off against each other. The reason this is so is probably because there are
limited routing resources, and the more routing re-sources that are used, the slower the design
will operate. Optimizing for minimum area allows the design to use fewer resources, but also
allows the sections of the design
Placement

Before the start of placement optimization all Wire Load Models (WLM) are
removed. Placement uses RC values from Virtual Route (VR) to calculate timing. VR is the
shortest Manhattan distance between two pins. VR RCs are more accurate than WLM RCs.
Placement is performed in four optimization phases:

2) Pre-placement optimization

3) In placement optimization

4) Post Placement Optimization (PPO) before clock tree synthesis (CTS)

5) PPO after CTS.

Pre-placement Optimization optimizes the netlist before placement, HFNs are

collapsed. It can also downsize the cells.
In-placement optimization re-optimizes the logic based on VR. This can perform cell
sizing, cell mov-ing, cell bypassing, net splitting, gate duplication, buffer insertion, area
recovery. Optimization per-forms iteration of setup fixing, incremental timing and
congestion driven placement.

Post placement optimization before CTS performs netlist optimization with ideal
clocks. It can fix setup, hold, max trans/cap violations. It can do placement optimization
 based on global routing. It re does HFN synthesis. Post placement optimization after CTS
optimizes timing with propagated clock. It tries to preserve clock skewClock tree
synthesis

Ideal clock before CTS

The goal of clock tree synthesis (CTS) is to minimize skew and insertion delay. Clock is
not propagated before CTS as shown in the picture. After CTS hold slack should improve.
Clock tree begins at .sdc defined clock source and ends at stop pins of flop. There are two
types of stop pins known as ignore pins and sync pins. ‗Don‘t touch‘ circuits and pins in front
end (logic synthesis) are treated as ‗ignore‘ circuits or pins at back end (physical synthesis).
‗Ignore‘ pins are ignored for timing analysis. If clock is divided then separate skew analysis
is necessary.

Global skew achieves zero skew between two synchronous pins without considering
logic relation-ship.

Local skew achieves zero skew between two synchronous pins while considering logic
relationship.

If clock is skewed intentionally to improve setup slack then it is known as useful skew.

Rigidity is the term coined in Astro to indicate the relaxation of constraints. Higher the
rigidity tighter is the constraints.

In clock tree optimization (CTO) clock can be shielded so that noise is not coupled to other
signals. But shield-ing increases area by 12 to 15%. Since the clock signal is global in nature
the same metal layer used for power routing is used for clock also. CTO is achieved by buffer
Clock After CTS sizing, gate sizing, buffer relocation, level adjustment and HFN synthesis.
We try to improve setup slack in pre-placement, in placement and post placement optimiza-
tion before CTS stages while neglecting hold slack. In post placement optimization after CTS
hold slack is im-proved. As a result of CTS lot of buffers are added. Gen-erally for 100k
gates around 650 buffers are added.

Routing

There are two types of routing in the physical design pro-cess, global routing and
detailed routing. Global routing allocates routing resources that are used for connections.
Physical Verification

Physical verification checks the correctness of the generated layout design. This includes
verifying that the layout

Complies with all technology requirements – Design Rule Checking (DRC)

Is consistent with the original net list – Layout vs. Schematic (LVS)

Has no antenna effects – Antenna Rule Checking

This also includes density verification at the full chip level...Cleaning density is a very
critical step in the lower technology nodes

Complies with all electrical requirements – Electrical Rule Checking (ERC).[5]

POWER DELAY ESTIMATION:

Delay Estimation

Delay Estimation : The propagation delay (tp) of a gate is defined as the time taken by
a gate to respond when there is change on its inputs. It expresses the delay experienced by a
signal when passing through a gate. It is measured between the 50% transition points of the
input and output waveforms as shown in below Figure for an inverter.

As a gate shows different response times for rising or falling input waveforms the
propagation delay is defined by two terms.

The tpLH defines the response time of the gate for a low to high output transition
while tpHL refers to high to low transition. The propagation delay (tp) is defined as the
average of these two times :

i.e. tp = tpLH + tpHL2

The propagation delay is function of both circuit technology and the style of the
circuit. Also the delay is function of the slopes of the input and output signals of the gate. In
order to consider this effect the terms rise time (tr) and fall time (tf) are introduced.
 The rise and fall times are defined between the 10% and 90% points of the waveform
as shown in Fig. The rise and fall times of a signal are determined by the strength of the
driving gate and the load connected to it.

CLOCK AND POWER ROUTING:

Power and Ground Routing:

In a design, almost all blocks require power and ground connections.

Power and ground nets are usually laid out entirely on the metal layer(s) of the chip.
– Due to smaller resistivity of metal.

– Planar single-layer implementation is desirable since contacts (via‘s) also significantly add to the
parasitics.
Routing of power (VDD) and ground (GND) nets consists of two main tasks:
– Construction of interconnection topology.

– Determination of the widths of the various segments

 UNIT IV

SUBSYSTEM DESIGN

Objectives: At the end of this unit we will be able to understand

• Design consideration, problem and solution

• Design processes
• Basic digital processor structure
• Data path
• Bus Architecture
• Design 4 – bit shifter
• Design of ALU subsystem
• 4 – bit Adder
General Considerations:
Lower unit cost
Higher reliability
Lower power dissipation, lower weight and lower volume
Better performance
Enhanced repeatability
Possibility of reduced design/development periods

Some Problems :

• How to design complex systems in a reasonable time & with reasonable effort.
• The nature of architectures best suited to take full advantage of VLSI and the
technology
• The testability of large/complex systems once implemented on silicon

Some Solution

Problem 1 & 3 are greatly reduced if two aspects of standard practices are
accepted.
• a) Top-down design approach with adequate CAD toolsto do the job
Partitioning the system sensibly
Aiming for simple interconnections
High regularity within subsystem
Generate and then verify each section of the design
• Devote significant portion of total chip area to test and diagnostic facility
• Select architectures that allow design objectives and high regularity in realization
Illustration of design processes
1. Structured design begins with the concept of hierarchy
2. It is possible to divide any complex function into less complex sub functions that is up to
leaf cells
3. Process is known as top-down design
4. As a systems complexity increases, its organization changes as different factors become
relevant to its creation
5. Coupling can be used as a measure of how much sub models interact
6. It is crucial that components interacting with high frequency be physically
proximate, since one may pay severe penalties for long, high-bandwidth
interconnects
7. Concurrency should be exploited – it is desirable that all gates on the chip do useful
work most of the time
8. Because technology changes so fast, the adaptation to a new process must occur in a short
time.
Hence representing a design several approaches are possible. They are:

• Conventional circuit symbols

• Logic symbols
• Stick diagram
• Any mixture of logic symbols and stick diagram thatis convenient at a stage
• Mask layouts
• Architectural block diagrams and floor plans
General arrangements of a 4 – bit arithmetic processor

The basic architecture of digital processor structure is as shown below in figure

Here the design of datapath is only considered.

Datapath is as shown below in figure 6.2. It is seen that the structure comprises of a unit
which processes data applied at one port andpresents its output at a second port.
Alternatively, the two data ports may be combined as a single bidirectional port if storage
facilities exist in the datapath. Control over the functions to be performed is effected by
control signals as shown
Communication strategy for the datapath

Datapath can be decomposed into blocks showing the main subunits as in figure 3. In
doing so it is useful to anticipate a possible floor plan to show the planned relative
decomposition of the subunits on the chip and hence on the mask layouts.

Subunits and basic interconnection for datapath

Nature of the bus architecture linking the subunits is discussed below. Some of the
possibilities are:

One bus architecture:

Sequence:
st
1. 1 operand from registers to ALU. Operand is stored there.
nd
2. 2 operand from register to ALU and added.
3. Result is passed through shifter and stored in the register
Two bus architecture

Sequence:
1. Two operands (A & B) are sent from register(s) to ALU & are operated upon, result
S in ALU.
2. Result is passed through the shifter & stored in registers.
Three bus architecture:

Three bus architecture

Sequence:

Two operands (A & B) are sent from registers, operated upon, and shifted result (S) returned
to another register, all in same clock period.

In pursuing this design exercise, it was decided toimplement the structure with a 2 – bus
architecture. A tentative floor plan of theproposed design which includes some form of
interface to the parent system data bus is shown in figure
Tentative floor plan for 4 – bit datapath

The proposed processor will be seen to comprise a register array in which 4-bit numbers can
be stored, either from an I/O port or from the output of the ALU via a shifter. Numbers from
the register array can be fedin pairs to the ALU to be added (or subtracted)
and the result can be shifted or not. The data connections between the I/O port, ALU,
and shifter must be in the form of 4-bitbuses. Also, each of the blocks must be suitably
connected to control lines so that its function may be defined for any of a range of
possible operations.

During the design process, and in particular when defining the interconnection strategy and
designing the stick diagrams, care must be taken in allocating the layers to the various data or
control paths. Points to be noted:

Metal can cross poly or diffusion Poly crossing diffusion form a transistor Whenever lines
touch on the same level an interconnection is formed Simple contacts can be used to join
diffusion or poly to metal.
Buried contacts or a butting contacts can be used to join diffusion and poly Each layer has
particular electrical properties which must be taken into account For CMOS layouts, p-and
n-diffusion wires must not directly join each other Nor may they cross either a p-well or an
n-well boundary

Design of a 4-bit shifter

Any general purpose n-bit shifter should be able toshift incoming data by up to n – 1 place in
a right-shift or left-shift direction. Further specifying that all shifts should be on an end-
around basis, so that any bit shifted out at one end of a data word will be shifted in at the
other end of the word, then the problem of right shift or left shift is greatly eased. It can be
analyzed that for a 4-bit word, that a 1-bit shift right is equivalent to a 3-bit shift left and a 2-
bit shift right is equivalent to a 2-bit left etc. Hence, the design of either shift right or left can
be done. Here thedesign is of shift right by 0, 1, 2, or 3 places.
The shifter must have:

• input from a four line parallel data bus

• four output lines for the shifted data

• means of transferring input data to output lines with any shift from 0 to 3 bits

Consider a direct MOS switch implementation of a 4 X 4 crossbar switches shown in figure

6.8. The arrangement is general and may be expanded to accommodate n-bit inputs/outputs.
In this arrangement any input can be connected to any or all the outputs.

Furthermore, 16 control signals (sw00 – sw15), one for each transistor switch, must be
provided to drive the crossbar switch, and such complexity is highly undesirable.

4 X 4 crossbar switch

An adaptation of this arrangement recognizes the fact that we couple the switch gates
together in groups of four and also form four separate groups corresponding to shifts
of zero, one, two and three bits. The resulting arrangement is known as a barrel
shifter and a 4 X 4 barrel shifter circuit diagram is as shown in the figure
BARREL SHIFTER

The interbus switches have their gate inputs connected in a staircase fashion in
groups of four and there are now fourshift control inputs which must be mutually
exclusive in the active state. CMOS transmission gates may be used in place of the simple
pass transistor switches if appropriate. Barrel shifter connects the input lines representing a
word to a group of output lines withthe required shift determined by its control inputs (sh0,
sh1, sh2, sh3). Control inputsalso determine the direction of the shift.

If input word has n – bits and shifts from 0 to n-1bit positions are to be implemented.

To summaries the design steps

Set out the specifications

Partition the architecture into subsystems
Set a tentative floor plan
Determine the interconnects
Choose layers for the bus & control lines
Conceive a regular architecture
Develop stick diagram
Produce mask layouts for standard cell
Cascade & replicate standard cells as required to complete the design

Design of an ALU subsystem

Having designed the shifter, we shall design another subsystem of the 4-bit data path. An
appropriate choice is ALU as shown in the figure below.

4-bit data path for processor

The heart of the ALU is a 4-bit adder circuit. A 4-bit adder must take sum of two 4-bit
numbers, and there is an assumption that all 4-bit quantities are presented in parallel form and
that the shifter circuit is designed to accept and shift a 4-bit parallel sum from the ALU. The
sum is to be stored in parallel at theoutput of the adder from where it is fed through the shifter
and back to the register array. Therefore, a single 4-bit data bus is needed from the adder to
the shifter and another 4-bit bus is required from the shifted output back to the register
array. Hence, for an adder two 4-bit parallel numbers are fed on two 4-bit buses. The clock
signal is also required to the adder, during which the inputs are given and sum is generated.
The shifter is unclocked but must be connected to four shift control lines.

Design of a 4-bit adder:

The truth table of binary adder is as shown in table

What is parity bit:

The parity generating technique is one of the most widely used error detection
techniques for the data transmission. In digital systems, when binary data is transmitted and
processed , data may be subjected to noise so that such noise can alter 0s (of data bits) to 1s
and 1s to 0s.

Hence, parity bit is added to the word containing data in order to make number of 1s
either even or odd.Thus it is used to detect errors , during the transmission of binary data .The
message containing the data bits along with parity bit is transmitted from transmitter node to
receiver node.

At the receiving end, the number of 1s in the message is counted and if it doesn‘t
match with the transmitted one, then it means there is an error in the data.

Parity generator and checker:

A parity generator is a combinational logic circuit that generates the parity bit in the
transmitter. On the other hand, a circuit that checks the parity in the receiver is called parity
checker. A combined circuit or devices of parity generators and parity checkers are
commonly used in digital systems to detect the single bit errors in the transmitted data word.

The sum of the data bits and parity bits can be even or odd . In even parity, the added
parity bit will make the total number of 1s an even amount whereas in odd parity the added
parity bit will make the total number of 1s odd amount.

The basic principle involved in the implementation of parity circuits is that sum of
odd number of 1s is always 1 and sum of even number of 1s is always zero. Such error
detecting and correction can be implemented by using Ex-OR gates (since Ex-OR gate
produce zero output when there are even number of inputs).

To produce two bits sum, one Ex-OR gate is sufficient whereas for adding three bits
two Ex-OR gates are required as shown in below figure.

Parity Generator:

It is combinational circuit that accepts an n-1 bit stream data and generates the
additional bit that is to be transmitted with the bit stream. This additional or extra bit is
termed as a parity bit.

In even parity bit scheme, the parity bit is ‗0‘ if there are even number of 1s in the
data stream and the parity bit is ‗1‘ if there are odd number of 1s in the data stream.

In odd parity bit scheme, the parity bit is ‗1‘ if there are even number of 1s in the
data stream and the parity bit is ‗0‘ if there are odd number of 1s in the data stream. Let us
discuss both even and odd parity generators.
Even Parity Generator

Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the
three inputs A, B and C are applied to the circuits and output bit is the parity bit P. The total
number of 1s must be even, to generate the even parity bit P.

The figure below shows the truth table of even parity generator in which 1 is placed as
parity bit in order to make all 1s as even when the number of 1s in the truth table is odd.

The K-map simplification for 3-bit message even parity generator is

From the above truth table, the simplified expression of the parity bit can be written as
 The above expression can be implemented by using two Ex-OR gates. The logic
diagram of even parity generator with two Ex – OR gates is shown below. The three bit
message along with the parity generated by this circuit which is transmitted to the receiving
end where parity checker circuit checks whether any error is present or not.

Parity Generator:

It is combinational circuit that accepts an n-1 bit stream data and generates the
additional bit that is to be transmitted with the bit stream. This additional or extra bit is
termed as a parity bit.

In even parity bit scheme, the parity bit is ‗0‘ if there are even number of 1s in the
data stream and the parity bit is ‗1‘ if there are odd number of 1s in the data stream.

In odd parity bit scheme, the parity bit is ‗1‘ if there are even number of 1s in the
data stream and the parity bit is ‗0‘ if there are odd number of 1s in the data stream. Let us
discuss both even and odd parity generators.

Even Parity Generator

Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the
three inputs A, B and C are applied to the circuits and output bit is the parity bit P. The total
number of 1s must be even, to generate the even parity bit P.

The figure below shows the truth table of even parity generator in which 1 is placed as
parity bit in order to make all 1s as even when the number of 1s in the truth table is odd.
The K-map simplification for 3-bit message even parity generator is

From the above truth table, the simplified expression of the parity bit can be written as

The above expression can be implemented by using two Ex-OR gates. The logic
diagram of even parity generator with two Ex – OR gates is shown below. The three bit
message along with the parity generated by this circuit which is transmitted to the receiving
end where parity checker circuit checks whether any error is present or not.
To generate the even parity bit for a 4-bit data, three Ex-OR gates are required to add the 4-
bits and their sum will be the parity bit.

Odd Parity Generator

Let us consider that the 3-bit data is to be transmitted with an odd parity bit. The three
inputs are A, B and C and P is the output parity bit. The total number of bits must be odd in
order to generate the odd parity bit.

In the given truth table below, 1 is placed in the parity bit in order to make the total
number of bits odd when the total number of 1s in the truth table is even.

The truth table of the odd parity generator can be simplified by using K-map as
The output parity bit expression for this generator circuit is obtained as

P = A ⊕ B Ex-NOR C

The above Boolean expression can be implemented by using one Ex-OR gate and one
Ex-NOR gate in order to design a 3-bit odd parity generator.

The logic circuit of this generator is shown in below figure , in which . two inputs are
applied at one Ex-OR gate, and this Ex-OR output and third input is applied to the Ex-NOR
gate , to produce the odd parity bit. It is also possible to design this circuit by using two Ex-
OR gates and one NOT gate.

Parity Check

It is a logic circuit that checks for possible errors in the transmission. This circuit can
be an even parity checker or odd parity checker depending on the type of parity generated at
the transmission end. When this circuit is used as even parity checker, the number of input
bits must always be even.

When a parity error occurs, the ‗sum even‘ output goes low and ‗sum odd‘ output
goes high. If this logic circuit is used as an odd parity checker, the number of input bits
should be odd, but if an error occurs the ‗sum odd‘ output goes low and ‗sum even‘ output
goes high.
Even Parity Checker

Consider that three input message along with even parity bit is generated at the
transmitting end. These 4 bits are applied as input to the parity checker circuit which checks
the possibility of error on the data. Since the data is transmitted with even parity, four bits
received at circuit must have an even number of 1s.

If any error occurs, the received message consists of odd number of 1s. The output of
the parity checker is denoted by PEC (parity error check).

The below table shows the truth table for the even parity checker in which PEC = 1 if
the error occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error
occurs, i.e., if the 4-bit message has even number of 1s.

The above truth table can be simplified using K-map as shown below.
 The above logic expression for the even parity checker can be implemented by using
three Ex-OR gates as shown in figure. If the received message consists of five bits, then one
more Ex-OR gate is required for the even parity checking.

Odd Parity Checker

Consider that a three bit message along with odd parity bit is transmitted at the
transmitting end. Odd parity checker circuit receives these 4 bits and checks whether any
error are present in the data.
 If the total number of 1s in the data is odd, then it indicates no error, whereas if the
total number of 1s is even then it indicates the error since the data is transmitted with odd
parity at transmitting end.

The below figure shows the truth table for odd parity generator where PEC =1 if the
4-bit message received consists of even number of 1s (hence the error occurred) and PEC=
0 if the message contains odd number of 1s (that means no error).

The expression for the PEC in the above truth table can be simplified by K-map as shown
below.
After simplification, the final expression for the PEC is obtained as

PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR D)

The expression for the odd parity checker can be designed by using three Ex-NOR gates as
shown below.

Parity Generator/Checker ICs:

There are different types of parity generator /checker ICs are available with different
input configurations such as 5-bit, 4-bit, 9-bit, 12-bit, etc. A most commonly used and
standard type of parity generator/checker IC is 74180.

It is a 9-bit parity generator or checker used to detect errors in high speed data
transmission or data retrieval systems. The figure below shows the pin diagram of 74180 IC.

This IC can be used to generate a 9-bit odd or even parity code or it can be used to
check for odd or even parity in a 9-bit code (8 data bits and one parity bit).
 This IC consists of eight parity inputs from A through H and two cascading inputs.
There are two outputs even sum and odd sum. In implementing generator or checker circuits,
unused parity bits must be tied to logic zero and the cascading inputs must not be equal.

Digital Comparator:

Fig.Digital Comparator
Another common and very useful combinational logic circuit is that of the Digital
Comparator circuit. Digital or Binary Comparators are made up from standard AND, NOR
and NOT gates that compare the digital signals present at their input terminals and produce
an output depending upon the condition of those inputs.

For example, along with being able to add and subtract binary numbers we need to be
able to compare them and determine whether the value of input A is greater than, smaller
than or equal to the value at input B etc. The digital comparator accomplishes this using
several logic gates that operate on the principles of Boolean Algebra. There are two main
types of Digital Comparator available and these are.

 1. Identity Comparator – an Identity Comparator is a digital comparator that has only one
output terminal for when A = B either ―HIGH‖ A = B = 1 or ―LOW‖ A = B = 0
 2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which has three
output terminals, one each for equality, A = B greater than, A > B and less than A < B
 The purpose of a Digital Comparator is to compare a set of variables or unknown
numbers, for example A (A1, A2, A3, …. An, etc) against that of a constant or unknown
value such as B (B1, B2, B3, …. Bn, etc) and produce an output condition or flag depending
upon the result of the comparison. For example, a magnitude comparator of two 1-bits, (A
and B) inputs would produce the following three output conditions when compared to each
other.

Which means: A is greater than B, A is equal to B, and A is less than B

This is useful if we want to compare two variables and want to produce an output when any
of the above three conditions are achieved. For example, produce an output from a counter
when a certain count number is reached. Consider the simple 1-bit comparator below.

1-bit Digital Comparator Circuit

Then the operation of a 1-bit digital comparator is given in the following Truth Table.

Digital Comparator Truth Table

Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

You may notice two distinct features about the comparator from the above truth table.
Firstly, the circuit does not distinguish between either two ―0‖ or two ―1‖‗s as an output A =
B is produced when they are both equal, either A = B = ―0‖ or A = B = ―1‖. Secondly, the
output condition for A = B resembles that of a commonly available logic gate, the Exclusive-
NOR or Ex-NOR function (equivalence) on each of the n-bits giving: Q = A ⊕ B

Digital comparators actually use Exclusive-NOR gates within their design for
comparing their respective pairs of bits. When we are comparing two binary or BCD values
or variables against each other, we are comparing the ―magnitude‖ of these values, a logic
―0‖ against a logic ―1‖ which is where the term Magnitude Comparator comes from.
 As well as comparing individual bits, we can design larger bit comparators by
cascading together n of these and produce a n-bit comparator just as we did for the n-bit
adder in the previous tutorial. Multi-bit comparators can be constructed to compare whole
binary or BCD words to produce an output if one word is larger, equal to or less than the
other.

A very good example of this is the 4-bit Magnitude Comparator. Here, two 4-bit
words (―nibbles‖) are compared to each other to produce the relevant output with one word
connected to inputs A and the other to be compared against connected to input B as shown
below.

4-bit Magnitude Comparator

Some commercially available digital comparators such as the TTL 74LS85 or CMOS
4063 4-bit magnitude comparator have additional input terminals that allow more individual
comparators to be ―cascaded‖ together to compare words larger than 4-bits with magnitude
comparators of ―n‖-bits being produced. These cascading inputs are connected directly to the
corresponding outputs of the previous comparator as shown to compare 8, 16 or even 32-bit
words.

8-bit Word Comparator:

 When comparing large binary or BCD numbers like the example above, to save time
the comparator starts by comparing the highest-order bit (MSB) first. If equality exists, A = B
then it compares the next lowest bit and so on until it reaches the lowest-order bit, (LSB). If
equality still exists then the two numbers are defined as being equal.

If inequality is found, either A > B or A < B the relationship between the two
numbers is determined and the comparison between any additional lower order bits stops.
Digital Comparator are used widely in Analogue-to-Digital converters, (ADC) and
Arithmetic Logic Units, (ALU) to perform a variety of arithmetic operations.

ZERO/ONE DETECTOR:

Zero/One detector :
Detecting all ones or zeros on wide N-bit words requires large fan-in AND or NOR gates.
Recall that by DeMorgan's law, AND, OR, NAND, and NOR are funda-mentally the same
operation except for possible inversions of the inputs and/or outputs. You can build a tree of
AND gateS. Here, alternate NAND and NOR gates have been used. The path has log N
stages.

ADVANTAGES:
A Zero Crossing Detector Circuit is a useful application of Op-amp as Comparator. It is used
to track the changing in the sine waveform from positive to negative or vice versa while
it crosses Zero voltage. It can also be used as a Square Wave Generator.
Drawback in zero crossing detectors:
Due to low frequency signal, the output voltage may not switch quickly from one
saturation voltage to other. The presence of noise can fluctuate the output between two
saturation voltages.
APPLICATIONS :
The zero crossing detector circuit changes the comparator's output state when the AC
input crosses the zero reference voltage. This is done by setting the comparator inverting
input to the zero reference voltage and applying the attenuated input to the noninverting
input.
COUNTERS:

Asynchronous Counters

Asynchronous counters are those whose output is free from the clock signal. Because the flip
flops in asynchronous counters are supplied with different clock signals, there may be delay
in producing output.

The required number of logic gates to design asynchronous counters is very less. So they are
simple in design. Another name for Asynchronous counters is ―Ripple counters‖.

The number of flip flops used in a ripple counter is depends up on the number of states of
counter (ex: Mod 4, Mod 2 etc). The number of output states of counter is called ―Modulus‖
or ―MOD‖ of the counter. The maximum number of states that a counter can have is 2n
where n represents the number of flip flops used in counter.

For example, if we have 2 flip flops, the maximum number of outputs of the counter is 4 i.e.
22. So it is called as ―MOD-4 counter‖ or ―Modulus 4 counter‖.

Different types of Asynchronous counters

There are many types of Asynchronous counters available in digital electronics. They are

 4 bit synchronous UP counter

 4 bit synchronous DOWN counter
 4 bit synchronous UP / DOWN counter
Asynchronous 4-bit UP counter

A 4 bit asynchronous UP counter with D flip flop is shown in above diagram. It is capable of
counting numbers from 0 to 15. The clock inputs of all flip flops are cascaded and the D input
(DATA input) of each flip flop is connected to a state output of the flip flop.

That means the flip flops will toggle at each active edge or positive edge of the clock signal.
The clock input is connected to first flip flop. The other flip flops in counter receive the clock
signal input from Q‘ output of previous flip flop. The output of the first flip flop will change,
when the positive edge on clock signal occurs.

In the asynchronous 4- bit up counter, the flip flops are connected in toggle mode, so when
the when the clock input is connected to first flip flop FF0, then its output after one clock
pulse will become 20.

The rising edge of the Q output of each flip flop triggers the clock input of its next flip flop. It
triggers the next clock frequency to half of its applied input. The Q outputs of every
individual flip flop (Q0, Q1, Q2, Q3) represents the count of the 4 bit UP counter such as 20
(1) to 23 (8).

Working of asynchronous up counter is explained below,

Let us assume that the 4 Q outputs of the flip flops are initially 0000. When the rising edge of
the clock pulse is applied to the FF0, then the output Q0 will change to logic 1 and the next
clock pulse will change the Q0 output to logic 0. This means the output state of the clock
pulse toggles (changes from 0 to1) for one cycle.
As the Q‘ of FF0 is connected to the clock input of FF1, then the clock input of second flip
flop will become 1. This makes the output of FF1 to be high (i.e. Q1 = 1), which indicates the
value 20. In this way the next clock pulse will make the Q0 to become high again.

So now both Q0 and Q1 are high, this results in making the 4 bit output 11002. Now if we
apply the fourth clock pulse, it will make the Q0 and Q1 to low state and toggles the FF2. So
the output Q2 will become 0010¬2. As this circuit is 4 bit up counter, the output is sequence
of binary values from 0, 1, 2, 3….15 i.e. 00002 to 11112 (0 to 1510).

Timing diagram of Asynchronous counter

Advantages

 Asynchronous counters can be easily designed by T flip flop or D flip flop.

 These are also called as Ripple counters, and are used in low speed circuits.
 They are used as Divide by- n counters, which divide the input by n, where n is an
integer.
 Asynchronous counters are also used as Truncated counters. These can be used to
design any mod number counters, i.e. even Mod (ex: mod 4) or odd Mod (ex: mod3).
Disadvantages

 Sometimes extra flip flop may be required for ―Re synchronization‖.

 To count the sequence of truncated counters (mod is not equal to 2n), we need
additional feedback logic.
 While counting large number of bits, the propagation delay of asynchronous counters
is very large.
 For high clock frequencies, counting errors may occur, due to propagation delay.

Applications of Asynchronous Counters

 Asynchronous counters are used as frequency dividers, as divide by N counters.

 These are used for low power applications and low noise emission.
 These are used in designing asynchronous decade counter.
 Also used in Ring counter and Johnson counter.
 Asynchronous counters are used in Mod N ripple counters. EX: Mod 3, Mod 4, Mod
8, Mod 14, Mod 10 etc.
HIGH DENSITY MEMORY ELEMENTS:
Static Random Access Memory (SRAM)
SRAM Architecture:

The typical SRAM design is shown in figure 1.8 the memory array contains the memory cells
which are readable and writable. The Row decoder selects from 1 out of n = 2k rows, while
the column decoder selects l = 2i out of m = 2j columns. The addresses are not multiplexed as
it in the DRAM. Sense amplifier detects small voltage variations on the memory
complimentary bitline which reduces the reading time. The conditioning circuit is used to
pre-charge the bit lines.
In a read operation, the bitlines are precharged to some reference voltage usually close to the
supply voltage. When word line turns high, the access transistor connected to the node storing
„0‟ starts discharging the bitline while the complementary bitline remains in its precharged
state, resulting in a differential voltage between the bitline pair.
Since the SRAM has an optimized area results in a small cell current and slow bitline
discharge rate. In order to speed up the RAM access, sense amplifiers are used which amplify
the small bitline signal and eventually drive it to the external world.
The word ―static‖ means that the memory retains its contents as long as the power is turned
on. Random access means that locations in the memory can be written to or read from in any
order, regardless of the memory location that was last accessed. Each bit in an SRAM is
stored on four transistors that form two cross-coupled inverters. This storage cell has two
stable states which are used to denote „0‟ and „1‟. The access transistors are used to access
the stored bits in the SRAM during read or write mode.
It thus typically takes six MOSFETs to store one memory bit. Access to the cell is enabled by
the word line WL which controls the two access transistors N1 and N2 which, in turn, control
whether the cell should be connected to the bitlines BL and /BL.
They are used to transfer data for both read and write operations. The bitlines are
complementary as it improves the noise margin. Chapter 2 explains more about SRAMs and
its Read/Write operations.
 UNIT –V
SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN

CPLD & FPGA ARCHITECTURE & APPLICATIONS

Introduction : The need of programmable devices was realized in early 70s itself with the
design of PLD by Ron Cline from Signetics . The digital ICs like TTL or CMOS have fixed
functionality and the user has no option to change or modify their functionality .i.e they work
according to the design given by the manufacturer. So,to change this people started thinking
of a methodology by which the functionality of an IC can be modified or changed. Then the
concept of using Fuses in ICs entered and gained momentum. This method of changing or
modifying the functionality of an IC using the Fuses was appreciated and this method of
blowing a Fuse between two contacts or keeping the Fuse intact was done by using a
software and hence these devices were called Programmable Logic Devices(PLDs). Many
digital chips were considered under the category of PLDs .But the most fundamental and
primitive was the Memories like ROM or PROM etc.
The realization of Digital circuits by PLDs can be classified as shown in the diagram
below.

PLAs were introduced in the early 1970s, by Philips, but their main drawbacks were
that they were expensive to manufacture and offered somewhat poor speed-performance.
Both disadvantages were due to the two levels of configurable logic, because programmable
logic planes were difficult to manufacture and introduced significant propagation delays. To
overcome these problems , Programmable Array Logic (PAL) devices were developed.
Memory : Memory is used to store, provide access to, and allow modification of data and
program code for use within a processor-based electronic circuit or system. The two basic
types of memory are ROM (read-only memory) and RAM (random access memory).
ROM is used for holding program code that must be retained when the memory power is
removed. It is considered to provide nonvolatile storage. The code can either be fixed when
the memory is fabricated (mask programmable ROM) or electrically programmed once
(PROM, Programmable ROM) or multiple times. Multiple programming capacity requires
the ability to erase prior programming, which is available with EPROM (electrically
programmable ROM, erased using ultraviolet [UV] light), EEPROM or EEPROM
(electrically erasable PROM), or flash (also electrically erased). PROM is sometimes
considered to be in the same category of circuit as programmable logic, although in this text,
PROM is considered in the memory category only.
RAM is used for holding data and program code that require fast access and the
ability to modify the contents during normal operation. RAM differs from read-only memory
(ROM) in that it can be both read from and written to in the normal circuit application.
However, flash memory can also be referred to as nonvolatile RAM (NVRAM). RAM is
considered to provide a volatile storage, because unlike ROM, the contents of RAM will be
lost when the power is removed. There are two main types of RAM: static RAM (SRAM)
and dynamic RAM (DRAM).

ROM- READ ONLY MEMORY : A ROM is essentially a memory device for storage
purpose in which a fixed set of binary information is stored. The user must first specify the
binary information to be stored and then it is embedded in the unit to form the required
interconnection pattern. ROM contains special internal links that can be fused or broken.
Certain links are to be broken or blown out to realize the desired interconnections for a
particular application and to form the required circuit path. Once a pattern is established for a
ROM, it remained fixed even if the power supply to the circuit is switched off and then
switched on again.
The block diagram of ROM is shown below. It consists of n input lines and m-output
lines. Each bit combination of input variables is called an address and each bit combination
that is formed at output lines is called a word. Thus, an address is essentially binary number
that denotes one of the min-terms of n variables and the number of bits per word is equal to
the number of output lines m. It is possible to generate p = 2n number of distinct addresses
from n number of input variables. Since there are 2n distinct addresses in a ROM, there are 2n
distinct words which are said to be stored in the device and an output word can be selected by
a unique address. The address value applied to the input lines specifies the word at output
lines at any given time. A ROM is characterized by the number of words 2n and number of
bits per word m and denoted as 2n × m ROM.
 For example a 32 × 8 ROM contains 32 words of 8 bits each. This means there are
eight output lines and there are 32 numbers of distinct words stored in that unit, each of
which is applied to the output lines. The particular word selected from the presently available
output lines is determined by five input variables, as there are five input lines for a 32 × 8
ROM, because 25 = 32. Five input variables can specify 32 addresses or min-terms and for
each address input there is a unique selected word. Thus, if the input address is 0000, word
number 0 is selected. For address 0001, word number 1 is selected and so on.

A ROM is sometimes specified by the total number of bits it contains, which is 2 n ×

m. For example, a 4,096-bit ROM may be organized as 512 words of 8 bits each. That means
the device has 9 input lines (29 × m = 512) and 8 output lines.
In Figure below, the block consisting of an AND array with buffers or inverters is
equivalent to a decoder. The decoder basically is a combinational circuit that generates 2n
numbers of minterms from n number of input lines. 2n or p numbers of minterms are realized
from n number of input variables with the help of n numbers of buffers, n numbers of
inverters, and 2n numbers of AND gates.
 Each of the minterms is applied to the inputs of m number of OR gates through fusible
links. Thus, m numbers of output functions can be produced after blowing of some selected
fuses. The equivalent logic diagram of a 2n×m ROM is shown below

ROM has many important applications in the design of digital computer systems. Realization
of complex combinational circuits, code conversions, generating bit patterns, performing
arithmetic functions like multipliers, forming look-up tables for arithmetic functions, and bit
patterns for characters are some of its applications. They are particularly useful for the
realization of multiple output combinational circuits with the same set of inputs. As such,
they are used to store fixed bit patterns that represent the sequence of control variables
needed to enable the various operations in the system. They are also used in association with
microprocessors and microcontrollers.

PROGRAMMABLE LOGIC DEVICE-(PLD): The logic devices other than TTL ,CMOS
families whose logical operation is specified by the user through a process called
programming are called Programmable Logic Devices. So, the programmable logic device
is the IC that contain digital logic cells and programmable interconnect . The idea of PLD
was first conceived by Ron Cline from Signetics in 1975 with programmable AND and
OR planes. The basic idea with these devices is to enable the designer to configure the logic
cells and interconnect to form a digital electronic circuit within a single IC package. Here, the
hardware resources will be configured to implement a required functionality. By changing the
hardware configuration, the PLD will operate a different function. The functioning and basic
working principle of PLD is explained below through the diagrams.
There are three types of PLD available. The simple programmable logic device (SPLD), the
Complex programmable logic device(CPLD), and the Field programmable gate array
(FPGA).

Device Type AND Array OR Array

ROM Fixed Programmable
PLA Programmable Programmable
PAL Programmable Fixed

Simple Programmable Logic Device (SPLD)

The PLD with simple architectural features can be called as SPLD or Simple
programmable Logic Device. The SPLD was introduced prior to the CPLD and FPGA.
Based on the architecture the SPLDs are classified into three types. Programmable logic array
(PLA), Programmable array of logic (PAL), and Generic Array of Logic (GAL).

PLA-Programmable Logic Array

PLA, Programmable Logic Array is a type of LSI device and conceptually similar to
a ROM. However, a PLA does not contain all AND gates to form the decoder or does not
generate all the minterms like ROM. In the PLA, the decoder is replaced by a group of AND
gates with buffers/inverters, each of which can be programmed to generate some product
terms of input variable combinations that are essential to realize the output functions. The
AND and OR gates inside the PLA are initially fabricated with the fusible links among them.
The required Boolean functions are implemented in sum of the products form by opening the
appropriate links and retaining the desired connections.

So, the PLA consists of two programmable planes AND and OR planes . The AND
plane consists of programmable interconnect along with AND gates. The OR plane consists
of programmable interconnect along with OR gates. In this view, there are four inputs to the
PLA and four outputs from the PLA. Each of the inputs can be connected to an AND gate
with any of the other inputs by connecting the crossover point of the vertical and horizontal
interconnect lines in the AND gate programmable interconnect. Initially, the crossover points
are not electrically connected, but configuring the PLA will connect particular cross over
points together. In this view, the AND gate is seen with a single line to the input. This view is
by convention, but this also means that any of the inputs (vertical lines) can be connected.
Hence, for four PLA inputs, the AND gate also has four inputs. The single output from each
of the AND gates is applied to an OR gate programmable inter connect.
 Again, the crossover points are initially not electrically connected, but configuring the
PLA will connect particular crossover points together. In this view, the OR gate is seen with a
single line to the input. This view is by convention, but this also means that any of AND gate
outputs can be connected to the OR gate inputs. Hence, for four AND gates, the OR gate also
has four inputs
 Therefore, the function is implemented in either AND-OR form when the output link
across INVERTER is in place, or in AND-OR-INVERT form when the link is blown off. The
general structure of a PLA with internal connections is shown in figure below.

The size of a PLA is specified by the number of inputs, the number of product
terms,and the number of outputs. The number of sum terms is equal to the number of outputs.
The PLA described in figure above is specified as n × p × m PLA. The number of
programmable links is 2n × p + p × m + m, whereas that of ROM is 2n × m. A typical PLA of
16 × 48 × 8 has 16 input variables, 48 product terms, and 8 output lines.
To implement the same combinational circuit, a 216 × 8 ROM is needed, which
consists of 216 = 65536 minterms or product terms. So there is a drastic reduction in number
of AND gates within the PAL chip, thus reducing the fabrication time and cost.
PROGRAMMABLE ARRAY LOGIC (PAL) :
The first programmable device was the programmable array logic (PAL) developed
by Monolithic Memories Inc(MMI). The Programmable Array Logic or PAL is similar to
PLA, but in a PAL device only AND gates are programmable. The OR array is fixed by the
manufacturer. This makes PAL devices easier to program and less expensive than PLA. On
the other hand, since the OR array is fixed, it is less flexible than a PLA device.

The PAL device. has n input lines which are fed to buffers/inverters.
Buffers/inverters are connected to inputs of AND gates through programmable links. Outputs
of AND gates are then fed to the OR array with fixed connections. It should be noted that, all
the outputs of an AND array are not connected to an OR array. In contrast to that, only some
of the AND outputs are connected to an OR array which is at the manufacturer's discretion.
This can be clarified by above, which illustrates the internal connection of a four-input, eight
AND-gates and three-output PAL device before programming. Note that while every
buffer/inverter is connected to AND gates through links, F1-related OR gates are connected
to only three AND outputs, F2 with three AND gates, and F3 with two AND gates. So this
particular device can generate only eight product terms, out of which two of the three OR
gates may have three product terms each and the rest of the OR gates will have only two
product terms. Therefore, while designing with PAL, particular attention is to be given to the
fixed OR array.
GAL-Generic Array Logic

PAL and PLA devices are one-time programmable (OTP) based on PROM, so the
PAL or PLA configuration cannot be changed after it has been configured. This limitation
means that the configured device would have to be discarded and a new device configured.
The GAL, although similar to the PAL architecture, uses EEPROM and can be reconfigured.
The Generic Array Logic (GAL) device was invented by Lattice Semiconductor. The GAL
was an improvement on the PAL because one device was able to take the place of many PAL
devices or could even have functionality not covered by the original range. Its primary
benefit, however, was that it was erasable and re-programmable making prototyping and
design changes easier for engineers. The GAL is very useful in the prototyping stage of a
design, when any bugs in the logic can be corrected by reprogramming.
Complex Programmable Logic Device (CPLD):
CPLDs were pioneered by Altera, first in their family of chips called Classic EPLDs,
and then in three additional series, called MAX 5000, MAX 7000 and MAX 9000. The
CPLD is the complex programmable Logic Device which is more complex than the SPLD.
This is build on SPLD architecture and creates a much larger design. Consequently, the
SPLD can be used to integrate the functions of a number of discrete digital ICs into a single
device and the CPLD can be used to integrate the functions of a number of SPLDs into a
single device.
So, the CPLD architecture is based on a small number of logic blocks and a global
programmable interconnect. Instead of relying on a programming unit to configure chip , it is
advantageous to be able to perform the programming while the chip is still attached to its
circuit board. This method of programming is known is called In-System programming
(ISP). It is not usually provided for PLAs (or) PALs , but it is available for the more
sophisticated chips known as Complex programmable logic device.
 The CPLD consists of a number of logic blocks or functional blocks, each of
which contains a macrocell and either a PLA or PAL circuit arrangement. In this view, eight
logic blocks are shown. The building block of the CPLD is the macro-cell, which contains
logic implementing disjunctive normal form expressions and more specialized logic
operations. The macro cell provides additional circuitry to accommodate registered or
nonregistered outputs, along with signal polarity control. Polarity control provides an output
that is a true signal or a complement of the true signal. The actual number of logic blocks
within a CPLD varies; the more logic blocks available, the larger the design that can be
configured.

In the center of the design is a global programmable interconnect. This interconnect

allows connections to the logic block macrocells and the I/O cell arrays (the digital I/O cells
of the CPLD connecting to the pins of the CPLD package).The programmable interconnect is
usually based on either array-based interconnect or multiplexer-based interconnect:• Array-
based interconnect allows any signal within the programmable interconnect to connect to any
logic block within the CPLD.
 This is achieved by allowing horizontal and vertical routing within the programmable
interconnect and allowing the crossover points to be connected or unconnected (the same idea
as with the PLA and PAL), depending on the CPLD configuration.
• Multiplexer-based interconnect uses digital multiplexers connected to each of the macrocell
inputs within the logic blocks. Specific signals within the programmable interconnect are
connected to specific inputs of the multiplexers. It would not be practical to connect all
internal signals within the programmable interconnect to the inputs of all multiplexers due to
size and speed of operation considerations.

FPGAs – FIELD PROGRAMMABLE GATE ARRAYS

The FPGA concept emerged in 1985 with the XC2064TM FPGA family from Xilinx
. The ―FPGA is an integrated circuit that contains many (64 to over 10,000) identical logic
cells that can be viewed as standard components.‖ The individual cells are interconnected by
a matrix of wires and programmable switches. A user's design is implemented by specifying
the simple logic function for each cell and selectively closing the switches in the interconnect
matrix. The array of logic cells and interconnect form a fabric of basic building blocks for
logic circuits. Complex designs are created by combining these basic blocks to create the
desired circuit.

Unlike CPLDs (Complex Programmable Logic Devices) FPGAs contain neither AND
nor OR planes.The FPGA architecture consists of configurable logic blocks, configurable
I/O blocks, and programmable interconnect. Also, there will be clock circuitry for driving
the clock signals to each logic block, and additional logic resources such as ALUs, memory,
and decoders may be available. The two basic types of programmable elements for an FPGA
are Static RAM and anti-fuses.
Each logic block in an FPGA has a small number of inputs and one output. A
look up table (LUT) is the most commonly used type of logic block used within FPGAs.
There are two types of FPGAs.(i) SRAM based FPGAs and (ii) Antifuse technology
based(OTP)

Every FPGA consists of the following elements

 Configurable logic blocks(CLBs)

 Configurable input output blocks(IOBs)
 Two layer metal network of vertical and horizontal lines for interconnecting the
CLBS
Configurable logic blocks(CLBs):
The configurable logic block is the basic logic cell and it is either RAM based
or PLD based . It consists of registers (memory), Muxes and combinatorial functional unit.
An array of CLBS are embedded within a set of vertical and horizontal channels that contain
routing which can be personalized to interconnect CLBs.
Configurable Input / Output logic locks (IOBs):
CLBs and routing channels are surrounded by a set of programmable I/Os which
is an arrangement of transistors for configurable I/O drivers.
Programmable interconnects:
These are un programmed interconnection resources on the chip which have
channeled routing with fuse links. Four types of interconnect architectures are available. They
are
 Row-Column Architecture
 Island Style Architecture
 Sea-of-Gates Architecture

Advantages of FPGAs:

 Design cycle is significantly reduced. A user can program an FPGA design in a few
minutes or seconds rather than weeks or months required for mask programmed parts.
 High gate density i.e, it offers large gate counts.
 No custom masks tooling is required (Low cost).
 Low risk and highly flexible.
 Reprogram ability for some FPGAs (design can be altered easily).
 Suitable for prototyping.
  Parallelism
Allows for system-level extraction of parallelism to match input data
at design time
 Huge computational capability
 Fast development and Dynamic reconfiguration
 Updating new pattern matching rules (or simply rules)
 Device should not stop when updating new rules
 Update time for new rules
 To provide fast response to new attacks, the compilation and updating
time for new rules needs to be short

 In case of a hardwired FPGA architecture, the update time is mostly

dependent on place & route time
 Memory-based units can provide near instantaneous updates
Limitations:

 Speed is comparatively less.

 The circuit delay depends on the performance of the design implementation tools.
 The mapping of the logic design into FPGA architecture requires sophisticated design
implementation (CAD) tools than PLDs.
FPGA Programming Technologies:
(a) Antifuse Technology:
An antifuse is a two terminal device that when un-programmed has a very high
resistance between the two terminals and when programmed, or ―blown‖, creates a very low
resistance or permanent connection. The application of a high voltage from 11 V to 21 V will
create the low resistive permanent connection. Antifuse technologies come in two types. The
first is oxide-nitride-oxide (ONO) dielectric based and the other is amorphous silicon or
metal-to-metal antifuse structures.
Dielectric based antifuses consist of a dielectric material between N+ diffusion and
polysilicon which breaks down when a high voltage is applied. Early dielectrics were a
single-layered oxide dielectric until Actel came out with the programmable low impedance
circuit element (PLICE), which is a multi-layer oxide-nitride-oxide (ONO) dielectric fuse. A
high voltage across the PLICE melts the dielectric and creates polycrystalline silicon between
the terminals. When the PLICE is blown, it adds three layers rather than the double metal
CMOS process. The layers are a thin layer of oxide an top off the N+ surface, Low-pressure
Chemical Vapor Deposition (LPCVD) nitride and the reoxidized top oxide. The
programming current has an important effect because the higher the current during
programming, the lower the link resistance, resulting in smaller thickness for the antifuse
material. Programming circuits for antifuses need to supply high currents (15 ma for Actel) to
insure high reliability and performance.
Amorphous silicon antifuse technology is the alternative to dielectric antifuse. It
consists of amorphous silicon between two layers of metal that changes phases when current
is applied. When the antifuse is not programmed the amorphous silicon has a resistance of 1
Giga ohm. When a high current (about 20 mA) is applied to the anitfuse the amorphous
silicon changes into a conductive polysilicon link. Quick Logic pASIC FPGA is a perfect
example of an amorphous silicon antifuse technology.
(b). SRAM-based Technology:
SRAM FPGA architecture consists of static RAM cells to control pass gates or
multiplexers. The FPGA speed is determined by the delay introduced by the logic cells and
the routing channels. Multiplexers, look-up tables and output drivers affect the speed of
signals through the logic cells. An FPGA with more PIPs is easier to route but introducing
more routing delay. The size of the look-up table plays an important role depending on the
design. Smaller LUTs provide higher density but larger ones are preferred for high-speed
applications.
Distinguish between SRAM and Antifuse Technologies: The following points explains
the differences between the two technologies.
1. Antifuse programming technology is faster than SRAM programming technology due to
the RC delays introduced by the interconnect structure.
2. Antifuse technology has more silicon area per gate and is easier to route than SRAM
technology.
3. A disadvantage of antifuse FPGA is that they require more process layers and mask steps
and also contain high voltage programming transistors.
4. SRAM-based technology contains higher capacity than antifuse technologies.
5. SRAM based technology is very flexible with in-system programmability and the ability to
reconfigure the design during the debugging stage while antifuse technology is one-time
programmable (OTP). This ability reduces design and development, which reduces
overall cost of the design. Another advantage to this is that SRAM technology can be
programmed at the factory through complete verification test where the antifuse are tested
as ―blanks‖ and require programming by the user to verify design requirements and
operation.
6. A disadvantage of SRAM technology is that it is volatile meaning it has to be
reprogrammed every time power is turned off and on again. The SRAM usually require
an extra memory element to program the chip which occupies board space .
Altera’s FLEX 10K Series CPLDs
Altera‘s FLEX 10K devices are the industry‘s first embedded PLDs. Based on
reconfigurable CMOS SRAM elements, the Flexible Logic Element MatriX (FLEX)
architecture incorporates all features necessary to implement common gate array mega
functions. With 10,000 to 250,000 typical gates ,the FLEX 10K family provides the density,
speed, and features to integrate entire systems, including multiple 32-bit buses, into a single
device.
FLEX 10K devices are reconfigurable .So, the designer is not required to generate test
vectors for fault coverage purposes. Additionally, the designer need not manage inventories
of different ASIC designs; FLEX 10K devices can be configured on the board for the specific
functionality required.
Each FLEX 10K device contains an Embedded Array (EA) and a Logic Array (LA).
The Embedded Array is used to implement a variety of memory functions or complex logic
functions, such as digital signal processing (DSP) ,microcontroller, wide-data-path
manipulation, and data-transformation functions.
 The Logic Array performs the same function as the sea-of-gates in the gate array: it is
used to implement general logic, such as counters, adders, state machines, and multiplexers.
The combination of embedded and logic arrays provides the high performance and high
density of embedded gate arrays, enabling designers to implement an entire system on a
single device.
FLEX 10K devices are configured at system power-up with data stored in an Altera
serial configuration device or provided by a system controller.
Logic Element is , the smallest unit of logic in the FLEX 10K architecture, has a
compact size that provides efficient logic utilization. Each LE contains a four-input LUT,
which is a function generator that can quickly compute any function of four variables. In
addition, each LE contains a programmable flip flop with a synchronous enable, a carry
chain, and a cascade chain. Each LE drives both the local and the Fast Track. The
programmable flip flop in the LE can be configured for D, T, JK, or SR operation. The clock,
clear, and preset control signals on the flip flop can be driven by global signals, general-
purpose I/O pins, or any internal logic. For combinatorial functions, the flip flop is bypassed
and the output of the LUT drives the output of the LE.
The carry chain provides a very fast (as low as 0.2 ns) carry-forward function between
Les. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the
carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature
allows the FLEX 10K architecture to implement high-speed counters, adders, and
comparators of arbitrary width efficiently. Cascade Chain in the FLEX 10K architecture can
implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute
portions of the function in parallel; the cascade chain serially connects the intermediate
values. The cascade chain can use a logical AND or logical OR (via De Morgan‘s inversion)
to connect the outputs of adjacent Les. Each additional LE provides four more inputs to the
effective width of a function, with a delay as low as 0.7 ns per LE. Cascade chain logic can
be created automatically by the Compiler during design processing, or manually by the
designer during design entry.
Altera offers the EPC1, EPC2, EPC16, and EPC1441 configuration devices, which
configure FLEX 10K devices via a serial data stream. Configuration data can also be
downloaded from system RAM or from Altera‘s Bit Blaster serial download cable or Byte
Blaster MV parallel port download cable. Even after configuring a FLEX 10K device , it can
be reconfigured in-circuit by resetting the device and loading new data .Because
reconfiguration requires less than 320 ms, real-time changes can be made during system
operation. FLEX 10K devices contain an optimized interface that permits microprocessors to
configure FLEX 10K devices serially or in parallel, and synchronously or asynchronously.
The interface also enables microprocessors to treat a FLEX 10K device as memory and
configure the device by writing to a virtual memory location, making it very easy for the
designer to reconfigure the device.

SPEED PERFORMANCE :
The speed performance of PLDs is affected by their architectural features like I/O
blocks, Logic Elements and the Interconnects. The routing of these elements also paly an important
role.For example if a finite state machine is to be implemented in an FPGA, then the amount
of logic feeding each state machine flip-flop must be minimized. This follows because in
FPGAs flip-flops are directly fed by logic blocks that have relatively few inputs (typically 4 -
8). If the state machine flip-flops are fed by more logic than will fit into a single logic block,
then multiple levels of logic blocks will be needed, and speed-performance will decrease.
Even in a CPLD architecture, speed-performance of a state machine can be significantly
affected by state bit encoding,for example, in the Altera MAX 7000 CPLDs, flip-flops that are fed
by five or fewer product terms will operate faster than those that require more than five terms.
CPLDS are ideal for high-speed applications requiring critical timing and FPGAs are
more flexible with the finer-grained architecture. Lattice semiconductor CPLD series
architecture offered predictable timing, high densities, in-system programmability, flexible
architecture for mixed combinatorial and register intensive designs and system partitioning.
Some applications can not use CPLDs. Planetary Spacecraft and earth orbiting satellites and
science instruments require Radiation Hardened PLDs. Between CPLD and FPGAs ,the
CPLDs are fast and , predictable but the FPGAs are application dependent. The CPLD
implementation of the sequential circuit is much faster than the FPGA version. However, the
most interesting aspect is the difference between the 5 -bit and13-bit versions of the circuit.
If both versions are operated at 100 MHz for CPLD implementation, while the 13-bit
version is much slower than its smaller counterpart for the FPGA. This is a good example of
how FPGAs are not suitable for implementing circuits that require ―wide‖ logic gates (the 14-
inputAND-gates for this example), whereas CPLDs can easily implement such applications.

It is widely accepted by designers who use PLDs that FPGAs are the best choice for
data-path circuits, because wide logic gates are not required and the number of flip-flops
needed is large. But it is true that the FPGAs cannot provide required performance in an
FPGA, and the CPLDs were successful . The reason that the CPLDs provided better
performance is to do with their simple structure that provides for very high-speed paths from
input pins, through AND-OR logic and flip-flops, to output pins.
STANDARD CELLS:

A standard cell based design requires development of a full custom mask set. The
standard cell is also known as the polycell. In this approach, all of the commonly used
logic cells are developed, characterized and stored in a standard cell library. A library
may contain a few hundred cells including inverters, NAND gates, NOR gates, complex
AOI, OAI gates, D-latches and Flip-flops. Each gate type can be implemented in several
versions to provide adequate driving capability for different fan-outs. The inverter gate can
have standard size, double size, and quadruple size so that the chip designer can select
the proper size to obtain high circuit speed and layout density. Each cell is
characterized according to several different characterization categories, such as,
Delay time versus load capacitance
 Circuit simulation mode
 Timing simulation model
 Fault simulation model
 Cell data for place-and-route
 Mask data

For automated placement of the cells and routing, each cell layout is designed with a
fixed height, so that a number of cells can be bounded side-by-side to form rows. The power
and ground rails run parallel to the upper and lower boundaries of the cell. So that,
neighboring cells share a common power bus and a common ground bus. The figure shown
below is a floorplan for standard-cell based design.

It is also found experimentally that the CPLD-based counters achieve the maximum
possible speed of tpd plus the setup time of the flip-flop. This is because each counter bit
needs up to 34-input AND functions that feed 4-input OR-gates .In the FLEX devices, high-
speed carry chain is employed to implement the required wide AND. It is the speed of this
carry chain that limits the speed-performance of the FLEX-based counter. Roughly, a counter
of double the size has twice the carry chain length and thus half the speed performance. So ,
the conclusion is Altera CPLDs can implement very fast counters, however, it is difficult to
construct many large counters in one device. The FLEX FPGAs are better suited for this purpose, but
performance and routability are compromised when the carry chain hardware is used. Both
performance and routability can be improved by enhancing the counter design with a very a small
cost in area. However, these gains cannot be realized without intimate knowledge of the FPGA
architecture.
TESTING:
Need of Testing:
The increasing capability of being able to fabricate a very large number of transistors
on a single integrated-circuit chip and the complexity of the possible systems has increased
the importance of being able to test such circuits in an acceptable way and in an acceptable
time. The time difficulties of tests are primarily due to the limited number of input/output
connections on a chip which is the only means of access to the circuit, the ratio of the number
of gates on a chip to the number of accessible I/Os increasing with chip size.
Fault Simulation:
 To evaluate the quality of a test set - usually in terms of fault coverage
 To incorporate into ATPG for test generation - due to its lower complexity
 To construct fault dictionary - for post-test diagnosis

Characteristics of Fault Simulation

 Fault activity with respect to fault-free circuit is often sparse both in time and in
space.
 For example, F1 is not activated by the given pattern, while F2 affects only the lower
part of this circuit.

 The

efficiency of a fault simulator depends on its ability to exploit these characteristics.

Parallel Fault Simulation

 Taking advantage of inherent parallel operation of computer words to simulate
faulty circuits in parallel with fault-free circuit – the number of faulty circuits,
or faults, can be processed parallelly is limited by the word length.
 Straightforward and memory efficient
 Some weaknesses: – An event, a value change, of a single fault or fault-free
circuit leads to the computation of the entire word. – The fault-free logic
simulation is repeated for the number of passes.
Example of Parallel Fault Simulation
 STUCK AT FAULTS:
 Stuck at faults occur when a line is permanently stuck to Vdd or ground giving a
faulty output. This line may be an input or output to any gate. Also this fault can be
single or multiple stuck at faults.
 When a signal, or gate output, is stuck at a 0 or 1 value, independent of the inputs to
the circuit, the signal is said to be ―stuck at‖ and the fault model used to describe this
type error is called a ―stuck at fault model‖.
 A fault model is an engineering model of something that could go wrong in the
construction or operation of a piece of equipment. From the model, the designer or
user can then predict the consequences of this particular fault.
 Basic fault models in digital circuits include the stuck-at fault model, the bridging
fault model, the transistor faults, the open fault model, the delay fault model, etc. In
the past several decades, the most popular fault model used in practice is the single
stuck-at fault model.
 To use this fault model, each input pin on each gate in turn, is assumed to be
grounded, and a test vector is developed to indicate the circuit is faulty. Hence, if a
circuit has n signal lines, there are potentially 2n stuck-at faults defined on the circuit.
 The test vector is a collection of bits to apply to the circuit's inputs, and a collection of
bits expected at the circuit's output. If the gate pin under consideration is grounded,
and this test vector is applied to the circuit, at least one of the output bits will not
agree with the corresponding output bit in the test vector.
  After obtaining the test vectors for grounded pins, each pin is connected in turn to a
logic one and another set of test vectors is used to find faults occurring under these
conditions. Each of these faults is called a single stuck-at-0 or a singlestuck-at-1 fault,
respectively.
 The stuck-at fault model is a logical fault model because no delay information is
associated with the fault definition.
 It is also called a permanent fault model because the faulty effect is assumed to be
permanent, in contrast to intermittent faults which occur (seemingly) at random and
transientfaults which occur sporadically, perhaps depending on operating conditions
like temperature, power supply voltage or on the data values (high or low voltage
states) on surrounding signal lines. The single stuck-at fault model is structural
because it is defined based on a structural gate-level circuit model.
 A pattern set with 100% stuck-at fault coverage consists of tests to detect every
possible stuck-at fault in a circuit. 100% stuck-at fault coverage does not necessarily
guarantee high quality, since faults of many other kinds—such as bridging faults,
opens faults, and transition or delay faults—often occur

TEST PRINCIPLES:

The VLSI Testing Process

 Verification testing, characterization testing and design debug:
 Verifies correctness of design and test procedure.
 More common to correct design than test procedure.

 Manufacturing testing:
 Factory testing of all manufactured chips for parametric faults and for random
 defects.

 Acceptance testing (incoming inspection):

 Customer performs tests on purchased parts to ensure quality.

Testing Principle

 When the chip is digital, the stimuli are called test patterns or test vectors .

 Automatic test equipment (ATE) carries out this process.

o A powerful computer operating under the control of a test program, a
program written in a high level language .
o Digital signal processor (DSP) used for analog testing.

 Chips are automatically fed to the tester through the wafer handler system.
o A probe card or membrane probe contacts pads of bare or packaged chip.

BILBO TESTING:

The BILBO is an embedded and off-line BIST architecture because it uses existing
flip-flops from the CUT to construct the TPG and ORA functions [139]. The basic idea is to
partition the CUT into groups of flip-flops and groups of combinational logic. Each group of
flip-flops is augmented with additional logic to provide multiple modes of operation. When
the BILBO functions as a TPG, it provides pseudo-random test patterns by operating as an
LFSR. When the BILBO functions as an ORA, it performs multiple-input signature analysis
by operating as a MISR [138]. The application of BILBO to a CUT in its simplest form is
illustrated in Figure 7.1, where the flip-flops at the primary inputs and outputs are used to
construct two BILBOs. The BILBO at the primary inputs generates pseudo-random test
patterns as a TPG and the BILBO at the primary outputs operates as a MISR-based ORA. As
a result, the BILBO is a test-per-clock BIST approach since a new test pattern is applied to
the
CUT
and a
new
output response is compacted during each clock cycle of the BIST sequence.
The additional gates added to the existing flip-flops to create the BILBO (as it was
originally proposed) are illustrated in Figure 7.2 for a 4-bit BILBO implementation. For each
flip-flop, one exclusive-OR gate, one AND gate, and one NOR gate are added [138]. For
each BILBO, one multiplexer, one inverter, and one or more exclusive- OR gates (needed to
construct a primitive characteristic polynomial) are added. Note that in Figure 7.2, the LFSR
mode of operation uses an external feedback implementation for the characteristic
polynomial,

CHIP LEVEL TEST TECHNIQUES:

Testability is the property of a circuit that makes it easy to test. The testability is
highly dependent on testing. Consider the example in which design engineer considers
complexity of test vector generation to test the circuit. Now the test engineer, testability is
compatibility of design with test equipment. Quality engineers relates testability to fault
coverage. By increasing the testability of a circuit, some function of the costs is reduced. For
example, scan designs lower the cost of test generation and increase the number of I/O pins,
area, and test time. Testability is a design characteristic due to which various costs associated
with testing and the cost-effective development of the tests to determine the status.
Testing can be accomplished on any circuitry from transistors, gates, macrocells,
cores, chips, boards, and systems. Design for Testability is adding logic to enhance the
testability of a design. Design for Testability is defined by adding features to enhance ability
to achieve quality metrics for,

1. To easily generate
vectors
2. To reduce the time
in vector generation
3. To reduce the cost
of vectors.
FAULT COVERAGE:
Fault Coverage :
A parameter used in quality assessment of digital circuits is fault coverage. Fault
coverage is related to another term known as fault grading. The measurement of fault
coverage is done with reference to a set of test vectors. The vectors detect number of faults
out of all possible faults in the design. The mathematical equation for fault coverage is,

(Total Detected Faults) / (Total Fault Population)

However different tools report different fault coverage numbers. The absolute total
number of faults in the design is not used as the denominator of the measurement process.
The error in fault coverage occurs when different tools identify faults differently. Tools
classify stuck-at 1‘s and 0‘s on gate inputs and outputs as faults, whereas other tools classify
stuck-at 1‘s and 0‘s on gate inputs, gate outputs, and the interconnecting wire nets as faults.
The way in which the fault coverage is calculated is as follows,

1. Each circuit node is taken in sequence and held to 0 and circuit is simulated,
2. When a discrepancy is detected between the ―faulty machine‖ and the good machine,
the faulty is marked as detected and the stimulation is stopped.
3. This is repeated for setting the node to 1. In turn, every node is stuck at 1 and 0.