Dataflow Modeling

//OR gate, NAND gate, NOR gate, XOR gate

Module gates(

Input a,

Input b,

Output y,

Output x,

Output z,

Output w,

);

Assign y=a|b;

Assign x=~(a&b);

Assign w=~( a|b);

Assign z=a^b;

Endmodule

//Half adder

Module halfadder(

Input a,

Input b,

Output s,

Output c,

);
Assign s=a^b;

Assign c=a&b;

endmodule

//Full Adder

Module fulladder(

Input a,

Input b,

Input ci,

Output s,

Output co,

);

Assign s= a^b^ci;

Assign co=(a&b)|(b&ci) |(ci&a);

Endmodule

//2:1 mux

Module 21mux(

Input s;

Input a;

Input b;

Output z,

);

Assign z=((~s)&a) |(s&b) ;

//4 bit Carry look ahead adder

module 4bitclaaddr(

output [3:0]s,

output cout,PG,GG,

input [3:0]a,b,

input cin

);

Wire[3:0]G,P,C;

Assign G=a&b;

Assign P=a^b;

Assign C[0]=cin;

Assign C[1]=G[0] |(P[0]&C[0]);

Assign C[2]=G[1] |(P[1]&G[0])|(P[1]&P[0]&C[0]);

Assign C[3]=G[2] |(P[2]&G[1])|(P[2]&P[1]&G[0]) | (P[2]&P[1]&P[0]&C[0]);

Assign cout=G[3] |(P[3]&G[2])|(P[3]&P[2]&G[1]) | (P[3]&P[2]&P[1]&G[0]) |

(P[3]&P[2]&P[1]&P[0]&C[0]);

Assign s=P^C;

Assign PG= P[3]&P[2]&P[1]&P[0];

Assign GG= G[3] |(P[3]&G[2])|(P[3]&P[2]&G[1]) | (P[3]&P[2]&P[1]&G[0]);

Endmodule
//Encoder 8:3

module encoder83df(din, a, b, c);

input [0:7] din;

output a;

output b;

output c;

assign a=din[4] | din[5] | din[6] | din[7];

assign b=din[2] | din[3] | din[6] | din[7];

assign c=din[2] | din[4] | din[6] | din[7];

endmodule

//4:1 mux

module mux41data (din,s,y);

input [0:3] din;

input[0:1]s;

output out;

assign out=din[s];

endmodule
Behavioral modeling
//2:1 mux using if else

module mux2x1_bh(A,B,select,OUT);

input A,B,select;

output reg OUT;

always @ (select or A or B)

if (select == 1)

OUT = A;

else

OUT = B;

endmodule

//3:8decoder

module Decoder3x8 (

input [2:0] A, output reg [7:0] D);

always @(A)

begin

if (A == 0)

D = 8'b00000001;

else if (A == 1)

D = 8'b00000010;

else if (A == 2)

D = 8'b00000100;
else if (A == 3)

D = 8'b00001000;

else if (A == 4)

D = 8'b00010000;

else if (A == 5)

D = 8'b00100000;

else if (A == 6)

D = 8'b01000000;

else D = 8'b10000000;

end

endmodule

//halfadder

Module halfaddr_bh(a,b,s,c);

Input a;

Input b;

Output reg s;

Output reg c;

Always@(a,b)

Begin

s= a^b;

c=a&b;

end

endmodule
//full adder

Module fulladerbh(

Input a,

Input b,

Input ci,

Output reg s,

Output reg co

);

always@(a,b,cin)

begin

s=a^b^cin;

c=(a&b)|(b&c) |(cin&a);

end

endmodule

//4:1 mux

Module mux41_bh(

Input a,

Input b,

Input s1,

Input s2,

Output reg y,

Input d,
 Input c

);

Always@(a,b,c,d,s1,s2)

Begin

If(s1)

begin

if(s0)

out=i3;

else

out=i2;

end

else

begin

if(s0)

out=i1;

else

out=i0;

end

end

endmodule
// JK Flipflop using case statement

Module jkflipflop(J,K,clk,Q);

Input J;

Input K;

input clk,

output reg Q,

always@(posedge clk)

begin

case({J,K})

2’b0_0:Q<=Q;

2’b0_1:Q<=1’b0;

2’b1_0:Q<=1’b1;

2’b1_1:Q<=~Q;

endcase

end

endmodule

//4:1 mux using case statement

Module muxcase(

Input s0,s1,

Input i1,

Input i2,

Input i3,

Input i4,
Output reg out

);

Always@(*)

Begin

Case({s0,s1})

2’b0_0:out<=i0;

2’b0_1:out<=i1;

2’b1_0:out<=i2;

2’b1_1:out<=i3;

Endcase

End

endmodule

//8 bit booth multiplier

module BoothMulti(X, Y, Z);

input signed [7:0] X, Y;

output signed [31:0] Z;

reg signed [31:0] Z;

reg [1:0] temp;

integer i;

reg E1;

reg [7:0] Y1;

always @ (X, Y)

begin
 Z = 31'd0;

E1 = 1'd0;

for (i = 0; i < 4; i = i + 1)

begin

temp = {X[i], E1};

Y1 = - Y;

case (temp)

2'd2 : Z [31 : 15] = Z [31 : 15] + Y1;

2'd1 : Z [31: 15] = Z [31 : 15] + Y;

default : begin end

endcase

Z = Z >> 1;

Z[31] = Z[30];

E1 = X[i];

end

if (Y == 16'd32)

begin

Z = - Z;

end

end

endmodule

//trailing zeros

Module zeros(

Input[7:0]data,
Output reg[3:0]out

);

Integer i;

always@(data)

begin

out=0;

i=0;

while(data[i]==0&&i<=7)

begin

out=out+1;

i=i+1;

end

end

endmodule

//no. of zeros in 8 bit no

Input[7:0]data,

Output reg[3:0]out

);

Integer i;

always@(data)

begin

out=0;

for(i=0;i<7;i++)

begin
if(data[i]==1)

begin

out=out+1;

end

end

end

endmodule

//counter

Module counter(

Input clk,

Input clr,

Output reg[2:0]out

);

Integer a;

Integer b;

Integer c;

always@(clk,clr)

begin

if(vlk)

begin

if(clr)

begin

out==000;
end

else

begin

case({a,b,c})

3’b0_0_0:out=001;

3’b0_0_1:out=010;

3’b0_1_0:out=011;

Endcase

End

End

End

Endmodule

//SRAM

Module jvb(data_in,data_out,ABUS,CS,R_WRbar);

Input [7:0]data_in;

Output [7:0]data_out;

Input CS;

Input [3:0]ABUS;

Input R_WRbar;

Reg[7:0]data_out;

Reg[7:0]memory[0:15];

always@( data_in, ABUS,CS,R_WRbar)

begin

if(CS==1’b1)
begin

if(R_WRbar==1’b0)

begin

memory[ABUS]==data_in;

end

else

begin

data_out=memory[ABUS];

end

else

data_out=8,bzzzzzzzz;

end

endmodule

// D, S ,R ,T flipflop

module sscdt(
input D,
input S,
input R,

input T,
output reg Q1,
output reg Q2,
output reg Q3,

);
always@( D, S ,R ,T)
begin
case({D})
 1’b0 : Q1<=1’b0;
1’b1 : Q1<=1’b1;
endcase

case({S,R})
2’b00 : Q2<=Q2;
2’b00 : Q2<=1’b0;
2,b10 : Q2<=1’b1;

2’b11 : Q2<=1’b2;
endcase
case ({T}
1’b0 : Q3<=Q3;

1’b1 : Q3<=~Q3;
Endcase
End
endmodule

// BCD UP/DOWN counter U/D module ud(

Output reg J1,

);
Always@(UD, QA, QB)
begin
J1=ud˄QB;

J2=1’B1;
 K1=ud˄QB;
K2=1’b1;
End

Endmodule
// module fact(
Input n,
Output reg fact

);
always@(n)
begin
integer i;

fact = 1;
if(n)
begin
fact=1;
end

else
begin
for(i=0;i<=n;i=i+1)
begin

fact=fact*i;
end
end
end
//4 bit asynchronous counter
Module acounter(clk,count);
Input clk;

Output[3:0] count;
Reg[3:0]count;
Wire clk;
Initial

Coutt=4’b0;
always@(negedge clk)
count[0]<= ~count[0];
always@(negedge count[0])

coumt[1]<= ~count[1]
always@(negedge count[1])
count[2]<= ~count[2];
always@(negedge count[2])
count[3]<= ~count[3];

endmodule

STRUCTURAL MODELLING
//RIPPLE CARRY ADDER

module halfadder(
output s,c;
input a,b
);
XOR(s,a,b);

AND(c,a,b);
 endmodule
module fulladder(
output s,cout,

input a,b,cin,
);
Wire s1,c1,c2;
Halfadder HA1(s1,c1,a,b);

Halfadder HA2(s,c2,s1,cin);
Or (cout,c2,c1);
Endmodule
Module ripple_adder(

Output [3:0]sumr,

Output cout;

Input[3:0]a,b;

Input cin

);

Wire c1,c2,c3;

Fulladder FA1(sum[0],c1,a[0],b[0],cin);

Fulladder FA2(sum[1],c2,a[1],b[1],c1);

Fulladder FA3(sum[2],c3,a[2],b[2],c2);

Fulladder FA4(sum[3],cout,a[3],b[3],c3);

Endmodule

//gray to binary using generate statement

Module graytobinary(gray,bin);

Parameter SIZE=4;

Input[SIZE-1:0]gray;
Output [SIZE-1]:0bin;

Genvar i;

Generate for(i=0;i<SIZE;i++)

Begin:bit

Assign bin[i]=^gray[SIZE-1:i];

End

endgenerate

//code for clock division

Module counting(clk,clr,count)

Input clk,clr;

Output reg[3:0]count;

Reg[24:0]clk_div=0;

Initial count=0;

always@(posedge clk)

begin

clk_div=clk_div+1;

end

always@(posedge clk_div[24])

begin

if(clk==0)

count=count+1;

else

count=4’b0000;

end
endmodule

//bitwise operations using task

Module operation/9inAa,inA,AB_AND,AB_OR,AB_XOR);

Input[15:0]inA,inB;

Output reg[15:0]AB_AND,AB_OR,AB_XOR;

Reg[15:0]A,B;

Always@(inA or inB)

Beign

A=inA;

B=inB;

Bitwise_oper(AB_AND,AB_OR,AB_XOR,A,B);

End

Task bitwise_oper;

Output[15:0] AB_AND,AB_OR,AB_XOR;

Input [15:0]A,B;

Begin #1 AB_AND=A&B;

AB_OR=A|B;

AB_XOR=A^B;

End

endtask

Endmodule

//full adder using task

module fulladder_task(a,b,cin,y,co);
input a,b,cin;
 output s,cout;
reg w1,w2,w3;
always@(a,b,cin)

begin
Halfadder (a,b,w1,w2);
Halfadder (w1,cin,y,w3);
Assign cout=w3|w2

End
Task halfadder;
Input a,b;
Output y,cout;

Begin
Y=a^b;
Cout=a&b;
End
Endtask

endmodule

//recursivefunction

Module recursivefunc(a);

Output reg[31:0]a;

Initial a=calfactorial(5);

Function automatic[31:0]calfactorial;

Input[7:0]number;

Begin

If(number==1)
 Calfactorial=1;

Else

Calfactorial=number*( Calfactorial(num-1));

End

Endfunction

Endmodule

//Interfacing programs

//stepper motor

Module stepper(clk,stepper);

Input clk;

Output reg[3:0]stepper;

Reg[23:0]cnt=0;

Reg[1:0]select=0;

always@(posedgde clk)

begin

cnt=cnt+1;

end

always@(posedge cnt[22])

begin

select<=select+2’b01;

case(select)

2’b00:stepper=4’b0110;

2’b01:stepper=4’b0101;

2’b10:stepper=4’b1001;
2’b11:stepper=4’b1010;

Default:stepper=4’b0000;

Endcase

End

Endmodule

//fnd counter

Module FNd_counter(relay,clk,FND0);

Input clk;

Output relay;

Output reg [7:0]FND0;

Reg [22:0]cnt;

Reg[15:0]val;

always@(posedge clk)

cnt=cnt+1;

always@(posedge cnt[22])

begin

val=val+1;

case(val[3:0])

0:FND0 = 8’b00111111;

1:FND0 = 8’b00000110;

2:FND0 = 8’b01011011;

3:FND0 = 8’b01001111;

4:FND0 = 8’b01100110;
5:FND0 = 8’b01101101;

6:FND0 = 8’b01111110;

7:FND0 = 8’b00000111;

8:FND0 = 8’b01111111;

9:FND0 = 8’b01101111;

10:FND0 = 8’b01110111;

11:FND0 = 8’b01111100;

12:FND0 = 8’b00111001;

13:FND0 = 8’b01011110;

14:FND0 = 8’b01111001;

15:FND0 = 8’b01110001;

Default:FND0=8’b00000000;

Endcase

End

Endmodule

//keypad

Module keypad(

Input [3:0]row,

Output reg[3:0]column,

Input clk

);

Reg[1:0]state;

Reg[17:0]count;

Always@(posedge clk)
Count=count+1;

Always@(posedge count[17])

Begin

State=state+1;

Case(state)

0:begin

Column=4’b1000;

Case(row)

4’h8:value=4’b1101;

4’h4:value=4’b1111;

4’h2:value=4’b0000;

4’h1:value=4’b1110;

Default value=value;

Endcase

End

1:begin

Column=4’b0100;

Case(row)

4’h8:value=4’b1010;

4’h4:value=4’b0011;

4’h2:value=4’b0010;

4’h1:value=4’b0001;

Default value=value;

Endcase
End

2:begin

Column=4’b0010;

Case(row)

4’h8:value=4’b1011;

4’h4:value=4’b0110;

4’h2:value=4’b0101;

4’h1:value=4’b0100;

Default value=value;

Endcase

End

3:begin

Column=4’b1001;

Case(row)

4’h8:value=4’b1100;

4’h4:value=4’b1001;

4’h2:value=4’b1000;

4’h1:value=4’b0111;

Default value=value;

Endcase

End

Endcase

End

Endmodule
//lcd

module lcd(clk,data,rst,rs,en,rw
);

input clk;
output rst;
output reg [7:0]data;

reg pre_clk,rs,en;
reg [5:0]step;
reg [32:0]clk_div;

parameter H = 8'b01001000,
E = 8'b01000101,
L = 8'b01001100,
O = 8'b01001111;
assign rw = 1'b0;

always@(posedge clk)
begin
clk_div = clk_div + 1;
pre_clk = clk_div[14];

end

always@(posedge pre_clk)
begin

if(rst == 1'b1)
step = 6'b0;
else
step = step + 1;
end
always@(step)
begin
case(step)

1: begin
en = 0;
end
2: begin

data= 8'h38;
rs = 0;
en = 1;
end

3: begin
en = 0;
end
4: begin
data = 8'h38;

rs = 0;
en = 1;
end
5: begin

en = 0;
end
6: begin
data = 8'h0c;

rs = 0;
en = 1;
end
7: begin

en = 0;
end
8: begin
data= 8'h06;

rs = 0;
en = 1;
end
9: begin

en = 0;
end
10: begin
data = 8'h01;

rs = 0;
en = 1;
end
11: begin
en = 0;

end
12: begin
data = 8'h80;
rs = 0;

en = 1;
end
13: begin
en = 0;

end

14: begin
data = H;

rs = 1;
en = 1;
end
15: begin

en = 0;
end
16: begin
data = E;

rs = 1;
en = 1;
end
17: begin

en = 0;
end
18: begin
data = L;
rs = 1;

en = 1;
end
19: begin
en = 0;

end
20: begin
data = L;
rs = 1;

en = 1;
end
21: begin
en = 0;

end
22: begin
data = 0;
rs = 1;

en = 1;
end
23: begin
en = 0;

end
endcase
end
endmodule

//mealy
Module mealy_fsm(din,reset,clk,y);
Input din;
Input clk;
Input reset;

Output reg y;
Reg[1:0]cst,nst;
Parameter s0=2’b00, s1=2’b01, s2=2’b10, s3=2’b11;
always@(cst,din)

begin
case(cst)
s0:if(din==1’b1)
begin nst=s0;y=1’b0;end

else
begin nst=s1;y=1’b0;end
s1:if(din==1’b0)
begin nst=s1;y=1’b0;end

else
 begin nst=s2;y=1’b0;end
s2:if(din==1’b1)
begin nst=s0;y=1’b0;end

else
begin nst=s3;y=1’b0;end
s3:if(din==1’b0)
begin nst=s1;y=1’b0;end

else
begin nst=s2;y=1’b1;end
default : nst=s0;
endcase

end
always@(posedge clk)
begin
if(reset)cst<=s0;
else cst<=nst;

end
endmodule

//moore model

Module moore_fsm(din,reset,clk,y);
Input din;
Input clk;
Input reset;

Output reg y;
Reg[1:0]cst,nst;
Parameter s0=3’b000, s1=3’b001, s2=3’b010, s3=3’b011, s4=3’b100;
always@(cst or din)

begin
case(cst)
s0:begin y=1’b0;
if(din==1’b1)nst=s0;

else nst=s1;end
s1:begin y=1’b0;
if(din==1’b0)nst=s1;
else nst=s2;end

s2:begin y=1’b0;
if(din==1’b1)nst=s0;
else nst=s3;end

s3:begin y=1’b0;
if(din==1’b0)nst=s1;
else nst=s4;end
s4:begin y=1’b1;
if(din==1’b0)nst=s1;

else nst=s0;end
default:nst=s0;
endcase
end

always@(posedge clk)
begin
if(reset)cst<=s0;
else cst<=nst;

end
endmodule