STM32WB06xC STM32WB07xC

Datasheet

Ultra-low-power wireless 32-bit MCUs Arm®-based Cortex®-M0+ with

Bluetooth® Low Energy and 2.4 GHz radio solution

Features

VFQFPN48 VFQFPN WLCSP49

Includes ST state-of-the-art patented technology.
(6 x 6 mm) (5 x 5 mm) (3.140 x 3.140 mm)

Bluetooth® Low Energy system-on-chip supporting Bluetooth 5.4

specifications
• 2 Mbps data rate
• Long range (Coded PHY)
• Advertising extensions
• Channel selection algorithm #2
Product status • GATT caching
STM32WB06CC • LE Ping procedure
STM32WB06xC • Periodic advertising and periodic advertising sync transfer
STM32WB06KC
• Periodic advertising with response
STM32WB07CC
STM32WB07xC • Advertising coding selection
STM32WB07KC • Encrypted advertising
• LE L2CAP connection-oriented channel
• LE power control and path loss monitoring
• LE channel classification
• Enhanced ATT (EATT)
• Connection subrating
• Broadcast isochronous streams (BIS)
• Connection isochronous streams (CIS)

Radio
• Rx sensitivity level: -97 dBm @ 1 Mbps, -104 dBm @ 125 kbps (long range)
• Programmable output power up to +8 dBm (at antenna connector)
• Data rate supported: 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps
• 128 physical connections
• Integrated balun
• Support for external PA
• STM32WB0xxC core coprocessor (DMA based) for Bluetooth® Low Energy
timing critical operation
• 2.4 GHz proprietary radio driver
• Suitable for systems requiring compliance with the following radio frequency
regulations: ETSI EN 300 328, EN 300 440, FCC CFR47 part 15, ARIB STD-
T66
• Available integrated passive device (IPD) companion chip for optimized
matching and filtering

Ultra-low-power features (ultra-low-power devices)

• 10 nA in Shutdown mode (1.8 V)
• 0.6 μA in Deepstop mode (with external LSE and Bluetooth® Low Energy
wake-up sources, 1.8 V)

DS14676 - Rev 4 - February 2025 www.st.com

For further information, contact your local STMicroelectronics sales office.
 STM32WB06xC STM32WB07xC

• 0.9 μA in Deepstop mode (with internal LSI and Bluetooth® Low Energy wake-up sources, 1.8 V)
• 4.3 mA peak current in Tx (@ 0 dBm, 3.3 V)
• 3.4 mA peak current in Rx (@ sensitivity level, 3.3 V)
• High performance and ultralow power Arm® Cortex®-M0+ 32-bit, running up to 64 MHz
• Dynamic current consumption: 16.5 μA/MHz
• Operating supply voltage: from 1.7 to 3.6 V

Security
• Flash read/write protection
• SWD disabling
• Secure bootloader
• True random number generator (RNG)
• Hardware encryption AES maximum 128-bit security coprocessor
• Hardware public key accelerator (PKA)
• CRC calculation unit
• 64-bit unique ID

Clock management
• High efficiency embedded SMPS step-down converter with intelligent bypass mode
• Ultra-low-power power-on-reset (POR) and power-down-reset (PDR)
• Programmable voltage detector (PVD)
• Fail-safe 32 MHz crystal oscillator with integrated trimming capacitors
• 32 kHz crystal oscillator
• Internal low-power 32 kHz RO

Memories
• On-chip nonvolatile flash memory of 256 Kbytes
• On-chip RAM of 64 Kbytes or 32 Kbytes
• One-time-programmable (OTP) memory area of 1 Kbyte
• Embedded UART bootloader
• Ultra-low-power modes with or without timer and RAM retention

Security
• Flash read/write protection
• SWD disabling
• Secure bootloader
• True random number generator (RNG)
• Hardware encryption AES maximum 128-bit security coprocessor
• Hardware public key accelerator (PKA)
• CRC calculation unit
• 64-bit unique ID

System peripherals
• 1x DMA controller with eight channels supporting ADC, SPI, I2C, USART, and LPUART
• 1x SPI
• 2x SPI/I2S
• 2x I2C (SMBus/PMBus)
• 1x PDM (digital microphone interface)
• 1x LPUART

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 STM32WB06xC STM32WB07xC

• 1x USART (ISO 7816 smartcard mode, IrDA, SPI controller, and modbus)
• 1x independent WDG
• 1x real-time clock (RTC)
• 1x independent SysTick
• 1x 16-bit, six channel advanced timer

General-purpose inputs/outputs
• Quadrature decoder
• Up to 32 fast I/Os
• 28 of them with wake-up capability
• 31 of them 5 V tolerant

Analog peripherals
• 12-bit ADC with eight input channels, up to 16 bits with a decimation filter
• Battery monitoring
• Analog watchdog
• Analog mic I/F with PGA

Debug
• Development support
• Serial wire debug (SWD)
• Four breakpoints and two watchpoints

All packages are ECOPACK2 compliant.

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 STM32WB06xC STM32WB07xC
Introduction

1 Introduction

This document provides information on STM32WB0xxC devices, such as description, functional overview, pin
assignment and definition, electrical characteristics, packaging and ordering information.
It must be read in conjunction with the STM32WB0xxC reference manual (RM0530).
For information on the device errata with respect to the datasheet and reference manual, refer to the
STM32WB0xxC errata sheet (ES0632).
For information on the Arm® Cortex®-M0+ core, refer to the Arm® Cortex®-M0+ Processor Technical Reference
Manual, available from the www.arm.com website.
For information on Bluetooth®, refer to http://www.bluetooth.com website.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DT75330V2

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 STM32WB06xC STM32WB07xC
Description

2 Description

The STM32WB0xxC is an ultra-low-power programmable Bluetooth® Low Energy wireless SoC solution. It
embeds STMicroelectronics state-of-art 2.4 GHz RF radio IPs combining unparalleled performance with extremely
long-battery lifetime. It is compliant with Bluetooth® Low Energy SIG core specification version 5.4 addressing
point-to-point connectivity and Bluetooth Mesh networking and allows large-scale device networks to be
established in a reliable way. The STM32WB0xxC is also suitable for 2.4 GHz proprietary radio wireless
communication to address ultra-low latency applications.
The STM32WB0xxC embeds a Cortex®‑M0+ microcontroller that can operate up to 64 MHz and also the
BlueNRG core coprocessor (DMA based) for Bluetooth® Low Energy timing critical operations.
In addition, the STM32WB0xxC provides enhanced security hardware support by dedicated hardware functions:
True random number generator (RNG), encryption AES maximum 128-bit security coprocessor, public key
accelerator (PKA), CRC calculation unit, 64-bit unique ID, flash memory read and write protection.
The STM32WB0xxC can be configured to support standalone or network processor applications. In the first
configuration, the STM32WB0xxC operates as a single device in the application for managing both the application
code and the Bluetooth® Low Energy stack.
The STM32WB0xxC embeds high-speed and flexible memory types: flash memory of 256 Kbytes, RAM memory
of 64 Kbytes, one-time-programmable (OTP) memory area of 1 Kbyte, ROM memory of 7 Kbytes (ST reserved
area).
Direct data transfer between memory and peripherals and from memory-to-memory is supported by eight DMA
channels with a full flexible channel mapping by the DMAMUX peripheral.
The STM32WB0xxC embeds a 12-bit ADC, allowing measurements of up to eight external sources and up to
three internal sources, including battery monitoring and a temperature sensor.
The STM32WB0xxC has a low-power RTC and one advanced 16-bit timer.
The STM32WB0xxC features standard and advanced communication interfaces:
1x SPI, 2x SPI/I2S, 1x LPUART, 1x USART supporting ISO 7816 (smartcard mode), IrDA, and modbus mode, 2x
I2C supporting SMBus/PMBus, 1x channel PDM.
The STM32WB0xxC operates in the -40 to +105°C temperature range from a 1.7 V to 3.6 V power supply. A
comprehensive set of power-saving modes enables the design of low-power applications.
The STM32WB0xxC integrates a high efficiency SMPS step-down converter and an integrated PDR circuitry with
a fixed threshold that generates a device reset when the VDD drops under 1.65 V.
The STM32WB0xxC comes in different package versions supporting up to:
32 I/Os for the VFQFPN48 package, 20 I/Os for the VFQFPN32 package, 30 I/Os for the WLCSP49 package.
Refer to Table 1 for the list of peripherals available on each part number.

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 STM32WB06xC STM32WB07xC
Description

Table 1. Device features and peripheral counts

STM32WB06KC

STM32WB06CC

STM32WB07KC

STM32WB07CC
Peripherals

Flash memory (Kbytes) 256 Kbytes

SRAM0 16 Kbytes 16 Kbytes
SRAM1 16 Kbytes 16 Kbytes
SRAM (Kbytes)
SRAM2 - 16 Kbytes
SRAM3 - 16 Kbytes
Bluetooth® Low Energy Yes
General purpose 1 x 16-bit, 6 channel advanced timer
2.4 GHz proprietary
Timers radio timer 32-bit
low‑power
SysTick 1
Real-time clock (RTC) Yes
Random number generator Yes
AES Yes
Public key accelerator (PKA) Yes
SPI/I2S 2 with I2S feature
I2C 1
Communication interfaces
USART 1
LPUART 1
12-bit ADC with 1 PDM Number of channels 8
GPIOs 32
Wakeup pins 28
Maximum CPU frequency (MHz) 64
Operating voltage 1.7 to 3.6 V
Operating temperature Temperature range: −40 to 105 °C
VFQFPN32
5 x 5 mm, 0.50 mm pitch, very fine pitch quad flat no lead package
VFQFPN48
Packages
6 x 6 mm, 0.40 mm pitch, very fine pitch quad flat no lead package
WLCSP49
3.140 x 3.140 mm, 0.40 mm pitch, wafer level chip scale array package

Figure 1 shows the general block diagram of the device family.

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 STM32WB06xC STM32WB07xC
Description

Figure 1. STM32WB0xxC block diagram

256 KByte flash

NVIC

JTAG/SWD
SRAM0
Cortex-M0+
SRAM1

SRAM2

DMA (8 ch)
SRAM3

AHB Lite
DMAMUX
PKA + RAM

RNG

PWRC
MR_BLE

RCC

LSE GPIO0
32 kHz

LSI GPIO1
32 kHz SYSCFG

CRC
ADC

APB
HSE
32 kHz RTC SPI1
I2C1
IWDG SPI2/I2S2
RC64MPLL
I2C2
TIM1 SPI3/I2S3
Power supply/POR/ USART
BOR /PVD
LPUART

DT58101V1

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 STM32WB06xC STM32WB07xC
Functional overview

3 Functional overview

3.1 ARM Cortex–M0+ core with MPU

The STM32WB0xxC contains an ARM Cortex-M0+ microcontroller core. The Cortex-M0+ was developed to
provide a low-cost platform that meets the needs of CPU implementation, with a reduced pin count and low-power
consumption, while delivering outstanding computational performance and an advanced response to interrupts.
The Cortex-M0+ can run from 1 MHz up to 64 MHz.
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage
pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but
powerful instruction set and extensively optimized design, providing high-end processing hardware including a
single-cycle multiplier.
The interrupts are handled by the Cortex-M0+ Nested Vector Interrupt Controller (NVIC). The NVIC controls
specific Cortex-M0+ interrupts as well as the STM32WB0xxC peripheral interrupts. With its embedded ARM core,
the STM32WB0xxC family is compatible with all ARM tools and software.

3.2 Memory protection unit (MPU)

The MPU is used to manage accesses to memory to prevent one task from accidentally corrupting the memory or
resources used by any other active task. This memory area is organized into up to 8 protected areas. The
protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be protected against the
misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program
accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area settings, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

3.3 Memories

3.3.1 Embedded flash memory

The flash memory controller implements the erase and program Flash memory operation. The flash controller
also implements the read and write protection.
The flash memory features are:
• Memory organization:
– 1 bank of 256 kB
– Page size: 2 kB
– Page number 128
• 32-bit wide data read/write
• Page erase and mass erase
The flash memory controller features are:
• Flash memory read operations
• Flash memory write operations: single data write or 4x32-bits burst write
• Flash memory erase operations
• Page write protect mechanism

3.3.2 Embedded SRAM

The STM32WB0xxC has a total of 64 kB of embedded SRAM, split into four banks as shown in the following
table:

Table 2. SRAM overview

SRAM bank Size Address Retained in Deepstop

SRAM0 16 kB 0x2000 0000 Always

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 STM32WB06xC STM32WB07xC
Functional overview

SRAM bank Size Address Retained in Deepstop

SRAM1 16 kB 0x2000 4000 Programmable by the user

SRAM2 16 kB 0x2000 8000 Programmable by the user
SRAM3 16 kB 0x2000 C000 Programmable by the user

3.3.3 Embedded ROM

The STM32WB0xxC has a total of 7 Kbytes of embedded ROM. This area is ST reserved and contains:
• The UART bootloader from which the CPU boots after each reset (first 6 Kbytes of ROM memory)
• Some ST reserved values including the ADC trimming values (the last 1 Kbyte of ROM memory)

3.3.4 Embedded OTP

The one-time-programmable (OTP) is a memory of 1 Kbyte dedicated for user data. The OTP data cannot be
erased.
The user can protect the OTP data area by writing the last word at address 0x1000 1BFC and by performing a
system reset. This operation freezes the OTP memory from further unwanted write operations.

3.4 Security and safety

The STM32WB0xxC contains many security blocks for the Bluetooth® Low Energy and the host application.
It includes:
• Flash read/write protections
• As protection against potential hacker attacks, the SWD access can be disabled
• Secure bootloader
• Customer storage of the Bluetooth® Low Energy keys
• True random number generator (RNG)
• Private key accelerator (PKA) including:
– Elliptic curve Diffie-Hellman (ECDH) public-private key pair calculation accelerator
– Based on the Montgomery method for fast modular multiplications
– Built-in Montgomery domain inward and outward transformations
◦ AMBA® AHB lite target interface with a reduced command set
• Cyclic redundancy check calculation unit (CRC)

3.5 Boot modes

After the CPU boots, the application software has the capability to modify the memory map at address 0x0000
0000. This modification is carried out by programming the REMAP bit in the flash memory controller.
The following memory can be remapped:
• Main flash memory
• SRAM0 memory

3.6 Radio system

3.6.1 RF subsystem
The STM32WB0xxC embeds an ultralow power radio, compliant with the Bluetooth® Low Energy specification.
The Bluetooth® Low Energy features 1 Mbps and 2 Mbps transfer rates as well as long range options (125 kbps,
500 kbps), supports multiple roles simultaneously acting at the same time as a Bluetooth® Low Energy sensor
and a hub device.
The Bluetooth® Low Energy protocol stack is implemented by an efficient system partitioned as follows:
• Hardware part: BlueCore handling time-critical and time consuming Bluetooth® Low Energy protocol parts
• Firmware part: Arm® Cortex®-M0+ core handling nontime critical Bluetooth® Low Energy protocol parts

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 STM32WB06xC STM32WB07xC
Functional overview

3.6.1.1 RF front-end block diagram

The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF architecture in Rx mode.
Thanks to an internal transformer with RF pins, the circuit directly interfaces the antenna (single ended
connection, impedance close to 50 Ω). The natural band pass behavior of the internal transformer simplifies
outside circuitry aimed at harmonic filtering and out of band interferer rejection.
In transmit mode, the maximum output power is user selectable through the programmable LDO voltage of the
power amplifier. A linearized, smoothed analog control offers a clean power ramp-up.
In receive mode, the automatic gain control (AGC) can reduce the gain in both the RF and IF stages, optimizing
interferer rejection. Thanks to the use of complex filtering and a highly accurate I/Q architecture, high sensitivity,
and excellent linearity can be achieved.

Figure 2. STM32WB0xxC RF block diagram

Note:
DT58104V2
VFQFPN32 and VFQFPN48: VSS through exposed pad, and VSSRF pins must be connected to ground plane.
WLCSP49: VSSRF pins must be connected to ground plane.

3.6.1.2 IPDs for STM32WB06xC and STM32WB07xC

Table 3 lists the available IPD variants for the STM32WB06xC and STM32WB07xC devices.

Table 3. IPDs for STM32WB0xxC

IPD MCU package STM32WB06xC and STM32WB07xC part number

VFQFPN32, STM32WB06KCV, STM32WB06CCV

MLPF-NRG-01D3 VFQFPN48 STM32WB07KCV, STM32WB07CCV
WLCSP49 STM32WB06CCF, STM32WB07CCF

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Functional overview

3.7 Power supply management

3.7.1 Power supply schemes

The STM32WB0xxC embeds three power domains:
• VDD33 (VDDIO or VDD):
– the voltage range is between 1.7 V and 3.6 V
– it supplies a part of the I/O ring, the embedded regulators and the system analog IPs as power
management block and embedded oscillators
• VDD12o:
– always-on digital power domain
– this domain is generally supplied at 1.2 V during active phase of the device
– this domain is supplied at 1.0 V during low power mode (Deepstop)
• VDD12i:
– interruptible digital power domain
– this domain is generally supplied at 1.2 V during active phase of the device
– this domain is shut down during low-power mode (Deepstop)

Figure 3. Power supply domain overview

VDDIO VFBSD

SMPS
VREG PAD

VGATEN CMDNO CMDNI VGATEP

LP-Reg MLDO
RFLDOs

VDD12O VDD12I VRF

V33 Domain AlwaysOn Interruptible domain
(VDDIO) Domain (VDD12I)
(VDD12O)
HSI CPU Analog
HSE, LSI, LSE RF
BLE_wakeup, RF_FSM
PDR, POR, PVD
RTC, WDOG, BLE
PWRC33,
PWRCo, Peripherals
RCC33
RCCo RCCi

3.7.2 Power supply supervisor

The STM32WB0xxC device embeds several power voltage monitorings:
• Power-on-reset (POR): during the power-on, the device remains in reset mode if VDDIO is below a VPOR
threshold (typically 1.65 V)
• Power-down-reset (PDR): during power-down, the PDR puts the device under reset when the supply
voltage (VDD) drops below the VPDR threshold (around 20 mV below VPOR). The PDR feature is always
enabled
• Programmable voltage detector (PVD): can be used to monitor the VDDIO (against a programmed
threshold) or an external analog input signal. When the feature is enabled and the PVD measures a
voltage below the comparator, an interrupt is generated (if unmasked)

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3.7.3 SMPS step-down regulator

The device integrates a step-down converter to improve low-power performance when the VDD voltage is high
enough. The SMPS output voltage can be programmed from 1.2 V to 1.90 V. It is internally clocked at 4 MHz or
8 MHz.
The device can be operated without the SMPS by just wiring its output to VDD. This is the case for applications
where the voltage is low, or where the power consumption is not critical.
Except for the configuration SMPS OFF, an L/C BOM must be present on the board and connected to the VFBSD
pad.

Figure 4. Power supply configuration

3.7.4 Linear voltage regulators

The digital power supplies are provided by different regulators:
• The main LDO (MLDO):
– it provides 1.2 V from a 1.4-3.3 V input voltage
– it supplies both VDD12i and VDD12o when the device is active
– it is disabled during the low power mode (Deepstop)
• Low power LDO (LPREG):
– it stays enabled during both active and low power phases
– it provides 1.0 V voltage
– it is not connected to the digital domain when the device is active
– it is connected to the VDD12o domain during low power mode (Deepstop)
• A dedicated LDO (RFLDO) to provide a 1.2 V to the analog RF block
An embedded SMPS step-down converter is available (inserted between the external power and the LDOs).

3.8 Low-power modes

Several operating modes are defined for the STM32WB0xxC:
• Run mode
• Deepstop mode
• Shutdown mode

Table 4. Relationship between the low power modes and functional blocks

Mode Shutdown Deepstop Idle Run

CPU OFF OFF OFF ON

Flash OFF OFF ON ON
RAM OFF ON/OFF granularity 16 Kbytes ON/OFF ON/OFF
Radio OFF OFF ON/OFF ON/OFF
Supply system OFF OFF ON (DC-DC ON/OFF) ON (DC-DC ON/OFF)
Register retention OFF ON ON ON

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 STM32WB06xC STM32WB07xC
Functional overview

Mode Shutdown Deepstop Idle Run

HS clock OFF OFF ON ON

LS clock OFF ON/OFF ON ON
Peripherals OFF OFF ON/OFF ON/OFF
Wake-on RTC OFF ON/OFF ON/OFF NA
Wake-on GPIOs OFF ON/OFF ON/OFF NA
Wake-on reset pin ON ON ON NA

3.8.1 Run mode

In Run mode the STM32WB0xxC is fully operational:
• All interfaces are active
• The internal power supplies are active
• The system clock and the bus clock are running
• The CPU core and the radio can be used
The power consumption may be reduced by gating the clock of the unused peripherals.

3.8.2 Deepstop mode

The Deepstop is the only low power mode of the STM32WB0xxC allowing the restart from a saved context
environment and the application at wakeup to go on running.
The conditions to enter the Deepstop mode are:
• The radio is sleeping (no radio activity)
• The CPU is sleeping (WFI with SLEEPDEEP bit activated)
• No unmasked wakeup sources are active
• The low power mode selection (LPMS) bit of the power controller unit is 0 (default)
In Deepstop mode:
• The system and the bus clocks are stopped
• Only the essential digital power domain is ON and supplied at 1.0 V
• The bank RAM0 is kept in retention
• The other banks of RAM can be in retention or not, depending on the software configuration
• The low speed clock can be running or stopped, depending on the software configuration:
– ON or OFF
– Sourced by LSE or by LSI
• The RTC and the IWDG stay active, if enabled and the low speed clock is ON
• The I/Os pull-up and pull-down can be controlled during Deepstop mode, depending on the software
configuration
• The radio wakeup block, including its timer, stays active (if enabled and the low speed clock is ON)
• Eight I/Os (PA4/ PA5/ PA6/ PA7/ PA8/ PA9/ PA10/ PA11) can be in output driving:
– A static low or high level
– The low speed clock
– The RTC output
Possible wakeup sources are:
• The radio block is able to generate two events to wake up the system through its embedded wakeup timer
running on a low speed clock:
– Radio wakeup time is reached
– CPU host wakeup time is reached
• The RTC can generate a wakeup event
• The IWDG can generate a reset event
• Up to 28 GPIOs are able to wake up the system (PA0 to PA15 and PB0 to PB11)

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At the wakeup, all the hardware resources located in the digital power domain that are OFF during the Deepstop
mode, are reset. The CPU reboots. The wakeup reason is visible in the register of the power controller.

3.8.3 Shutdown mode

The Shutdown mode is the least power-consuming mode.
The conditions to enter Shutdown mode are the same conditions needed to enter Deepstop mode except that the
LPMS bit of the power controller unit is 1.
In Shutdown mode, the STM32WB0xxC is in ultralow power consumption: all voltage regulators, clocks, and the
RF interface are not powered. The STM32WB0xxC can enter shutdown mode by internal software sequence. The
only way to exit Shutdown mode is by asserting and deasserting the RSTN pin.
In shutdown mode:
• The system is powered down as both the regulators are OFF.
• The VDDIO power domain is ON.
• All the clocks are OFF, LSI, and LSE are OFF.
• The I/Os pull-up and pull-down can be controlled during Shutdown mode, depending on the software
configuration.
• The only wakeup source is a low pulse on the RSTN pin.
The exit from Shutdown is similar to a POR startup. The PDR feature can be enabled or disabled during
Shutdown.

3.9 Peripheral interconnect matrix

3.9.1 System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
• Three masters:
– CPU (Cortex®-M0+) core S-bus
– DMA1
– Radio system
• Nine slaves:
– Internal Flash memory on CPU (Cortex®-M0+) S bus
– Internal SRAM0 (16 kB)
– Internal SRAM1 (16 kB)
– Internal SRAM2 (16 kB)
– Internal SRAM3 (16 kB)
– APB0 peripherals (through an AHB to APB bridge)
– APB1 peripherals (through an AHB to APB bridge)
– AHB0 peripherals
– AHBRF including AHB to APB bridge and radio peripherals (connected to APB2)
The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even
when several high-speed peripherals work simultaneously.

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Figure 5. Bus matrix

3.10 Reset and clock controller (RCC)

3.10.1 Reset management

The STM32WB0xxC offers two different resets:
• The PORESETn: this reset is provided by the low power management unit (LPMU) analog block and
corresponds to a POR or PDR root cause. It is linked to power voltage ramp-up or ramp-down. This reset
impacts all resources of the STM32WB0xxC. The exit from Shutdown mode is equivalent to a POR and
thus generates a PORESETn. The PORESETn signal is active when the power supply of the device is
below a threshold value or when the regulator does not provide the target voltage.

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• The PADRESETn (system reset): this reset is built through several sources:
– PORESETn
– Reset due to the watchdog
The STM32WB0xxC device embeds a watchdog timer, which may be used to recover from software
crashes
– Reset due to CPU lockup
The Cortex®-M0+ generates a lockup to indicate the core is in the lock-up state resulting from an
unrecoverable exception. The lock-up reset is masked if a debugger is connected to the Cortex®-
M0+
– Software system reset
The system reset request is generated by the debug circuitry of the Cortex®-M0+. The debugger sets
the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR). This system
reset request through the AIRCR can also be done by the embedded software (into the hard fault
handler for instance)
– Reset from the RSTN external pin
The RSTN pin toggles to inform that a reset has occurred
This PADRESETn resets all resources of the STM32WB0xxC, except:
• Debug features
• Flash memory controller key management
• RTC timer
• Power controller unit
• Part of the RCC registers
The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case
of reset from the RSTN external pad, the reset pulse is generated when the pad is asserted low.

3.10.2 Clock management

Three different clock sources may be used to drive the system clock of the STM32WB0xxC:
• HSI: high speed internal 64 MHz RC oscillator
• PLL64M: 64 MHz PLL clock
• HSE: high speed 32 MHz external crystal
The STM32WB0xxC also has a low speed clock tree used by some timers in the radio, RTC, and IWDG.
Four different clock sources can be used for this low speed clock tree:
• Low speed internal (LSI): low speed and low drift internal RC with a fixed frequency between 24 kHz and
49 kHz depending on the sample
• Low speed external (LSE) from:
– An external crystal 32.768 kHz
– A single-ended 32.738 kHz input signal
• A 32 kHz clock (CLK_16 MHz/512 in Figure 6. Clock tree) obtained by dividing HSI or HSE. In this case,
the slow clock is not available in Deepstop low power mode
• LSI_LPMU: 32 kHz clock used by the low power management unit (LPMU) analog block.
By default, after a system reset, all low-speed sources are OFF.
Both the activation and the selection of the slow clock are relevant during the Deepstop mode and at wakeup as
the slow clock generates a clock for the timers involved in wakeup event generation.
The HSI and the PLL64M clocks are provided by the same analog block called RC64MPLL. The 64 MHz clock
output by this block can be:
• A nonaccurate clock when no external XO provides an input clock to this block (HSI)
• An accurate clock when the external XO provides the 32 MHz and once its internal PLL is locked (PLL64M)
This fast clock source is used to generate all the fast clocks of the device through dividers. After reset, the
CLK_SYS is divided by four to provide a 16 MHz to the whole system (CPU, DMA, memories, and peripherals).
This fast clock source is also used to generate several internal fast clocks in the system:
• Always 32 MHz requested by a few peripherals like the radio

DS14676 - Rev 4 page 16/74

 STM32WB06xC STM32WB07xC
Functional overview

• Always 16 MHz requested by a few peripherals like serial interfaces (to maintain fixed the baud rate while
the system clock is switching from one frequency to another) or like the flash memory controller and radio
(to have a fixed reference clock to manage delays)

Figure 6. Clock tree

LSI RCO LSI_ LP MU

32 kHz RCO 32 kHz
CLKSLOWSEL
RCC_LCOSEL

RCC_LCO CK_RTC,
CK_WDG,
CK_BLEWKUP
CLK_16 M Hz /51 2

RCC_OSC32_OUT CLK_ TIM1

LSE O SC
32k Hz
RCC_OSC32_IN S Y S CL K D IV

SYSC L K P RE
CLK_SYS
OSC_OUT /1 , /2, .. , /32 to CPU,
HSE O SC AHB0,
1 1
32 M Hz
OSC_IN APB0,
0 0 APB1,
SYSC L K P RE SRAM ,
/1 , /2, .. , /64 PK A,
HSESEL CLK_SPI1
HSI HSESEL
RCO +PLL
64 M Hz SYSCLKDIV

/4 1
CLKANA_ADC CLK_SMPS
/2 0
CLK_SMPS
CLKANA_ADC,
SMPSDIV CLK_USART,
CLK_SYS CLK_I2C,
/2 1 CLK_BLE16,
RCC_MCO /1 , /2 , .. , /1 6 CLK_16MHz
HSE CLK_FLASH,
/4 0 CLK_PWR,
HSI CLK_RNG
1 CLK_LPUART
CLK_16 MHz/51 2 HSESEL CLKSYS_BLE
0
RCC_MCOSEL
1
BLECLKDIV
CLK_32MHz CLK_BLE32 ,
CLKDIG_ADC
/2 0

1
HSESEL
C L K_16 MH z CLK_SPI2/I2S2
0

SP2CKSEL

1
CLK_SPI3/I2S3
0

DT58107V2
SP3CKSEL

It is possible to output some internal clocks on external pads:

• The low speed clocks can be output on the RCC_LCO I/O
• The high speed clocks can be output on the RCC_MCO I/O
This is possible by programming the associated I/O in the correct alternate function.
Most of the peripherals only use the system clock except:
• I2C, USART, LPUART: they always use an a16 MHz clock to have a fixed reference clock for baud rate
management. The goal is to allow the CPU to boost or slow down the system clock (depending on ongoing
activities) without impacting a potential ongoing serial interface transfer on external I/Os
• SPI: when the I2S mode is used, the baud rate is always managed through the 16 MHz or 32 MHz clock.
When modes other than the I2S run, the baud rate is managed by the system clock. This implies that its
baud rate is impacted by dynamic system clock frequency changes
• RNG: in parallel to the system clock, the RNG always uses a 16 MHz clock to generate at a constant
frequency the random number whatever the system clock frequency
• Flash memory controller: in parallel to the system clock, the flash memory controller always uses a 16 MHz
clock to generate specific delays required by the flash memory during programming and erase operations
for example
• PKA: in parallel to the system clock, the PKA uses a clock at half of the system clock frequency

DS14676 - Rev 4 page 17/74

 STM32WB06xC STM32WB07xC
Functional overview

• Radio: it does not directly use the system clock for its APB/AHB interfaces, but the system clock with a
potential divider (1 or 2 or 4). In parallel, the radio always uses 16 MHz and always 32 MHz for modulator,
demodulator and to have a fixed reference clock to manage specific delays
• ADC: in parallel to the system clock, ADC uses a 64 MHz prescaled clock running at 16 MHz

3.11 General purpose inputs/outputs (GPIO)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without
pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB0 bus.
The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid
spurious writing to the I/Os registers.

3.11.1 Tx and Rx event alert

The STM32WB0xxC is provided with the RADIO_TX_SEQUENCE and RADIO_RX_SEQUENCE signals which
alert, respectively, transmission and reception activities.
A signal can be enabled for Tx and Rx on two pins, through alternate functions:
• RADIO_TX_SEQUENCE is available on PA10 (AF2) or PB15 (AF1).
• RADIO_RX_SEQUENCE is available on PA8 (AF2) or PA11 (AF2).
The signal is high when the radio is in Tx (or Rx), low otherwise.
The signals can be used to control external antenna switching and support coexistence with other wireless
technologies.

DS14676 - Rev 4 page 18/74

 STM32WB06xC STM32WB07xC
Functional overview

3.12 Direct memory access (DMA)

The DMA is used in order to provide high-speed data transfer between peripherals and memory as well as
memory-to-memory. Data can be quickly moved by DMA without any CPU actions. In this manner, CPU resources
are free for other operations.
The DMA controller has eight channels in total. Each has an arbiter to handle the priority among DMA requests.
DMA main features are:
• Eight independently configurable channels (requests)
• Each of the eight channels is connected to dedicated hardware DMA requests, software trigger is also
supported on each channel. This configuration is done by software
• Priorities among requests from channels of DMA are software programmable (four levels consisting of very
high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, and so on)
• Independent source and destination transfer size (byte, half word, word), emulating packing and
unpacking. Source/destination addresses must be aligned on the data size
• Support for circular buffer management
• Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed
together in a single interrupt request for each channel
• Memory-to-memory transfer (RAM only)
• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers
• Access to SRAMs and APB1 peripherals as source and destination
• Programmable number of data to be transferred: up to 65536

3.13 Interrupts and events

3.13.1 Nested vectored interrupt controller (NVIC)

The interrupts are handled by the Cortex®-M0+ nested vector interrupt controller (NVIC). NVIC controls specific
Cortex®-M0+ interrupts as well as the STM32WB0xxC peripheral interrupts.
The NVIC benefits are the following:
• Nested vectored interrupt controller that is an integral part of the Arm® Cortex®-M0+
• A tightly coupled interrupt controller provides low interrupt latency
• Control system exceptions and peripheral interrupts
• NVIC supports 32 vectored interrupts
• Four programmable interrupt priority levels with hardware priority level masking
• Software interrupt generation using the Arm® exceptions SVCall and PendSV
• Support for NMI
• Arm® Cortex® M0+ vector table offset register VTOR implemented
NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.14 Analog digital converter (ADC)

The STM32WB0xxC embeds a 12-bit ADC. The ADC consists of a 12-bit successive approximation analog-to-
digital converter (SAR) with 2 x 8 multiplexed channels allowing measurements of up to eight external sources
and up to two internal sources.
The ADC main features are:
• Conversion frequency is up to 1 Msps
• Three input voltage ranges are supported (0 - 1.2 V, 0 - 2.4 V, 0 - 3.6 V)
• Up to eight analog single-ended channels or four analog differential inputs or a mix of both
• Temperature sensor conversion
• Battery level conversion up to 3.6 V
• ADC continuous or single mode conversion is possible
• ADC down-sampler for multi-purpose applications to improve analog performance while off-loading the
CPU (ratio adjustable from 1 to 128)
• A watchdog feature to inform when data is outside thresholds

DS14676 - Rev 4 page 19/74

 STM32WB06xC STM32WB07xC
Functional overview

• DMA capability
• Interrupt sources with flags.

3.14.1 Digital MEMS microphone interface

The digital MEMS microphone interface aims to interconnect with an external digital MEMS microphone. The
STM32WB0xxC can configure two GPIOs as a PDM interface. The PDM_CLK provides the clock output signal,
programmable in frequency, to the microphone, while the PDM_DATA receives the PDM output data from the
microphone. The decimation filter and the digital control resources are used to handle the PDM data stream.

3.14.2 Analog microphone interface

The analog microphone interface is dedicated to the analog microphone signal. The input audio signal is amplified
with a programmable gain amplifier (PGA) from 0 dB to 30 dB, then the data stream is sampled by ADC and
processed through the decimation filter.

3.14.3 Temperature sensor

The temperature sensor (TS) generates a voltage that varies linearly with temperature. The temperature sensor is
internally connected to the ADC input channel, which is used to convert the sensor output voltage into a digital
value.
To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by
ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in
read-only mode.

3.15 True random number generator (RNG)

An RNG, or random number generator, is based on continuous analog noise and provides a 16-bit value to the
host upon being read. The minimum period is 1.25 µs, which corresponds to 20 RNG clock cycles between two
consecutive random numbers.

3.16 Timers and watchdog

The STM32WB0xxC includes one advanced 16-bit timer, one watchdog timer, and a SysTick timer.

3.16.1 Advanced control timer (TIM1)

The advanced-control timer can be considered as a three-phase PWM multiplexed on six channels. The six
channels have complementary PWM outputs with programmable inserted dead-times.
They can also be used as general-purpose timers for:
• Input capture (except channels 5 and 6)
• Output compare
• PWM generation (edge and center-aligned mode)
• One-pulse mode output

3.16.2 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from the LS clock
and it can operate in Deepstop mode. It can also be used as a watchdog to reset the device when a problem
occurs.

3.16.3 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It
features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0

DS14676 - Rev 4 page 20/74

 STM32WB06xC STM32WB07xC
Functional overview

3.17 Real-time clock (RTC), tamper and backup registers

3.17.1 Real-time clock (RTC)

The RTC is an independent BCD timer/counter. The RTC provides a time of day/clock/calendar with
programmable alarm interrupt. RTC includes also a periodic programmable wakeup flag with interrupt capability.
The RTC provides an automatic wakeup to manage all low power modes.
Two 32-bit registers contain seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of
month), month, and year, expressed in binary coded decimal format (BCD). The sub-second value is also
available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the
programmable alarm sub seconds, seconds, minutes, hours, day, and date.
A digital calibration circuit with 0.95 ppm resolution is available to compensate for quartz crystal inaccuracy. After
power-on reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply
voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low
power mode or under system reset). The RTC counter does not freeze when CPU is halted by a debugger.

3.18 Inter-integrated circuit interface (I2C)

The STM32WB0xxC embeds two I2Cs. The I2C bus interface handles communications between the
microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration, and timing.
The I2C peripheral supports:
• I2C bus specification and user manual rev. 5 compatibilities:
– Target and controller modes
– Multicontroller capability
– Standard mode (Sm), with a bitrate up to 100 Kbit/s
– Fast mode (Fm), with a bitrate up to 400 Kbit/s
– Fast mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output driver I/Os
– 7-bit and 10-bit addressing mode
– Multiple 7-bit target addresses (two addresses, 1 with configurable mask)
– All 7-bit address acknowledge mode
– General call
– Programmable setup and hold times
– Easy to use event management
– Optional clock stretching
– Software reset
• System management bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK control
– Address resolution protocol (ARP) support
– Host and device support
– SMBus alert
– Timeouts and idle condition detection
• Power system management protocol (PMBus™) specification Rev. 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be
independent from the PCLK reprogramming
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

3.19 Universal synchronous/asynchronous receiver transmitter (USART/UART)

USART offers flexible full-duplex data exchange with external equipment requiring an industry standard NRZ
asynchronous serial data format. USART is able to communicate with a speed up to 2 Mbit/s. Furthermore,
USART is able to detect and automatically set its own baud rate, based on the reception of a single character.
The USART peripheral supports:

DS14676 - Rev 4 page 21/74

 STM32WB06xC STM32WB07xC
Functional overview

• Synchronous one-way communication

• Half-duplex single wire communication
• Local interconnection network (LIN) master/slave capability
• Smart card mode, ISO 7816 compliant protocol
• IrDA (infrared data association) SIR ENDEC specifications
• Modem operations (CTS/RTS)
• RS485 driver enable
• Multiprocessor communications
• SPI-like communication capability
High speed data communication is possible by using DMA (direct memory access) for multibuffer configuration.

3.19.1 Embedded UART bootloader

The STM32WB0xxC has a preprogrammed bootloader supporting the UART protocol with automatic baud rate
detection. The main features of the embedded bootloader are:
• Auto baud rate detection up to 1 Mbps
• Flash mass erase, section erase
• Flash programming
• Flash readout protection enable/disable
The preprogrammed bootloader is an application, which is stored in the STM32WB0xxC internal ROM at
manufacturing time by STMicroelectronics. This application allows upgrading the flash device with a user
application using a serial communication channel (UART).
The bootloader is activated by hardware by forcing PA10 high during hardware reset, otherwise, application
residing in flash is launched.

3.20 LPUART
LPUART is a UART which allows bidirectional UART communications. It supports half-duplex single wire
communications and modem operations (CTS/RTS). It also supports multiprocessor communications. DMA (direct
memory access) can be used for data transmission/reception.

3.21 Serial peripheral interface (SPI)

The STM32WB0xxC has three SPI interfaces (SPI1, SPI2, SPI3) allowing communication up to 32 Mbit/s in both
controller and target modes. The SPI peripheral supports:
• Controller or target operation
• Multimaster support
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• Serial communication with external devices
• NSS management by hardware or software for both controller and target: dynamic change of controller/
target operations
• SPI Motorola support
• SPI TI mode support
• Hardware CRC features for reliable communication
All SPI interfaces can be served by the DMA controller.

3.21.1 Inter-IC sound (I2S)

The STM32WB0xxC SPI interfaces: SPI2 and SPI3 support the I2S protocol. The I2S interface can operate in
target or controller mode with half-duplex communication. It can address four different audio standards:
• Philips I2S standard
• MSB-justified standards (left-justified)
• LSB-justified standards (right-justified)

DS14676 - Rev 4 page 22/74

 STM32WB06xC STM32WB07xC
Functional overview

• Phase-change memory standard.

The I2S interfaces DMA capability for transmission and reception.

3.22 Development support

3.22.1 Serial wire debug port

The STM32WB0xxC embeds an Arm SWD interface that allows interactive debugging and programming of the
device. The interface is composed of only two pins: DEBUG_SWDIO and DEBUG_SWCLK. The enhanced
debugging features for developers allow up to four breakpoints and up to two watchpoints.

DS14676 - Rev 4 page 23/74

 STM32WB06xC STM32WB07xC
Pinouts/ballouts, pin description, and alternate functions

4 Pinouts/ballouts, pin description, and alternate functions

4.1 Pinout/ballout schematics

The STM32WB0xxC comes in three package versions: VFQFPN48 offering 32 GPIOs, WLCSP49 offering 30
GPIOs and VFQFPN32 offering 20 GPIOs.

Figure 7. VFQFPN48 pinout

Package top view

PB4 PB5 PB6 PB7 PB8 PB9 P B 10 P B 11 VDD A VDD 1 R S T N VDD 3

48 47 46 45 44 43 42 41 40 39 38 37

PB3 1 36 VDD S D

PB2 2 35 VL XS D

PB1 3 34 VS S

PB0 4 33 NC

P A15 5 32 VF B S D

P A14 6 31 VC AP
GND
P A13 7 pa d 30 P B 12/ RCC_OSC32_OUT

P A12 8 29 P B 13/ RCC_OSC32_IN

P A11 9 28 P B 14

P A10 10 27 P B 15

P A9 11 26 VDD 4

P A8 12 25 O S C IN

13 14 15 16 17 18 19 20 21 22 23 24
RF1 .

VDDR F .

O S C O UT .

P A0 P A1 P A2 P A3 P A4 P A5 P A6 P A7 VDD 2

DT58108V2
Figure 8. VFQFPN32 pinout
Package top view

VDD 1 P B 4 PB5 PB6 P B 7 VC AP R S T N VDD S D

32 31 30 29 28 27 26 25

PB3 1 24 VL XS D

PB2 2 23 VS S

PB1 3 22 VF B S D

PB0 4 21 P B 12/ RCC_OSC32_OUT

GND
P A11 5 pa d 20 P B 13/ RCC_OSC32_IN

P A10 6 19 P B 14

P A9 7 18 P B 15

P A8 8 17 O S C IN

9 10 11 12 13 14 15 16
O S C O UT.

P A0 P A1 P A2 P A3 VDD 2
VDDR F
RF1

DT58109V2

DS14676 - Rev 4 page 24/74

 STM32WB06xC STM32WB07xC
Pinouts/ballouts, pin description, and alternate functions

Figure 9. WLCSP49 pinout

Package top view

1 2 3 4 5 6 7
5
A VDDSD VLXSD VSSIO VDD3 RSTN VDDA VSSA

B VSSSD PB7 PB6 PB5 PB4 PB3 PB2

C VFBSD PB12 PB9 PB1 PB0 PA15 PA14

D VCAP PB13 PA11 PB8 PA13 PA12 PA9

E OSCOUT PB14 PA4 PA3 PA2 PA10 PA8

VSS
F OSCIN PB15 VSSRF PA5 PA0 VSSIO
IFADC

VSSRFT
G VSSSX VDDRF RF1 PA7 PA1 VDD2

DT58110V1
RX

DS14676 - Rev 4 page 25/74

 4.2 Pin description
DS14676 - Rev 4

Table 5. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name.
A Analog-only input
I Input-only pin
Pin type I/O Input/output pin
O Output-only pin
S Supply pin
DDR 1.5 V or 1.2 V I/O for DDR3, DDR3L, LPDDR2/LPDDR3, DDR4, and LPDDR4
DDR
interfaces
DSI 1.2 V I/O for DSI interface
FT 5 V-tolerant I/O
FTP 5 V-tolerant I/O with fixed pull‑down
FTPD 5 V-tolerant I/O with fixed programmable pull‑down
FTU 5 V-tolerant I/O with fixed pull‑up
RF RF I/O

TC 3.6 V-capable I/O with ESS diode connected to VDD

Pinouts/ballouts, pin description, and alternate functions

TT 3.6 V-tolerant I/O

TTa 3.6 V-tolerant I/O with internal clamping to VDDA

I/O structure

STM32WB06xC STM32WB07xC
B Dedicated BOOT0 pin

POR External power on reset pin with embedded weak pull‑up resistor, powered from VDDA

RST Bidirectional reset pin with embedded weak pull‑up resistor

Options for TT and FT I/Os(1)

_a I/O with analog switch function supplied by VDDA

_c USB Type-C® power delivery capable I/O

_d USB Type-C® power delivery dead battery function I/O

_e I/O with switchable diode to VDD

_f I2C Fm+ capable I/O

page 26/74

_h High-speed low-voltage I/O

 DS14676 - Rev 4

Name Abbreviation Definition

_l I/O with LCD function supplied by VLCD

_p I/O with differential clock capability CLKP/CLKN

_s I/O supplied only by VDDIO2

I/O structure
_t Tamper I/O

_u I/O with USB function, supplied by VDDUSB

_v Very high-speed I/O

All I/Os are set as input pullup during and after reset, with the exception of PA2 (DEBUG_SWDIO) and PA3 (DEBUG_SWCLK) pins
Notes which are set, respectively, as alternate function pullup and alternate function pulldown. By default, all I/Os pull-ups/pull-downs are
controlled by the PWR IP, through the PWRC_PUCRx/PWRC_PDCRx registers.
Alternate functions Functions selected through GPIOx_AFR registers
Pin functions
Additional functions Functions directly selected/enabled through peripheral registers

1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a.

Pinouts/ballouts, pin description, and alternate functions

STM32WB06xC STM32WB07xC
page 27/74
 Table 6. STM32WB0xxC pin/ball definition
DS14676 - Rev 4

Pin number Pin name

(function after Pin type I/O structure Alternate functions Additional functions
VFQFPN32 VFQFPN48 WLCSP49 reset)

1 1 B6 PB3 I/O FT_a USART_CTS, LPUART_TX, TIM1_CH4 ADC_VINP0,PWR_WKUP3

2 2 B7 PB2 I/O FT_a USART_RTS_DE, PDM_DATA, TIM1_CH3 ADC_VINM0, PWR_WKUP2
3 3 C4 PB1 I/O FT_a SPI1_NSS, PDM_CLK, TIM1_ETR ADC_VINP1, PWR_WKUP1
4 4 C5 PB0 I/O FT_a USART_RX, LPUART_RTS_DE, TIM1_CH2N ADC_VINM1, PWR_WKUP0
- 5 C6 PA15 I/O FT_a I2C2_SMBA, SPI1_MOSI, TIM1_BKIN2 ADC_VINP2, PWR_WKUP27
- 6 C7 PA14 I/O FT_a I2C2_SDA, SPI1_MISO, TIM1_BKIN ADC_VINM2, PWR_WKUP26
I2C2_SCL, SPI1_SCK, SPI2_MISO,
- 7 D5 PA13 I/O FT_a ADC_VINP3, PWR_WKUP25
TIM1_ETR
I2C1_SMBA, SPI1_NSS,
- 8 D6 PA12 I/O FT_a ADC_VINM3, PWR_WKUP24
SPI2_MOSI,TIM1_CH1, I2S2_SD
RCC_MCO, SPI1_NSS,
PWR_WKUP11, GPIO in Deepstop,
5 9 D3 PA11 I/O FT RADIO_RX_SEQUENCE, SPI3_MOSI,
RTC_OUT
I2S3_SD
RCC_LCO, SPI1_MISO, BOOT, PWR_WKUP10, GPIO in Deepstop,
6 10 E6 PA10 I/O FT
RADIO_TX_SEQUENCE, I2S3_MCK RCC_LCO
USART_TX, SPI1_SCK, RTC_OUT,
7 11 D7 PA9 I/O FT PWR_WKUP9, GPIO in Deepstop, RCC_LCO
SPI3_NSS, TIM1_CH4, I2S3_WS
USART_RX, SPI1_MOSI,

Pinouts/ballouts, pin description, and alternate functions

8 12 E7 PA8 I/O FT RADIO_RX_SEQUENCE, SPI3_MISO, PWR_WKUP8, GPIO in Deepstop, RTC_OUT
TIM1_CH3
I2C1_SCL, USART_CTS, TIM1_CH3,
9 13 F6 PA0 I/O FT_f PWR_WKUP12
I2S2_MCK

STM32WB06xC STM32WB07xC
I2C1_SDA, SPI2_MISO, USART_TX,
10 14 G6 PA1 I/O FT_f PWR_WKUP13
TIM1_CH4
DEBUG_SWDIO, USART_CK, TIM_BKIN,
11 15 E5 PA2 I/O FT PWR_WKUP14
I2S3_MCK
DEBUG_SWCLK, USART_RTS_DE,
12 16 E4 PA3 I/O FT PWR_WKUP15
TIM_BKIN2, SPI3_SCK, I2S3_SCK
RCC_LCO, SPI2_NSS, LPUART_TX, PWR_WKUP16, GPIO in Deepstop,
- 17 E3 PA4 I/O FT
TIM1_CH1, I2S2_WS RCC_LCO
RCC_MCO, SPI2_SCK, LPUART_RX, PWR_WKUP17, GPIO in Deepstop,
- 18 F5 PA5 I/O FT
TIM1_CH2, I2S2_SCK RCC_LCO
page 28/74

LPUART_CTS, SPI2_MOSI, SPI2_NSS, PWR_WKUP18, GPIO in Deepstop,

- 19 - PA6 I/O FT
TIM1_CH1, I2S2_SD, I2S2_WS RCC_LCO
 DS14676 - Rev 4

Pin number Pin name

(function after Pin type I/O structure Alternate functions Additional functions
VFQFPN32 VFQFPN48 WLCSP49 reset)

LPUART_RTS_DE, SPI2_MISO, SPI2_SCK, PWR_WKUP19, GPIO in Deepstop,

- 20 G5 PA7 I/O FT
TIM1_CH2, I2S2_SCK RTC_OUT
13 21 G7 VDD2 S - - 1.7-3.6 battery voltage input
14 22 G4 RF1 I/O RF - RF input/output. Impedance 50 Ω
15 23 G2 VDDRF S - - 1.7-3.6 battery voltage input
16 24 E1 OSCOUT I/O RF - 32 MHz crystal
17 25 F1 OSCIN I/O RF - 32 MHz crystal
- 26 - VDD4 S - - 1.7-3.6 battery voltage input
I2C1_SMBA, RADIO_TX_SEQUENCE,
18 27 F2 PB15 I/O FT -
RCC_MCO, TIM1_CH4N, USART_TX
SPI1_MOSI, I2C2_SDA, TIM1_ETR,
19 28 E2 PB14 I/O FT_a PWR_PVD_IN
TIM1_CH3N, USART_RX
SPI1_MISO, I2C2_SCL, PDM_CLK,
20 29 D2 PB13 I/O FT RCC_OSC32_OUT
TIM1_BKIN2, TIM1_CH4
SPI1_SCK, RCC_LCO, PDM_DATA,
21 30 C2 PB12 I/O FT RCC_OSC32_IN
TIM1_BKIN, TIM1_CH3
27 31 D1 VCAP S - - 1.2 Vdigital core
22 32 C1 VFBSD S - - SMPS output

Pinouts/ballouts, pin description, and alternate functions

- 33 - NC S - - -
23 34 B1 VSSSD S - - SMPS Ground
24 35 A2 VLXSD S - - SMPS input/output

STM32WB06xC STM32WB07xC
25 36 A1 VDDSD S - - 1.7-3.6 battery voltage input
- 37 A4 VDD3 S - - 1.7-3.6 battery voltage input
26 38 A5 RSTN I/O RST - Reset pin
32 39 - VDD1 S - - 1.7-3.6 battery voltage input
- 40 A6 VDDA S - - 1.2 V analog ADC core
SPI1_SCK, SPI2_NSS, I2C1_SCL,
- 41 - PB11 I/O FT PWR_WKUP23
TIM1_CH1, TIM1_CH4N, I2S2_WS
SPI1_NSS, SPI2_SCK, I2C1_SDA,
- 42 - PB10 I/O FT PWR_WKUP22
TIM1_CH2, TIM1_CH3N, I2S2_SCK
USART_TX, LPUART_CTS, TIM1_CH1N,
page 29/74

- 43 C3 PB9 I/O FT PWR_WKUP21

TIM1_CH2N, I2S2_MCK
 DS14676 - Rev 4

Pin number Pin name

(function after Pin type I/O structure Alternate functions Additional functions
VFQFPN32 VFQFPN48 WLCSP49 reset)

USART_CK, LPUART_RX, TIM1_CH4,

- 44 D4 PB8 I/O FT PWR_WKUP20
TIM1_CH1N
I2C2_SDA, SPI2_SCK, LPUART_RX,
28 45 B2 PB7 I/O FT_f PWR_WKUP7
TIM1_CH2, I2S2_SCK
I2C2_SCL, SPI2_NSS, LPUART_TX,
29 46 B3 PB6 I/O FT_f PWR_WKUP6
TIM1_CH1, I2S2_WS
LPUART_RX, SPI2_MOSI, PDM_CLK,
30 47 B4 PB5 I/O TT PGA_VBIAS_MIC(1), PWR_WKUP5
I2S2_SD
48 31 B5 PB4 I/O FT LPUART_TX, SPI2_MISO, PDM_DATA PGA_VIN, PWR_WKUP4
- - A7 VSSA S - - Ground analog ADC core
- - A3 VSSIO S - - Ground I/O
- - F7 VSSIO S - - Ground I/O
- - F4 VSSIFADC S - - Ground analog RF
- - G1 VSSSX S - - Ground analog RF
- - G3 VSSRFTRX S - - Ground analog RF
- - F3 VSSRF S - - Ground analog RF
Exposed pad Exposed pad - GND S - - Ground

1. This pin is not 5 V tolerant.

Pinouts/ballouts, pin description, and alternate functions

STM32WB06xC STM32WB07xC
page 30/74
 4.3 Alternate functions
DS14676 - Rev 4

Table 7. Alternate function port A

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port I2C1/I2C2/SYS_AF SPI1/SPI2/ SYS_AF/ SPI1/SPI2/RTC USART/ SPI2/ SPI3 LPUART/
TIM1 SYS_AF - SYS_AF
LPUART/ USART USART/I2S2 TIM/ I2S2 I2S2/ I2S3

PA0 I2C1_SCL USART_CTS I2S2_MCK - TIM1_CH3 - - -

PA1 I2C1_SDA SPI2_MISO USART_TX - TIM1_CH4 - - -
PA2 DEBUG_SWDIO USART_CK TIM_BKIN I2S3_MCK - DEBUG_SWDIO - DEBUG_SWDIO
PA3 DEBUG_SWCLK USART_RTS_DE TIM_BKIN2 SPI3_SCK/I2S3_SCK - DEBUG_SWCLK - DEBUG_SWCLK
PA4 RCC_LCO SPI2_NSS/I2S2_WS - LPUART_TX TIM1_CH1 - - -
PA5 RCC_MCO SPI2_SCK/I2S2_SCK - LPUART_RX TIM1_CH2 - - -
PA6 LPUART_CTS SPI2_MOSI/I2S2_SD - SPI2_NSS/I2S2_WS TIM1_CH1 - - -
PA7 LPUART_RTS_DE SPI2_MISO - SPI2_SCK/I2S2_SCK TIM1_CH2 - - -
Port A
PA8 USART_RX SPI1_MOSI RADIO_RX_SEQUENCE SPI3_MISO TIM1_CH3 - - -
PA9 USART_TX SPI1_SCK RTC_OUT SPI3_NSS/I2S3_WS TIM1_CH4 - - -
PA10 RCC_LCO SPI1_MISO RADIO_TX_SEQUENCE I2S3_MCK - - - -
PA11 RCC_MCO SPI1_NSS RADIO_RX_SEQUENCE SPI3_MOSI/I2S3_SD - - - -
PA12 I2C1_SMBA DEBUG_SWDIO SPI1_NSS SPI2_MOSI/I2S2_SD TIM1_CH1 - - -

Pinouts/ballouts, pin description, and alternate functions

PA13 I2C2_SCL DEBUG_SWCLK SPI1_SCK SPI2_MISO TIM1_ETR - - -
PA14 I2C2_SDA - SPI1_MISO - TIM1_BKIN - - -

STM32WB06xC STM32WB07xC
PA15 I2C2_SMBA - SPI1_MOSI - TIM1_BKIN2 - - -
page 31/74
 Table 8. Alternate function port B
DS14676 - Rev 4

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port SPI2/I2C1/PDM TIM1/SYS_AF/
SPI1/I2C2 USART/LPUART PDM/SYS_AF/I2C2 LPUART/SPI2/I2S2 TIM1/PDM LPUART TIM1 - - USART
I2S2

PB0 USART_RX LPUART_RTS_DE - TIM1_CH2N - - - -

PB1 SPI1_NSS PDM_CLK - TIM1_ETR - - - -
PB2 USART_RTS_DE PDM_DATA - TIM1_CH3 - - - -
PB3 USART_CTS LPUART_TX - TIM1_CH4 - - - -
PB4 LPUART_TX SPI2_MISO - PDM_DATA - - - -
PB5 LPUART_RX SPI2_MOSI/I2S2_SD - PDM_CLK - - - -
PB6 I2C2_SCL SPI2_NSS/I2S2_WS - LPUART_TX TIM1_CH1 - - -
PB7 I2C2_SDA SPI2_SCK/IS2S_SCK - LPUART_RX TIM1_CH2 - - -
Port B
PB8 USART_CK LPUART_RX - TIM1_CH4 TIM1_CH1N - - -
PB9 USART_TX LPUART_CTS I2S2_MCK TIM1_CH1N TIM1_CH2N - - -
PB10 SPI1_NSS SPI2_SCK/I2S2_SCKK I2C1_SDA TIM1_CH2 TIM1_CH3N - - -
PB11 SPI1_SCK SPI2_NSS/I2S2_WS I2C1_SCL TIM1_CH1 TIM1_CH4N - - -
PB12 SPI1_SCK RCC_LCO PDM_DATA TIM1_BKIN TIM1_CH3 - - -
PB13 SPI1_MISO I2C2_SCL PDM_CLK TIM1_BKIN2 TIM1_CH4 - - -
PB14 SPI1_MOSI I2C2_SDA TIM1_ETR TIM1_CH3N - - - USART_RX

Pinouts/ballouts, pin description, and alternate functions

PB15 I2C1_SMBA RADIO_TX_SEQUENCE RCC_MCO TIM1_CH4N - - - USART_TX

STM32WB06xC STM32WB07xC
page 32/74
 STM32WB06xC STM32WB07xC
Application circuits

5 Application circuits

The schematics below are purely indicative.

Figure 10. Application circuit: DC-DC converter, VFQFPN48 package

C20

VDD

C18

VDD
C19

C5

VDD

C7
C8
49

47
46

44

42

40
39

37
48

45

38
43

41

C6
U1
GND

PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
VDDA
VDD1
RSTN
VDD3

C9
1 36
PB3 VDDSD
2 35
PB2 VLXSD
3 34

L1

L2
PB1 VSS
4 33
PB0 NC
5 32
PA15 VFBSD

C15
6 31
PA14 VCAP
7 PB12/RCC_OSC32_OUT 30
PA13
8 29

XTAL_LS
PA12 PB13/RCC_OSC32_IN
9 28
PA11 PB14
10 27

X1
PA10 STM32WB07xC/STM32WB06xC PB15
11 VFQFPN48 26
PA9 VDD4
12 25
PA8 OSCIN

C16
OSCOUT
VDDRF
VDD2

XTAL_HS
PA0

PA2

PA4

PA6
PA5

PA7
PA3
PA1

RF1

X2
13
14
15
16
17
18
19
20
21
22
23
24
C1

C3

VDD
C13
VDD

C17
VDD
C2

C14

C4
L3
C11

L4
C12

C10

DT58112V3
A1

DS14676 - Rev 4 page 33/74

 VDD VDD DT58113V2
C4 C3 C6 C5
Application circuits

page 34/74
STM32WB06xC STM32WB07xC

VDD
C18 VDD
C19
C7
C2 C1
Figure 11. Application circuit: DC-DC converter, WLCSP49 package

G7
A4
G2
A1

A6
D1

A5

U1
VDD3
VDD2

VDDRF
VDDSD

VCAP
VDDA

RSTN

F6
PA0
G6
PA1
E5 L1 L2
PA2
E4 A2
PA3 VLXSD
E3 C1
PA4 VFBSD C8
F5 C9
PA5
F3
VSSRF
G5
PA7
E7
PA8 C12
D7
PA9 A1
E6
PA10
D3 STM32WB07xC/STM32WB06xC
PA11
D6 L3 L4 C10
PA12
D5 G4
PA13 RF1
C7
PA14 C13 C11
C6 C14

WLCSP49
PA15
C5
PB0
C4
PB1
B7
PB2
B6
PB3
B5
PB4
B4
PB5
B3
PB6 X2
B2 F1
PB7 OSCIN
D4 E1
PB8 OSCOUT
C3
PB9 XTAL_HS
C2
RCC_OSC32_OUT /PB12
X1 D2
RCC_OSC32_OUT /PB13
E2
PB14
F2

VSSRFTRX
VSSIFADC
PB15

VSSSD

VSSSX
XTAL_LS

VSSIO

VSSIO
VSSA
C15 C16

B1

G1
G3
A3
F7
A7

F4

DS14676 - Rev 4
 STM32WB06xC STM32WB07xC
Application circuits

Figure 12. Application circuit: DC-DC converter, VFQFPN32 package

C5

VDD
C7

C6
C20

VDD

C8
32

30
29
28
27
26
33

25
31

U1
GND

VDD1
PB4
PB5
PB6
PB7
VCAP
RSTN
VDDSD

C9

C15
1 24
PB3 VLXSD
2 23

L1

L2
PB2 VSS
3 22

XTAL_LS
PB1 VFBSD
4 PB12/RCC_OSC32_OUT 21
PB0

X1
5 PB13/RCC_OSC32_IN 20
PA11
6 19
PA10 PB14
7 18
PA9 PB15
8 17
PA8 STM32WB07xC/STM32WB06xC OSCIN

C16
VFQFPN32
OSCOUT
VDDRF
VDD2
PA0

PA2
PA3
PA1

XTAL_HS
RF1

X2
9
10
11
12
13
14
15
16
C1

C3
C13
VDD

VDD
C2

C14

C4
L3
C11

L4
C12

C10

DT58114V2
A1

DS14676 - Rev 4 page 35/74

 STM32WB06xC STM32WB07xC
Application circuits

Table 9. Application circuit external components

Component Description

C1 Decoupling capacitor
C2 Decoupling capacitor
C3 Decoupling capacitor
C4 Decoupling capacitor
C5 Decoupling capacitor
C6 Decoupling capacitor
C7 Decoupling capacitor
C8 DC-DC converter output capacitor
C9 DC-DC converter output inductor
C10 DC block capacitor
C11 RF matching capacitor
C12 RF matching capacitor
C13 RF matching capacitor
C14 RF matching capacitor
C15 32 kHz crystal loading capacitor
C16 32 kHz crystal loading capacitor
C17 Decoupling capacitor
C18 Decoupling capacitor
C19 Decoupling capacitor
C20 Decoupling capacitor
L1 DC-DC converter output inductor
L2 DC-DC converter filtering inductor
L3 RF matching inductor
L4 RF matching inductor
X1 Low speed crystal
X2 High speed crystal
U1 STM32WB06xC/STM32WB07xC

Note: In order to make the board DC–DC OFF, the inductance L1 must be removed and the supply voltage must be
applied to the VFBSD pin.

DS14676 - Rev 4 page 36/74

 STM32WB06xC STM32WB07xC
Electrical characteristics

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction
temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an junction
temperature at TJ = 25 °C and TJ = TJmax (given by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics are indicated in the
table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and
represent the mean value plus or minus three times the standard deviation (mean ± 3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the 1.62 V ≤ VDD ≤ 3.6 V
voltage range). They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion
lot over the full temperature range, where 95% of the devices have an error less than or equal to the value
indicated (mean ± 2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 13.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 14.

Figure 13. Pin loading conditions Figure 14. Pin input voltage

Device pin
Device pin

VIN
C = 50 pF
DT47493V1

DT47494V1

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in the tables below, may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 10. Voltage characteristics

Symbol Ratings Min. Max. Unit

VDD1, VDD2, VDD3, VDD4, VDDRF, VDDSD DC-DC converter supply voltage input and output -0.3 +3.9
V
VCAP, VDDA DC voltage on linear voltage regulator -0.3 +1.32

DS14676 - Rev 4 page 37/74

 STM32WB06xC STM32WB07xC
Electrical characteristics

Symbol Ratings Min. Max. Unit

FXTALOUT, FXTALIN DC Voltage on HSE -0.3 +1.32

PA0 to PA15, PB0 to PB4, PB6 to PB15 DC voltage on digital input/output pins
-0.3 +3.9 V
VLXSD, VFBSD DC voltage on analog pins
RCC_OSC32_OUT/PB12, RCC_OSC32_IN/PB13,
DC voltage on XTAL pins and PGA_VBIAS_MIC +3.6
PB5 -0.3
RF1 DC voltage on RF pin +1.4 -
Variations between different VDDX
|ΔVDD| - 50 mV
power pins of the same domain

Note: All the main power and ground pins must always be connected to the external power supply, in the permitted
range.

Table 11. Current characteristics

Symbol Ratings Max. Unit

ΣIVDD Total current into sum of all VDD power lines (source) 130

ΣIVGND Total current out of sum of all ground lines (sink) 130

IVDD(PIN) Maximum current into each VDD power pin (source) 100

IVGND(PIN) Maximum current out of each ground pin (sink) 100

mA
Output current sunk by any I/O and control pin 20
IIO(PIN)
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins 100
ΣIIO(PIN)
Total output current sourced by sum of all I/Os and control pins 100

Table 12. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -40 to -125

°C
TJ Maximum junction temperature 125

6.3 Operating conditions

6.3.1 General operating conditions

Table 13. General operating conditions

Symbol Parameter Conditions Min. Max. Unit

fHCLK Internal AHB clock frequency - 1 64

fPCLK0 Internal APB0 clock - 1 64

MHz
fPCLK1 Internal APB1 clock frequency - 1 64

fPCLK2 Internal APB2 clock frequency - 16 32

VDD Standard operating voltage - 1.7 3.6

VFBSMPS SMPS feedback voltage - 1.4 3.6 V

VDDRF Minimum RF voltage - 1.7 3.6

DS14676 - Rev 4 page 38/74

 STM32WB06xC STM32WB07xC
Electrical characteristics

Symbol Parameter Conditions Min. Max. Unit

VIN I/O input voltage - -0.3 VDD+0.3 V

VFQFPN48 package
PD Power dissipation at TA=105 °C(1) - 30 mW
VFQFPN32 package
TA Ambient temperature Maximum power dissipation -40 105 °C

TJ Junction temperature range - -40 105 -

1. TA cannot exceed the TJ max.

6.3.2 Summary of main performance

Table 14. Main performance SMPS ON

Typ. Typ.
Symbol Parameter Test conditions Unit
VDD = 1.8 V VDD = 3.3 V

Shutdown 8 19 nA
Deepstop, no timer, wakeup
0.44 0.46
GPIO, RAM0 retained
Deepstop, no timer, wakeup
0.62 0.64
GPIO, all RAM retained
Deepstop (32 kHz LSI), RAM0
0.94 1.06
retained
µA
Deepstop (32 kHz LSI), all RAMs
1.12 1.24
retained
Deepstop (32 kHz LSE), RAM0
0.64 0.75
retained
Deepstop (32 kHz LSE), all RAM
Core current 0.83 0.94
ICORE retained
consumption
CPU in Run (64 MHz).
- 2719
Dhrystone, clock source PLL64
CPU in Run (32 MHz).
- 2188
Dhrystone, clock source PLL64
CPU in WFI (64 MHz), all
peripherals off, clock source - 1708
PLL64 uA

CPU in WFI (16 MHz), all

peripherals off, clock source - 1092
direct HSE
Radio Rx at sensitivity level - 3350
Radio Tx 0 dBm output power - 4300
Computed value: (CPU 64 MHz
IDYNAMIC Dynamic current Dhrystone - CPU 32 MHz - 16.5 µA/MHz
Dhrystone) / 32

DS14676 - Rev 4 page 39/74

 STM32WB06xC STM32WB07xC
Electrical characteristics

Table 15. Main performance SMPS bypassed

Typ. Typ.
Symbol Parameter Test conditions Unit
VDD = 1.8 V VDD = 3.3 V

Shutdown 8 19 nA
Deepstop, no timer,
wakeup GPIO, RAM0 0.44 0.46
retained
Deepstop, no timer,
wakeup GPIO, all 0.62 0.64
RAM retained
Deepstop (32 kHz
0.94 1.06
LSI), RAM0 retained
Deepstop (32 kHz
LSI), all RAMs 1.12 1.24
retained
Deepstop (32 kHz
0.64 0.75
LSE), RAM0 retained
Core current Deepstop (32 kHz
ICORE 0.83 0.94
consumption LSE), all RAM retained µA
CPU in Run (64 MHz).
Dhrystone, clock - 4482
source PLL64
CPU in WFI (64 MHz),
all peripherals off, - 2230
clock source PLL64
CPU in WFI (16 MHz),
all peripherals off,
- 757
clock source direct
HSE
Radio Rx at sensitivity
- 6700
level
Radio Tx 0 dBm
- 8900
output power

DS14676 - Rev 4 page 40/74

 STM32WB06xC STM32WB07xC
Electrical characteristics

Table 16. Peripheral current consumption at VDD = 3.3 V, sysclk at 32 MHz, SMPS on

Parameter Test conditions Typ. Unit

ADC - 80
DMA - 39
GPIOA - 2
GPIOB - 2
I2C1 - 40
I2C2 - 39
I2S2 Peripheral clock at 32 MHz 46
I2S3 Peripheral clock at 32 MHz 47
IWDG - 11
LPUART - 52
PVD - 0.8
PKA - 50 µA
RNG - 64
RTC - 14
SPI1 - 35
SPI2 Peripheral clock at 16 MHz 40
SPI3 Peripheral clock at 16 MHz 42
SysTick - 8
TIM1 - 248
USART - 81
SYSCFG - 33
THSENS - 301
CRC - 9

6.3.3 RF general characteristics

All performance data are referred to a 50 Ω antenna connector, via reference design.

DS14676 - Rev 4 page 41/74

 STM32WB06xC STM32WB07xC
Electrical characteristics

Table 17. Bluetooth Low Energy RF general characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

FRANGE Frequency range(1) - 2400 - 2483.5

MHz
RFCH RF channel center frequency(1) - 2402 - 2480

PLLRES RF channel spacing(1) - - 2 - MHz

ΔF Frequency deviation(1) - - 250 - kHz

Δf1 Frequency deviation average(1) - 450 - 550 kHz

During the packet and including both

CFdev Center frequency deviation(1) - - ±150 kHz
initial frequency offset and drift
Frequency deviation Δf2 (average) / Δf1
Δfa - 0.80 - - -
(average)(1)
Rgfsk On-air data rate(1) - 1 - 2 Mbps

STacc Symbol time accuracy(1) - - - ±50 ppm

MOD Modulation scheme - GFSK -

BT Bandwidth-bit period product - - 0.5 - -

Mindex Modulation index(1) - 0.45 0.5 0.55 -

At antenna connector, VSMPS = 1.9 V,

PMAX Maximum output - +8 - dBm
LDO code
PMIN Minimum output At antenna connector - -20 - dBm
@ 27 °C - ±1.5 -
PRFC RF power accuracy dB
All temperatures - ±2.5 -

1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).

6.3.4 RF transmitter characteristics

All performance data are referred to a 50 Ω antenna connector, via reference design.

Table 18. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps not coded

Symbol Parameter Test conditions Min. Typ. Max. Unit

6 dB bandwidth for modulated

PBW1M Using resolution bandwidth of 100 kHz 500 - - kHz
carrier
Using resolution bandwidth of 100 kHz and
PRF1, 1 Ms/s In-band emission at ±2 MHz(1) - - -20 dBm
average detector
In-band emission at ±[3+n]MHz, Using resolution bandwidth of 100 kHz and
PRF2, 1 Ms/s - - -30 dBm
where n=0,1,2..(1) average detector

Harmonics included. Using resolution

PSPUR Spurious emission - - -41 dBm
bandwidth of 1 MHz and average detector
Integration interval #n – integration interval
Freqdrift Frequency drift(1) -50 - +50 kHz
#0, where n=2,3,4..k
Integration interval #1 – integration interval
IFreqdrift Initial carrier frequency drift(1) -23 - +23 kHz
#0
Intermediate carrier frequency Integration interval #n – integration interval
IntFreqdrift -20 - +20 kHz
drift(1) #(n-5), where n=6,7,8..k

Between any two 10-bit groups separated by kHz/50

Drift Rate max Maximum drift rate(1) -20 - +20
50 µs µs
Optimum RF load
ZRF1 @ 2440 MHz - 40 - Ω
(impedance at RF1 pin)

DS14676 - Rev 4 page 42/74

 STM32WB06xC STM32WB07xC
Electrical characteristics

1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).

Table 19. Bluetooth Low Energy RF transmitter characteristics at 2 Mbps not coded

Symbol Parameter Test conditions Min. Typ. Max. Unit

6 dB bandwidth for modulated

PBW1M Using resolution bandwidth of 100 kHz 670 - - kHz
carrier
Using resolution bandwidth of 100 kHz and
PRF1, 2 Ms/s In-band emission at ±4 MHz(1) - - -20 dBm
average detector
Using resolution bandwidth of 100 kHz and
PRF2, 2 Ms/s In-band emission at±5 MHz(1) - - -20 dBm
average detector
In-band emission at ±[6+n]MHz, Using resolution bandwidth of 100 kHz and
PRF3, 2 Ms/s - - -30 dBm
where n=0,1,2..(1) average detector

Harmonics included. Using resolution

PSPUR Spurious emission - - -41 dBm
bandwidth of 1 MHz and average detector
Integration interval #n – integration interval
Freqdrift Frequency drift(1) -50 - +50 kHz
#0, where n=2,3,4..k
IFreqdrift Initial carrier frequency drift(1) Integration interval #1 – integration interval #0 -23 - +23 kHz

Intermediate carrier frequency Integration interval #n – integration interval

IntFreqdrift -20 - +20 kHz
drift(1) #(n-5), where n=6,7,8..k

Between any two 20-bit groups separated by

DriftRatemax Maximum drift rate(1) -20 - +20 kHz/50µs
50 µs
Optimum RF load
ZRF1 @ 2440 MHz - 40 - Ω
(impedance at RF1 pin)

1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).

Table 20. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps LE coded (S=8)

Symbol Parameter Test conditions Min. Typ. Max. Unit

6 dB bandwidth for modulated

PBW Using resolution bandwidth of 100 kHz 500 - - kHz
carrier
Using resolution bandwidth of 100 kHz and
PRF1, LE coded In-band emission at ±2 MHz(1) - - -20 dBm
average detector
In-band emission at ±[3+n] Using resolution bandwidth of 100 kHz and
PRF2, LE coded - - -30 dBm
MHz, where n=0,1,2..(1) average detector

Harmonics included. Using resolution

PSPUR Spurious emission - - -41 dBm
bandwidth of 1 MHz and average detector
Integration interval #n – integration interval
Freqdrift Frequency drift(1) -50 - +50 kHz
#0, where n=1,2,3..k
Integration interval #3 – integration interval
IFreqdrift Initial carrier frequency drift(1) -19.2 - +19.2 kHz
#0
Intermediate carrier frequency Integration interval #n – integration interval
IntFreqdrift -19.2 - +19.2 kHz
drift(1) #(n-3), where n=7,8,9..k

Between any two 16-bit groups separated kHz/48

DriftRatemax Maximum drift rate(1) -19.2 - +19.2
by 48 µs µs
Optimum RF load
ZRF1 @ 2440 MHz - 40 - Ω
(Impedance at RF1 pin)

1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).

6.3.5 RF receiver characteristics

All performance data are referred to a 50 Ω antenna connector, via reference design.

DS14676 - Rev 4 page 43/74

 STM32WB06xC STM32WB07xC
Electrical characteristics

Table 21. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s uncoded

Symbol Parameter Test conditions Min. Typ. Max. Unit

RXSENS Sensitivity PER < 30.8% - -97 - dBm

PSAT Saturation PER < 30.8% - 8 - dBm

Optimum RF source
ZRF1 @ 2440 MHz - 40 - Ω
(impedance at RF1 pin)
RF selectivity with Bluetooth® Low Energy equal modulation on interfering signal
Co-channel interference
C/ICO-channel Wanted signal = -67 dBm, PER < 30.8% - 8 - dBc
fRX = finterference

Adjacent interference
C/I1 MHz Wanted signal = -67 dBm, PER < 30.8% - -1 - dBc
finterference = fRX ± 1 MHz

Adjacent interference
C/I2 MHz Wanted signal = -67 dBm, PER < 30.8% - -35 - dBc
finterference = fRX ± 2 MHz

Adjacent interference
C/I3 MHz finterference = fRX ± (3+n) MHz Wanted signal = -67 dBm, PER < 30.8% - -47 - dBc
[n = 0,1,2…]
Image frequency interference
C/IImage Wanted signal = -67 dBm, PER < 30.8% - -25 - dBc
finterference = fimage

Adjacent channel-to-image frequency

C/IImage±1 MHz Wanted signal= -67 dBm, PER < 30.8% - -25 - dBc
finterference = fimage ± 1 MHz

Out of band blocking (interfering signal CW)

Interfering signal frequency 30 MHz – Wanted signal = -67 dBm, PER <
C/IBlock - 5 - dB
2000 MHz 30.8%, measurement resolution 10 MHz
Interfering signal frequency 2003 MHz – Wanted signal = -67 dBm, PER <
C/IBlock - -5 - dB
2399 MHz 30.8%, measurement resolution 3 MHz
Interfering signal frequency 2484 MHz – Wanted signal = -67 dBm, PER <
C/IBlock - -5 - dB
2997 MHz 30.8%, measurement resolution 3 MHz
Interfering signal frequency 3000 MHz – Wanted signal = -67 dBm, PER <
C/IBlock - 10 - dB
12.75 GHz 30.8%, measurement resolution 25 MHz
Intermodulation characteristics (CW signal at f1, Bluetooth® Low Energy interfering signal at f2)

Input power of IM interferer at 3 and 6

P_IM(3) Wanted signal = -64 dBm, PER < 30.8% - -27 - dBm
MHz distance from the wanted signal
Input power of IM interferer at -3 and -6
P_IM(-3) Wanted signal = -64 dBm, PER < 30.8% - -40 - dBm
MHz distance from the wanted signal
Input power of IM interferer at ±4 and ±8
P_IM(4) Wanted signal= -64 dBm, PER < 30.8% - -32 - dBm
MHz distance from the wanted signal
Input power of IM interferer at ±5 and ±10
P_IM(5) Wanted signal = -64 dBm, PER < 30.8% - -32 - dBm
MHz distance from the wanted signal

Table 22. Bluetooth® Low Energy RF receiver characteristics at 2 Msym/s uncoded

Symbol Parameter Test conditions Min. Typ. Max. Unit

RXSENS Sensitivity PER < 30.8% - -94 - dBm

PSAT Saturation PER < 30.8% - 8 - dBm

Optimum RF source
ZRF1 @ 2440 MHz - 40 - Ω
(impedance at RF1 pin)

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Symbol Parameter Test conditions Min. Typ. Max. Unit

RF selectivity with Bluetooth® Low Energy equal modulation on interfering signal

Co-channel interference
C/ICO-channel Wanted signal= -67 dBm, PER < 30.8% - 8 - dBc
fRX = finterference

Adjacent interference Wanted signal = -67 dBm, PER <

C/I2 MHz - -14 - dBc
finterference = fRX ± 2 MHz 30.8%

Adjacent interference Wanted signal = -67 dBm, PER <

C/I4 MHz - -41 - dBc
finterference = fRX ± 4 MHz 30.8%

Adjacent interference
Wanted signal = -67 dBm, PER <
C/I6 MHz finterference = fRX ± (6+2n) MHz - -45 - dBc
30.8%
[n = 0,1,2…]
Image frequency interference Wanted signal = -67 dBm, PER <
C/IImage - -25 - dBc
finterference = fimage-2M 30.8%

Adjacent channel-to-image frequency -

C/IImage±1 MHz Wanted signal= -67 dBm, PER < 30.8% -14 - dBc
finterference = fimage-2M ± 2 MHz -

Out of band blocking (interfering signal CW)

Wanted signal= -67 dBm, PER <
Interfering signal frequency 30 MHz –
C/IBlock 30.8%, measurement resolution 10 - 5 - dB
2000 MHz
MHz
Interfering signal frequency 2003 MHz – Wanted signal= -67 dBm, PER <
C/IBlock - -5 - dB
2399 MHz 30.8%, measurement resolution 3 MHz
Interfering signal frequency 2484 MHz – Wanted signal= -67 dBm, PER <
C/IBlock - -5 - dB
2997 MHz 30.8%, measurement resolution 3 MHz
Wanted signal= -67 dBm, PER <
Interfering signal frequency 3000 MHz –
C/IBlock 30.8%, measurement resolution 25 - 10 - dB
12.75 GHz
MHz
Intermodulation characteristics (CW signal at f1, Bluetooth® Low Energy interfering signal at f2)

Input power of IM interferer at 6 and 12

P_IM(6) Wanted signal= -64 dBm, PER < 30.8% - -27 - dBm
MHz distance from the wanted signal
Input power of IM interferer at -6 and -12
P_IM(-6) Wanted signal= -64 dBm, PER < 30.8% - -30 - dBm
MHz distance from the wanted signal
Input power of IM interferer at ±8 and ±16
P_IM(8) Wanted signal= -64 dBm, PER < 30.8% - -30 - dBm
MHz distance from the wanted signal
Input power of IM interferer at ±10 and ±20
P_IM(10) Wanted signal= -64 dBm, PER < 30.8% - -28 - dBm
MHz distance from the wanted signal

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Table 23. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=2)

Symbol Parameter Test conditions Min. Typ. Max. Unit

RXSENS Sensitivity PER < 30.8% -100 - dBm

PSAT Saturation PER < 30.8% 8 - dBm

-
Optimum RF source
ZRF1 @ 2440 MHz 40 - Ω
(impedance at RF1 pin)
RF selectivity with Bluetooth® Low Energy equal modulation on interfering signal -
Co-channel interference
C/ICO-channel Wanted signal = -79 dBm, PER < 30.8% 2 - dBc
fRX = finterference

Adjacent interference
C/I1 MHz Wanted signal = -79 dBm, PER < 30.8% -5 - dBc
finterference = fRX ± 1 MHz

Adjacent interference
C/I2 MHz Wanted signal = -79 dBm, PER < 30.8% -38 - dBc
finterference = fRX ± 2 MHz

Adjacent interference -
C/I3 MHz finterference = fRX ± (3+n) MHz Wanted signal = -79 dBm, PER < 30.8% -50 - dBc
[n = 0,1,2…]
Image frequency interference
C/IImage Wanted signal = -79 dBm, PER < 30.8% -30 - dBc
finterference = fimage

Adjacent channel-to-image frequency

C/IImage±1 MHz Wanted signal = -79 dBm, PER < 30.8% -34 - dBc
finterference = fimage ± 1 MHz

Table 24. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=8)

Symbol Parameter Test conditions Min. Typ. Max. Unit

RXSENS Sensitivity PER < 30.8% -104 - dBm

PSAT Saturation PER < 30.8% 8 - dBm

-
Optimum RF source
ZRF1 @ 2440 MHz 40 - Ω
(impedance at RF1 pin)
RF selectivity with Bluetooth® Low Energy equal modulation on interfering signal -
Co-channel interference
C/ICO-channel Wanted signal = -79 dBm, PER < 30.8% 1 - dBc
fRX = finterference

Adjacent interference
C/I1 MHz Wanted signal = -79 dBm, PER < 30.8% -4 - dBc
finterference = fRX ± 1 MHz

Adjacent interference
C/I2 MHz Wanted signal = -79 dBm, PER < 30.8% -39 - dBc
finterference = fRX ± 2 MHz

Adjacent interference -
C/I3 MHz finterference = fRX ± (3+n) MHz Wanted signal = -79 dBm, PER < 30.8% -53 - dBc
[n = 0,1,2…]
Image frequency interference
C/IImage Wanted signal = -79 dBm, PER < 30.8% -33 - dBc
finterference = fimage

Adjacent channel-to-image frequency

C/IImage ± 1 MHz Wanted signal = -79 dBm, PER < 30.8% -32 - dBc
finterference = fimage ± 1 MHz

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6.3.6 Embedded reset and power control block characteristics

Table 25. Embedded reset and power control block characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Reset temporization after PDR

TRSTTEMPO VDD rising - - 500 us
is detected
VPDR Power-down reset threshold - - 1.63 -
VPVD0 PVD0 threshold PVD0 threshold at the falling edge of VDDIO - 2.05 -
VPVD1 PVD1 threshold PVD1 threshold at the falling edge of VDDIO - 2.21 -
VPVD2 PVD2 threshold PVD2 threshold at the falling edge of VDDIO - 2.36 -
VPVD3 PVD3 threshold PVD3 threshold at the falling edge of VDDIO - 2.53 -
V
VPVD4 PVD4 threshold PVD4 threshold at the falling edge of VDDIO - 2.64 -
VPVD5 PVD5 threshold PVD5 threshold at the falling edge of VDDIO - 2.82 -
VPVD6 PVD6 threshold PVD6 threshold at the falling edge of VDDIO - 2.91 -
PVD7 threshold (VBGP) at the falling edge of
VPVD7 PVD threshold for VIN_PVD - 1.2 -
VIN_PVD

6.3.7 Supply current characteristics

The current consumption is a function of several parameters and factors such as: the operating voltage, ambient
temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program
location in memory and executed binary code.
The MCU is put under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait state number
• When the peripherals are enabled fPCLK = fHCLK

Table 26. Current consumption

Typ.
Symbol Parameter Conditions Unit
25°C 85 °C 105 °C

fHCLK = 64 MHz
2.40 2.49 2.54
All peripherals disabled
fHCLK = 32 MHz
IDD(Run) Supply current in Run mode 1.98 2.03 2.08 mA
All peripherals disabled
fHCLK = 16 MHz
1.62 1.67 1.71
All peripherals disabled
Timer OFF 0.65 6.73 15.73
Timer source LSI 1.25 7.41 16.46
Timer source LSI
1.30 7.56 16.70
RTC ON
IDD(Deepstop) Supply current in Deepstop(1) µA
Timer source LSI
1.27 7.47 16.55
IWDG ON
Timer source LSI
1.33 7.61 16.79
RTC and IWDG ON

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Typ.
Symbol Parameter Conditions Unit
25°C 85 °C 105 °C

Timer source LSE 1.00 7.16 16.22

Timer source LSE
1.06 7.31 16.45
RTC ON
IDD(Deepstop) Supply current in Deepstop(1) Timer source LSE
1.02 7.22 16.30 µA
IWDG ON
Timer source LSE
1.07 7.36 16.54
RTC and IWDG ON
IDD(Shutdown) Supply current in Shutdown - 0.02 0.46 1.36

IDD(RST) Current under reset condition - 1.34 1.45 1.55 mA

1. The current consumption in Deepstop is measured considering the entire SRAM retained.

6.3.8 Wakeup time from low power modes

The wakeup times reported are the latency between the event and the execution of the instruction. The device
goes to low-power mode after WFI (wait for interrupt) instructions.

Table 27. Low power mode wakeup timing

Symbol Parameter Conditions Typ. Unit

TWUDEEPSTOP Wakeup time from Deepstop mode to Run mode Wakeup from GPIO VDD = 3.3 V flash memory 110 µs

6.3.9 External clock source characteristics

6.3.9.1 High speed crystal requirements

The high speed external oscillator must be supplied with an external 32 MHz crystal that is specified for a 6 to 8
pF loading capacitor. The STM32WB0xxC includes internal programmable capacitances that can be used to tune
the crystal frequency to compensate the PCB parasitic one. These internal load capacitors are made by a fixed
one, in parallel with a 6-bit binary weighted capacitor bank. Thanks to the low CL step size (LSB is typically 0.07
pF), very fine crystal tuning is possible. With a typical XTAL sensitivity of -14 ppm/pF, it is possible to trim a 32
MHz crystal, with a resolution of 1 ppm.
The requirements for the external 32 MHz crystal are reported in the table below.

Table 28. HSE crystal requirements

Symbol Parameter Conditions Min. Typ. Max. Unit

fNOM Oscillator frequency - - 32 - MHz

Includes initial accuracy, stability over temperature,

fTOL Frequency tolerance aging, and frequency pulling due to incorrect load - - ±50 ppm
capacitance
ESR Equivalent series resistance - - - 100 Ω
PD Drive level - - - 100 µW

27°C, typical corner

CL HSE crystal load capacitance 5 (1) 7(2) 9.2(3) pF
GMCONF = 3
27 °C,
HSE crystal load capacitance
CLstep GMCONF = 3 - 0.07 - pF
LSB value
XOTUNE code between 32 and 33

1. XOTUNE programmed at minimum code = 0

2. XOTUNE programmed at center code = 32

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3. XOTUNE programmed at maximum code = 63

6.3.9.2 Low speed crystal requirements

A low speed clock can be supplied with an external 32.768 kHz crystal oscillator. Requirements for the external
32.768 kHz crystal are reported in the table below.

Table 29. LSE crystal requirements

Symbol Parameter Conditions Min. Typ. Max. Unit

fNOM Nominal frequency - - 32.768 - kHz

ESR Equivalent series resistance - - - 90 kΩ

PD Drive level - - - 0.1 µW

LSEDRV[1:0] = 00
- - 0.50
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Medium low drive capability
Gmcritmax Maximum critical crystal gm μA/V
LSEDRV[1:0] = 10
- - 1.70
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.70
High drive capability

6.3.10 Internal clock source characteristics

6.3.10.1 High speed ring oscillator characteristics

Table 30. HSI oscillator characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

Nominal
fNOM - - 64 - MHz
frequency

6.3.10.2 Low speed ring oscillator characteristics

Table 31. LSI oscillator characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

fNOM Nominal frequency - - 33 - kHz

ΔFRO_ΔT/FRO Frequency spread vs. temperature Standard deviation - 140 - ppm/ºC

6.3.11 PLL characteristics

Characteristics measured over recommended operating conditions unless otherwise specified.

Table 32. PLL characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

At ±1 MHz offset from carrier

PNSYNTH RF carrier phase noise - -110 - dBc/Hz
(measured at 2.4 GHz)

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Symbol Parameter Conditions Min. Typ. Max. Unit

At 2.4 GHz ±3 MHz offset from carrier

- -114 - dBc/Hz
(measured at 2.4 GHz)
PNSYNTH RF carrier phase noise At 2.4 GHz±6 MHz offset from carrier
- -128 - dBc/Hz
(measured at 2.4 GHz)
At ±25 MHz offset from carrier - -135 - dBc/Hz
LOCKTIMETX PLL lock time to TX With calibration @2.5 ppm - 150 - µs

LOCKTIMERX PLL lock time to RX With calibration @2.5 ppm - 110 - µs

LOCKTIMERXTX PLL lock time RX to TX Without calibration @2.5 ppm - 47 - µs

LOCKTIMETXRX PLL lock time TX to RX Without calibration @2.5 ppm - 32 - µs

6.3.12 Flash memory characteristics

The characteristics below are specified by design - not tested in production.

Table 33. Flash memory characteristics

Symbol Parameter Test conditions Typ. Max. Unit

tprog 32-bit programming time - 20 40

µs
tprog_burst 4x32-bit burst programming time - 4x20 4x40

tERASE Page (2 kbytes) erase time - 20 40

ms
tME Mass erase time - 20 40

Write mode 3 -
IDD Average consumption from VDD Erase mode 3 - mA
Mass erase 5 -

Table 34. Flash memory endurance and data retention

Symbol Parameter Test conditions Min. Unit

NEND Endurance TA = -40 to +105 ºC 10 kcycles

tRET Data retention TA = 105 ºC 10 Years

6.3.13 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each
sample according to each pin combination. The sample size depends on the number of supply pins in the device
(3 parts x (n + 1) supply pins). This test conforms to the ANSI/JEDEC standard.

Table 35. ESD absolute maximum ratings

Symbol Parameter Conditions Class Max.(1) Unit

Electrostatic discharge voltage (human body

VESD(HBM) Conforming to ANSI/ESDA/JEDEC JS-001 2 2000
model)
V
Electrostatic discharge voltage (charge Conforming to ANSI/ESDA/STM5.3.1
VESD(CBM) C2a 500
device model) JS-002

1. Guaranteed by design.

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6.3.14 I/O port characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests performed under the
conditions summarized in General operating conditions. All I/Os are designed as CMOS-compliant.
The characteristics below are guaranteed by characterization.

Table 36. I/O static characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

VIL I/O input low level voltage - - 0.3 x VDD

1.62 V < VDD < 3.6 V V
VIH I/O input high level voltage 0.7 x VDD - -

0 <= VIN <= Max(VDDx)(1) - - +/-100

Ilkg Input leakage current Max(VDDx)(1) <= VIN <= Max(VDDx)(1) +1 V - - 650 nA

Max(VDDx)(1) + 1 V < VIN <= 5.5 V - - 200

RPU Pull-up resistor VIN = GND 25 40 55

kΩ
RPD Pull-down resistor VIN = VDD 25 40 55

CIO I/O pin capacitance - - 5 - pF

1. Max(VDDx) is the maximum value among all the I/O supplies.

All I/Os are CMOS-compliant (no software configuration required).

GPIOs (general purpose input/outputs) can sink or source up to ±8 mA and sink or source up to ± 20 mA (with a
relaxed VOL / VOH).
In the user application, the number of I/O pins that can drive current must be limited to respect the absolute
maximum rating specified.
• The sum of currents sourced by all I/Os on VDD, plus the maximum consumption of MCU sourced on VDD,
cannot exceed the absolute maximum rating ΣIVDD
• The sum of currents sunk by all I/Os on VSS, plus the maximum consumption of the MCU sunk on GND,
cannot exceed the absolute maximum rating ΣIVGND
The characteristics below are guaranteed by characterization.

Table 37. Output voltage characteristics

Symbol Parameter Conditions Min. Max. Unit

VOL Output low level voltage for I/O pin - 0.4

CMOS port(1) |IIO| = 8 mA VDD ≥ 2.7 V
VOH Output high level voltage for I/O pin VDD -0.4 -

VOL Output low level voltage for I/O pin - 1.3

|IIO| = 20 mA VDD ≥ 2.7 V V
VOH Output high level voltage for I/O pin VDD -1.3 -

VOL Output low level voltage for I/O pin - 0.4

|IIO| = 4 mA VDD ≥ 1.62 V
VOH Output high level voltage for I/O pin VDD-0.45 -

1. CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

6.3.15 RSTN pin characteristics

The RSTN pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in General operating conditions.
The characteristics below are specified by design - not tested in production.

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Table 38. RSTN pin characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit.

VIL(RSTN) RSTN input low level voltage - - - 0.3 x VDD

V
VIH(RSTN) RSTN input high level voltage - 0.7 x VDD - -

Vhys(RSTN) RSTN Schmitt trigger voltage hysteresis - - 200 - mV

RPU Weak pull-up equivalent resistor VIN=GND 25 40 55 kΩ

Figure 15. Recommended RSTN pin protection

Note: The external reset circuit protects the device against parasitic resets.
The user must ensure that the level on the RSTN pin can go below the VIL(RSTN) max. level specified in the
table, otherwise the reset is not considered by the device. The external capacitor on RSTN must be placed as
close as possible to the device.

6.3.16 ADC characteristics

Table 39. ADC characteristics (HSI must be set to PLL mode)

Symbol Parameter Test conditions Min. Typ. Max. Units

Number of channels for

Ch_diff_num VFQFPN48, WLCSP49 - - 4 -
differential mode
Number of channels for single
Ch_se_num VFQFPN48, WLCSP49 - - 8 -
ended mode
ADC biasing consumption at
IBATADCBIAS Biasing blocks turned on - 145 - µA
battery
ADC active consumption at
IBATADCACTIVE ADC activated in differential mode - 185 - µA
battery
VDDA Analog supply voltage - 1.2 - 1.32 V
RAIN Input impedance In DC - 250 - kΩ

Rin Internal access resistance VBOOST is enabled for VDD < 2.7 V - - 550 Ω

Cin Input sampling capacitor - - 4 - pF

Ts Sampling period Default configuration - 1 - µs

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Symbol Parameter Test conditions Min. Typ. Max. Units

Tsw Sampling time Default configuration - 125 - ns

DR Output data rate - - 200 - k samples/s

FRMToutput Output data format - - 16 - bits

TL Latency time 200 kSps - 5 - µs

TSTARTUP Start-up time From ADC enable to conversion start - - 1 µs

DNL Differential non-linearity - - ±0.7 - LSB

INL Integral non-linearity - - ±1 - LSB
Differential input
SNR Diff Signal to noise ratio - 72 - dB
@1 kHz, -1 dBFs, Fs = 1 MHz with DF

Signal to THD ratio (10 Differential input

STHD Diff - 75 - dB
harmonics) @1 kHz, -1 dBFs, Fs = 1 MHz with DF
Differential input
ENOB Diff Effective number of bits - 11.5 - bits
@1 kHz, -1 dBFs, Fs = 1 MHz with DF
Single ended
SNR SE Signal-to-noise ratio - 70 - dB
@1 kHz, -1 dBFs, Fs = 1 MHz with DF

Signal-to THD ratio (10 Single ended

STHD SE - 70 - dB
harmonics) @1 kHz, -1 dBFs, Fs = 1 MHz with DF
Single ended
ENOB SE Effective number of bits - 11 - bits
@1 kHz, -1 dBFs, Fs = 1 MHz with DF
- ADC_ERR_1V7 - 13 -
- ADC_ERR_2V4 Absolute error when used for battery - 0 -
mV
- ADC_ERR_3V0 measurements at 1.7 V, 2.4 V, 3.0 V, 3.6 V - -9 -
- ADC_ERR_3V6 - -22 -

6.3.17 Temperature sensor characteristics

Table 40. Temperature sensor characteristics

Symbol Parameter Min. Typ. Max. Unit

TrERR Error in temperature - ±4 - °C

TSLOPE Average temperature coefficient - 8 - LSB/°C

TICC Current consumption - 415 - µA

TTS-OUT Output code at 30 °C (+/-5 °C) - 2533 - LSB

6.3.18 Timer characteristics

The characteristics below are guaranteed by design.

Table 41. TIM1 characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

tres(TIM) Timer resolution time fTIMxCLK = 64 MHz - 15.625 - ns

ResTIM Timer resolution - - 16 - bit

tCOUNTER 16-bit counter clock period fTIMxCLK = 64 MHz 0.015625 - 1024 μs

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Symbol Parameter Test conditions Min. Typ. Max. Unit

tMAX_COUNT Maximum possible count time fTIMxCLK= 64 - - 67.10 s

Table 42. IWDG min./max. timeout period at 32 kHz (LSE)

Prescaler divider PR[2:0] bits Min. timeout RL[11:0] = 0x000 Max. timeout RL[11:0] = 0xFFF Unit

/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768

6.3.19 I2C interface characteristics

The I2C interface meets the timing requirements of the I2C-Bus specifications and user manual rev. 03 for:
• Standard-mode (Sm): bit rate up to 100 kbit/s
• Fast-mode (Fm): bit rate up to 400 kbit/s
• Fast-mode plus (Fm+): bit rate up to 1 Mbit/s
SDA and SCL I/O requirements are met with the following restrictions: SDA and SCL I/O pins are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still
present. The 20 mA output drive requirement in fast-mode plus is supported partially.
This limits the maximum load Cload supported in fast-mode plus, given by these formulas:
• tr(SDA/SCL) = 0.8473 x Rp x Cload
• Rp(min.) = [VDD - VOL(max)] / IOL(max)
where Rp is the I2C lines pull-up.
All I2C SDA and SCL I/Os embed an analog filter.
The characteristics below are guaranteed by design.

Table 43. I2C analog filter characteristics

Symbol Parameter Min. Max. Unit

tAF Maximum pulse width of spikes that are suppressed by the analog filter 50 110 ns

6.3.20 SPI characteristics

The parameters for SPI are derived from tests performed according to fPCLKx frequency and supply voltage
conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD
The characteristics below are specified by design - not tested in production.

Table 44. SPI characteristics

Symbol Parameter Conditions Min. Typ. Max. Units

fSCK SPI clock frequency Controller mode - - 32 MHz

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Symbol Parameter Conditions Min. Typ. Max. Units

fSCK SPI clock frequency Target mode - - 32(1) MHz

tsu(NSS) NSS setup time - 4 / fPCLK - - -

th(NSS) NSS hold time - 2 / fPCLK - - -

tw(SCKH) 1 / fPCLK - 1.5 1 / fPCLK 1 / fPCLK+1

SCK high and low time Controller mode
tw(SCKL) 1 / fPCLK- 1.5 1 / fPCLK 1 / fPCLK+1

tsu(MI) Data input set-up time Controller mode 1 - -

tsu(SI) Data input set-up time Target mode 1 - -
th(MI) Data input hold time Controller mode 3 - -
th(SI) Data input hold time Target mode 1 - -
ns
ta(SO) Data output access time Target mode 5 - 40

tdis(SO) Data output disable time Target mode 5 - 38

tv(MO) Controller mode - 2 8

Data output valid time
tv(SO) Target mode - 12 39

th(MO) Controller mode 2 -

Data output hold time -
th(SO) Target mode 4 -

1. The maximum frequency in target transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit SCK
low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
controller having tsu(MI) = 0 while duty(SCK) = 50 %.

Figure 16. SPI timing diagram - target mode and CPHA = 0

DT57476V1

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Figure 17. SPI timing diagram - target mode and CPHA = 1

DT57477V1
Figure 18. SPI timing diagram - controller mode

DT57478V1

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Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

7.1 Device marking

Refer to technical note "Reference device marking schematics for STM32 microcontrollers and microprocessors"
(TN1433 ) available on www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation of the
marking areas versus pin 1 / ball A1.
Parts marked as "ES", "E" or accompanied by an engineering sample notification letter, are not yet qualified and
therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package information subsection.

DS14676 - Rev 4 page 57/74

 STM32WB06xC STM32WB07xC
Package information

7.2 VFQFPN32 package information (42)

This VFQFPN is a 32 lead, 5 x 5 mm, 0.50 mm pitch, very fine pitch quad flat no lead package.

Figure 19. VFQFPN32 - Outline

ddd C
SEATNG PLANE

A1
A3
SIDE VIEW

17 e
8

b
E2 E

24 L

42_VFQFPN32_CALAMBA_ME_V1
PIN #1 ID 32 25
CHAMFER 0.35
b L

D2

BOTTOM VIEW

1. Drawing is not to scale.

2. Package outline exclusive of any mold flashes dimensions and metal burrs.
3. Details of terminal 1 are optional but must be located on the top surface of the package by using either a mold
or marked features.

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 STM32WB06xC STM32WB07xC
Package information

Table 45. VFQFPN32 - Mechanical data

Millimetres Inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0 - 0.05 0 - 0.0020
A3 - 0.20 - - 0.008 -
b 0.18 0.25 0.30 0.0070 0.0098 0.0118
D 4.90 5.00 5.10 0.1929 0.19 0.2008
E 4.90 5.00 5.10 0.1929 0.19 0.2008
D2 3.60 3.70 3.80 0.1417 0.1457 0.1496
E2 3.60 3.70 3.80 0.1417 0.1457 0.1496
e - 0.50 - - 0.0197 -
L 0.30 0.40 0.50 0.0118 0.0157 0.0197
ddd - - 0.05 - - 0.0020

1. Values in inches are converted from mm and rounded to 3 decimal digits.

2. VFQFPN stands for thermally Enhanced very thin fine pitch quad flat package No lead . Very thin profile 0.80 < A ≤ 1.00
mm.

Figure 20. VFQFPN32 - Footprint example

3.50

0.80
0.25

0.25

0.50
3.50 5.70

42_VFQFPN32_CALAMBA_FP_V1

4.10
0.30

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 STM32WB06xC STM32WB07xC
Package information

7.3 VFQFPN48 package information

This VFQFPN is a 48 lead, 6 x 6 mm, 0.40 mm pitch, very fine pitch quad flat no lead package.

Figure 21. VFQFPN48 - Outline

A D
B
48

PIN 1 CORNER

TOP VIEW E

ccc C

bbb C A2
SIDE VIEW A
ccc C

A3
C SEATING PLANE

37 48
PIN 1 ID

36
1

BOTTOM VIEW D1
eee C AB e/2
E1
A0BE_D_VFQFPN48_ME_V1

25

13
48x L
48x b
ddd C AB
EXPOSED DIE
ATTACH PAD

1. Drawing is not to scale.

2. Dimension and tolerances conform to ASME Y14.5M.
3. Coplanarity applies to leads , corner leads and die attach pad.

DS14676 - Rev 4 page 60/74

 STM32WB06xC STM32WB07xC
Package information

Table 46. VFQFPN48 - Mechanical data

Millimetres Inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.80 0.85 0.90 0.0315 0.0335 0.0354

A1 0 0.035 0.05 0 0.0014 0.0020
A2 - 0.65 0.67 - 0.0256 0.0264
A3 0.203 Ref 0.0080 Ref
b 0.15 0.20 0.25 0.006 0.0080 0.0098
D 6.00 BSC 0.2362 BSC
D1 4.30 4.40 4.50 0.1693 0.1732 0.1772
E 6.00 BSC 0.2362 BSC
E1 4.30 4.40 4.50 0.1693 0.1732 0.1772
e - 0.40 BSC - - 0.0157 BSC -
L 0.40 0.45 0.50 0.0157 0.0177 0.0197
aaa 0.10 0.0039
bbb 0.10 0.0039
ccc 0.08 0.0031
ddd 0.10 0.0039

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 22. VFQFPN48- Footprint example

4.70

37
48
0.65
PIN 1 ID
0.30
36

0.40
4.50

4.70

12 25
A0BE_D_VFQFPN48_FP_V1

13 24

4.50

DS14676 - Rev 4 page 61/74

 STM32WB06xC STM32WB07xC
Package information

7.4 WLCSP49 package information( 01C1)

This WLCSP is a 49-ball, 3.140 x 3.140 mm, 0.40 mm pitch, wafer level chip scale array package.

Figure 23. WLCSP49 - Outline

fH A1 BALL LOCATION
fD
D1 (1)

e fE

A
B
e
C
D E1

E
F
G
fG
7 6 5 4 3 2 1

BOTTOM VIEW

A1
C b A

ccc C A2
A3
FRONT VIEW

01C1_WLCSP49_ME_V1

TOP VIEW

1. The terminal A1 on the bumps side is identified by a distinguishing feature (for instance by a circular "clear
area" - typically 0.1 mm diameter) and/or a missing bump.
The terminal A1 on the backside of the product is identified by a distinguishing feature (for instance by a
circular "clear area" - typically 0.5 mm diameter).
2. Drawing is not to scale.

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 STM32WB06xC STM32WB07xC
Package information

Table 47. WLCSP49 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 0.420 - - 0.0165
A1 0.135 - - 0.0053 - -
A2 - 0.225 - - 0.0088 -
A3 - 0.025 - - 0.0010 -
b 0.214 0.218 0.222 0.0084 0.0085 0.0087
D - 3.140 - - 0.1236 -
D1 - 2.400 - - 0.0945 -
E - 3.140 - - 0.1236 -
E1 - 2.400 - - 0.0945 -
e - 0.40 - - 0.0157 -
fD - 0.416 - - 0.0164 -
fE - 0.263 - - 0.0103 -
fG - 0.477 - - 0.0188 -
fH - 0.324 - - 0.0127 -
aaa - 0.023 - - 0.0009 -

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 24. WLCSP49 - Footprint example

2.40
0.40
0.202

F Dpad
Dsm
0.10
7

E
2.40

C
0.40

01C1_WLCSP49_FP_V1

7 6 5 4 3 2 1
Grid placement area

1. Dimensions are expressed in millimeters.

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 STM32WB06xC STM32WB07xC
Package information

Table 48. WLCSP49 - Example of PCB design rules

Dimension Values

Pitch 0.4 mm
Dpad 0,225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm

7.4.1 Device marking for WLCSP49

The following figure gives an example of topside marking versus ball A1 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 25. WLCSP49 marking example

Dot

Product identification(1)

Revision code

Y WW

DT58390
Date code

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting from
such use. In no event will ST be liable for the customer using any of these engineering samples in production.
ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a
qualification activity.

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 STM32WB06xC STM32WB07xC
Package information

7.5 Thermal characteristics

The maximum chip junction temperature (TJmax.) must never exceed the values in general operating conditions.
The maximum chip-junction temperature, TJ max., in degrees Celsius, can be calculated using the equation:

T Jmax . = TAmax. + PDmax × θJA (1)

where:
• TA max. is the maximum ambient temperature in °C
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W
• PD max. is the sum of PINT max. and PI/O max. (PD max. = PINT max. + PI/O max.)
• PINT max. is the product of IDD and VDD, expressed in Watt. This is the maximum chip internal power
PI/O max represents the maximum power dissipation on output pins:
• PI/O max. = Σ (VOL × IOL) + Σ ((VDD – VOH) × IOH)
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the applications.
Note: When the SMPS is used, a portion of the power consumption is dissipated into the external inductor, therefore
reducing the chip power dissipation. This portion depends mainly on the inductor ESR characteristics.
Note: As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the chip power
consumption.
Note: RF characteristics (such as: sensitivity, Tx power, consumption) are provided up to 85 °C.

Table 49. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

25.1
VFQFPN48 – 6 mm x 6 mm
Thermal resistance junction-ambient
ΘJA 26.9 ºC/W
VFQFPN32 - 5 mm x 5 mm
Thermal resistance junction-ambient
-
WLCSP49 – 0.4 mm pitch

7.5.1 Reference documents

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
available on www.jedec.org.
• For information on thermal management, refer to application note "Guidelines for thermal management on
STM32 applications" (AN5036) available on www.st.com.

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 STM32WB06xC STM32WB07xC
Ordering information

8 Ordering information

Example: STM32 WB 07 K C V 6 TR TR

Device family
STM32 = Arm®-based 32-bit
microcontroller

Product type
WB = wireless Bluetooth

Device subfamily
07 = full set of features (64 KB RAM)
06 = full set of features (32 KB RAM)

Pin count
K = 32 pins
C = 48 pins

Flash memory size

C = 256 Kbytes

Package
F = WLCSP ECOPACK2
V = VFQFPN ECOPACK2

Temperature range
6 = industrial temperature range, –40 to 85 °C
7 = industrial temperature range, –40 to 105 °C

Packing
TR = tape and reel

Note: For a list of available options (such as speed and package) or for further information on any aspect of this
device, contact your nearest ST sales office.

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 STM32WB06xC STM32WB07xC
Ordering information

Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST
product(s) identified in this documentation may be certified by various security certification bodies and/or may
implement our own security measures as set forth herein. However, no level of security certification and/or built-in
security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the
customer needs both in relation to the ST product alone, as well as when combined with other components and/or
software for the customer end product or application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such as Platform
Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms
(www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received
security certification along with the level and current status of such certification, either visit the relevant
certification standards website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can change from time to
time, customers should re-check security certification status/level as needed. If an ST product is not shown
to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST
products. These certification bodies are therefore independently responsible for granting or revoking
security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations,
assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard
technologies which may be used in conjunction with an ST product are based on standards which were not
developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open
technologies or for any methods which have been or may be developed to bypass, decrypt or crack such
algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections
against all attacks, including, for example, against advanced attacks which have not been tested for,
against new or unidentified forms of attack, or against any form of attack when using an ST product outside
of its specification or intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance against such
attacks. As such, regardless of the incorporated security features and/or any information or support that
may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for
meets their needs, both in relation to the ST product alone and when incorporated into a customer end
product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like),
including but not limited to any enhanced security features added by ST, are provided on an "AS IS"
BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL
WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

DS14676 - Rev 4 page 67/74

 STM32WB06xC STM32WB07xC

Revision history
Table 50. Document revision history

Date Revision Changes

13-Jun-2024 1 Initial release.

04-Sep-2024 2 Updated VFQFPN32 package information
Updated:
• Table 6. STM32WB0xxC pin/ball definition
26-Sep-2024 3
• Table 7. Alternate function port A
• Table 8. Alternate function port B
13-Feb-2025 4 Updated Table 5. Legend/abbreviations used in the pinout table

DS14676 - Rev 4 page 68/74

 STM32WB06xC STM32WB07xC
Contents

Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 ARM Cortex–M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Memory protection unit (MPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.1 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.3 Embedded ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.4 Embedded OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Radio system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6.1 RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7.3 SMPS step-down regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7.4 Linear voltage regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8.2 Deepstop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8.3 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.9 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.9.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.10 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10.1 Reset management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10.2 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.11 General purpose inputs/outputs (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.1 Tx and Rx event alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.12 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13.1 Nested vectored interrupt controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14 Analog digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14.1 Digital MEMS microphone interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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 STM32WB06xC STM32WB07xC
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3.14.2 Analog microphone interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.14.3 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.16 Timers and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.16.1 Advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.16.2 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.16.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.17 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.17.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.18 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.19 Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . . . . . . . . . 21
3.19.1 Embedded UART bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.20 LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.21.1 Inter-IC sound (I2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.22 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.22.1 Serial wire debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Pinouts/ballouts, pin description, and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . .24
4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.2 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.3 RF general characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.4 RF transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.5 RF receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3.6 Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 47

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6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.3.8 Wakeup time from low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.12 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.13 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.15 RSTN pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.16 ADC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.17 Temperature sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.19 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.20 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.2 VFQFPN32 package information (42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.3 VFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.4 WLCSP49 package information( 01C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.4.1 Device marking for WLCSP49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.5.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

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List of tables

List of tables
Table 1. Device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. SRAM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. IPDs for STM32WB0xxC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Relationship between the low power modes and functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. STM32WB0xxC pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Alternate function port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. Alternate function port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9. Application circuit external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 11. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. Main performance SMPS ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Main performance SMPS bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Peripheral current consumption at VDD = 3.3 V, sysclk at 32 MHz, SMPS on. . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. Bluetooth Low Energy RF general characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 18. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps not coded. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. Bluetooth Low Energy RF transmitter characteristics at 2 Mbps not coded. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps LE coded (S=8) . . . . . . . . . . . . . . . . . . . . . . . 43
Table 21. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s uncoded. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 22. Bluetooth® Low Energy RF receiver characteristics at 2 Msym/s uncoded. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 23. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=2). . . . . . . . . . . . . . . . . . . . . . . 46
Table 24. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=8). . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 27. Low power mode wakeup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 28. HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 29. LSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 30. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 32. PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 33. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 34. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 36. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 37. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 38. RSTN pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 39. ADC characteristics (HSI must be set to PLL mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 40. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 41. TIM1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 42. IWDG min./max. timeout period at 32 kHz (LSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 43. I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 44. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 45. VFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 46. VFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 47. WLCSP49 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 48. WLCSP49 - Example of PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 49. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 50. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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List of figures

List of figures
Figure 1. STM32WB0xxC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. STM32WB0xxC RF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. Power supply domain overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Power supply configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. VFQFPN48 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. VFQFPN32 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. WLCSP49 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. Application circuit: DC-DC converter, VFQFPN48 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Application circuit: DC-DC converter, WLCSP49 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. Application circuit: DC-DC converter, VFQFPN32 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 14. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 15. Recommended RSTN pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 16. SPI timing diagram - target mode and CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 17. SPI timing diagram - target mode and CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 18. SPI timing diagram - controller mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 19. VFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 20. VFQFPN32 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 21. VFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 22. VFQFPN48- Footprint example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 23. WLCSP49 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 24. WLCSP49 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 25. WLCSP49 marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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 STM32WB06xC STM32WB07xC

IMPORTANT NOTICE – READ CAREFULLY

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2025 STMicroelectronics – All rights reserved

DS14676 - Rev 4 page 74/74