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Analog Electronics - GATE Full Syllabus Test Paper

The document contains a series of questions and answers related to analog electronics, specifically focusing on circuit analysis involving transistors, op-amps, and MOSFETs. Each question presents a circuit scenario and asks for specific values or conditions, with corresponding answer options. The document also includes hints and solutions for some of the questions, providing insights into the calculations and reasoning behind the answers.

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0% found this document useful (0 votes)
20 views15 pages

Analog Electronics - GATE Full Syllabus Test Paper

The document contains a series of questions and answers related to analog electronics, specifically focusing on circuit analysis involving transistors, op-amps, and MOSFETs. Each question presents a circuit scenario and asks for specific values or conditions, with corresponding answer options. The document also includes hints and solutions for some of the questions, providing insights into the calculations and reasoning behind the answers.

Uploaded by

appalabalaji5
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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GATE

FULL LENGTH TEST


HINGLISH
ANALOG ELECTRONICS

Q1 For the circuit given IS = 3 × 10–17 A and VA = ∞ Q3 A DC-biased transistor circuit is shown below:
and IC = 1 mA. Assume VT = 26 mV.

Then the value of the collector's current IC is


The value of VB is _______mA.
(A) 26 mV (B) 809.6 mV
Q4 An OPAMP circuit is as given below:
(C) 726 mV (D) 0 mV

Q2 The circuit of figure shown below, drives a light


emitting diode D1 that has forward voltage
drop of 2V when current through it is 10 mA. The
BJT Q1 has
β = 50 and VBE = 0.7 V. The value of V1(in volts)
for LED current of 10 mA, is ________. (Rounded
off to two decimal places).

OPAMP is ideal OPAMP. The value of power


delivered by the 5 V DC source will be ____mW.

Q5 For the given circuit VCB = 0.5 V and ꞵ = 100. The


value of IQ (IE)is _______ mA. (Rounded off to
two decimal places).

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GATE

(B) R1 = 2.5 kΩ, R2 = 5 kΩ


(C) R1 = 500 kΩ, R2 = 50 kΩ
(D) R1 = 50 Ω, R2 = 500 Ω

Q8 In the regulator circuit shown below Vz = 12 V, ß =


50, VBE = 0.7 V. The Zener current is _______ mA.
(Rounded off to two decimal places).

Q6 For the transistor shown β = 25. The range of V1


such that 1.0 V ≤ VCE ≤ 4.5 V is

Q9 For the circuit shown below α = 0.992. The value


of voltage VBC is _____ volts. (Rounded off to
two decimal places).

(A) 1.86 V ≤ V1 ≤ 3.96 V


(B) 2.81 V ≤ V1 ≤ 4.46 V
(C) 1.43 V ≤ V1 ≤ 79 V
(D) 2.18 V ≤ V1 ≤ 3.69 V

Q7 The transistor following amplifiers circuits has


parameters ꞵ = 100, rπ = 2.5 kΩ.

Q10 Two perfectly matched silicon transistor are


connected as shown in figure. The value of the
current I is __________ mA. (Rounded off to
three decimal places).

If input impedances of the two circuits are given


as R1 and R2 respectively then
(A) R1 = 2.5 kΩ, R2 = 2.5 kΩ

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GATE

Given gm = 2.68 m℧
The value of the 3dB frequency due to coupling
capacitor CC1 is (Hz). (Rounded off to
three decimal places).
Q11 For the circuit shown below, both transistors are
identical and has following parameters: Q14 An NMOS technology has µnCox = 200
µnCox = 40 mA/V2, VTH =1V, W/L = 3. then the mA/V2 and VTH = 0.5 V. For a transistor with L =
value of current I1 will be________µA. 0.5 mm, the values of W and VGS that results in
gm = 2mA/V at ID = 0.25mA are respectively
(A) W = 20 mm & VGS = 0.75 V
(B) W = 20 mm & VGS = 1.5 V
(C) W = 40 mm & VGS = 0.75 V
(D) W = 80 mm & VGS = 3 V

Q15 For the MOSFET circuit given in the below figure


ID = 0.1 mA & VD = 0.3 V. The MOSFET has Vt = 0.5
V, µnCOX = 400 µA/V2, L = 0.4 µm & W = 5 µm.
Which of the following options is/are correct?

Q12 The extremely high input impedance of a


MOSFET is primarily due to the
(A) Absence of its channel.
(B) Negative gate-source voltage.
(C) Depletion of current carriers.
(D) Extremely small leakage current of its gate
capacitor.

Q13 Consider the circuit shown in figure below. The


(A) The value of RD is 3 kΩ
transistor parameter are:
(B) The value of RS is 7 kΩ
Kp = 2 mA/V2, VTP = –1.5V and λ = 0 .
(C) The value of RD is 7 kΩ
(D) The value of RS is 3 kΩ

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GATE

Q16 The PMOS transistor in the circuit of the given (D) A0 = 11(2 – A) and B0 = –11B
figure below has VT = – 0.5 V, µpCOX = 100
Q18 A Zener diode specified to have VZ = 6.8V at the
µA/V2, L = 0.18 µm and λ = 0. The value
test current IZ = 5 mA, incremental (dynamic)
required for W & R in order to establish a drain
resistance rz = 20 Ω and knee current Izk = 0.2
current of 180 µA & a voltage VD of 1 V are
mA, is connected in the circuit shown below.
respectively
The supply voltage Vs = 10 V.

Let VL = 𝑉𝐿1 for 𝑅𝐿1 = 2 kΩ and VL = 𝑉𝐿2 for RL =


0.5 kΩ. The value of 𝑉𝐿1 − 𝑉𝐿2 (in volts) is _____.
(A) W = 7.2 µm & R = 5.55 kΩ
(upto two decimal places)
(B) W = 15.4 µm & R = 10 kΩ
(C) W = 3.35 µm & R = 12 kΩ Q19 A MOSFET circuit is designed as shown:
(D) W = 8.7 µm & R = 10 kΩ

Q17 The amplifier circuit shown below uses three


op-amps operating in linear region. The input
V1(t) = A + B cos ωt V and V2 = 2V. If the output
V0(t) is expressed as V0(t) = A0 + B0 cos ωt, the
value of A0 and B0 are

Initially capacitor is discharged and circuit


started at t = 0 then the maximum value of
transconductance gm in above circuit will be
_____ (mA/V).

Q20 Consider the circuit shown below, assume that


diodes is on and VI = 20 sin ωt

(A) A­0 = 10(2 – A) and B0 = – 10B


(B) A0 = –11(2 – A) and B0 = 11B
(C) A0 = –10(2 – A) and B0 = 10B

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GATE

The maximum value of output V0 will be


(A) 0 (B) 40
(C) 20 (D) None of these

Q21 Consider a non-inverting Schmitt trigger with


upper and lower threshold values equal to 0.5
and – 0.2. If input is 2 sin ω 0 t then duty cycle
of the output will be _________%

Q22 Consider the op-amp circuit shown below, if the


op-amp is ideal then voltage V0 will be
_________ Volts. (A) 7.07 × 105 rad/sec, 1.25 × 10–4A/V
(B) 5.34 × 105 rad/sec, 4 × 10–4A/V
(C) 10 × 105 rad/sec, 9.5 × 10–4A/V
(D) None of these

Q25 In figure below the NMOS has VTH = 1.0V and


. The current through
W 2
(un Cox ) = 4 mA /V
L

diode (in mA) is _________ (Assume MOSFET in


saturation)

Q23 Consider the circuit shown below,

If value of L = 1 mH, C = 1 nF then which of the


following statements are correct.
(A) Value of Rx for sustained oscillation is 20 kΩ
(B) Value of Rx for sustained oscillation is 15 kΩ
(C) Oscillation frequency = 106Hz
(D) Oscillation frequency = 106 rad/sec

Q24 In the oscillator circuit shown in figure, the


frequency of oscillation and the required value
of gm to maintain oscillations are respectively

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GATE

Answer Key
Q1 (B) Q14 (A)

Q2 4.3~4.5 Q15 (C, D)

Q3 1.6~1.65 Q16 (A)

Q4 26~28 Q17 (D)

Q5 0.9~0.92 Q18 1.7~1.8

Q6 (A) Q19 1~1

Q7 (B) Q20 (A)

Q8 35.8~36.4 Q21 47~48

Q9 4.4~4.55 Q22 24~26

Q10 4.19~4.24 Q23 (B, D)

Q11 230~250 Q24 (A)

Q12 (D) Q25 0.5~0.5

Q13 34~36

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GATE

Hints & Solutions


Q1 Text Solution: ⇒ VBE = VB − VE = 0. 7 V

If ß >> 1 ⇒ VB = VE + 0. 7
V
BE
VCE ⇒ VB = 3. 5 + 07 = 4. 2 V
V
IC = IE = IS ⋅ e T [1 + ]
VA 3
⇒ V1 = I B × 1 × 10 + VB
IE 3
⇒ V1 = × 1 × 10 + VB
β+1
−3 3
10 ×10 ×1 ×10
⇒ V1 = + 4. 2 = 4. 396 = 4
50+1

. 40 V

Q3 Text Solution:

Let’s analyze the circuit:

If VA = ∞
V
BE

⇒ IC ≃ IE = IS ⋅ e V
T

IC
⇒ VBE = VT ln ( )
IS

−3
−3 1×10
⇒ VBE = 26 × 10 ln ( )
−17
3×10

⇒ VBE = 809. 577 mV

= VB (∵ VE = 0 V)

Open circuit test, VB = 6.7 V & VE = 0


Q2 Text Solution:
\ Open circuit (VB – VE) = 6.7 V > VBE [0.7V]
VE = I E R E + 2
\ This BJT is definitely ON and will be either
⇒ I E = 10 mA

−3 in active region or saturation region.


⇒ VE = (10 × 10 × 150) + 2
Let’s assume it to be in active region and
⇒ VE = 1. 5 + 2 = 3. 5 V
moving in B-E loop, we get:
⇒ VE = 3. 5 V
6.7 – 120IB - 0.7 = 0
IB = 0.05 mA
IC = βIB in active region.
\ IC = ∞ & \ VCE = VC – VE = –ve value < 0.2 V
As VCE < 0.2 V, therefore our assumption of
active region is wrong and as BJT is ON
therefore it will be in saturation region with
circuit as:

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GATE

Therefore, the power delivered by the 5 V DC


source is:
P = VI1 = 5 × 5.4= 27 mW.

Q5 Text Solution:
VCB = 0. 5 V

⇒ VC − VB = 0. 5 V

⇒ VC − 0 = 0. 5 V

⇒ VC = 0. 5 V
5−VC 5−0.5
⇒ IC = = = 0. 90 mA
3 3
5 ×10 5 ×10
From C-E loop: β 100
IQ = IE = IC = × 0. 90 = 0
V CC −V C 6.7−0.2 β+1 100+1
IC = = = 1.625 mA
4kΩ 4kΩ
. 909mA ≃ 0. 91 mA
IC = 1.625 mA→Saturation current & IB from B-E
I csat
loop IB = 0.05 mA & as IB > →
β Q6 Text Solution:
\ saturation region
Hence IC = Icsat = 1.625 mA.

Q4 Text Solution:

Let’s draw the circuit and analyze it.

VCE = VC & VBE = VB = 0. 7 V

⇒ apply KCL & ohm 's law at node

VB
V1 −0.7 0.7+5
⇒ = + IB
3 3
15×10 100 ×10
V1 −0.7 −3 IC
⇒ = 0. 057 × 10 +
3
15×10 β

As value of negative terminal V- is fixed at 5 V ⇒ V1 = 0. 7 + 0. 855 +


IC
× 15 × 10
3

25

therefore, no negative feedback is present in ⇒ IC =


5−VCE

the circuit, so OPAMP works in open loop 1×10

⇒ I C = (5 − VCE ) mA
configuration as comparator.
(i) ⇒ I Cmin = (5 − VCEmax ) mA
As V– = 5 V & V+ = 1 V, \ V– > V+ Þ so Vo = – Vsat
⇒ I Cmin = (5 − 4. 5) mA
\ Vo = –Vsat = –10 V
⇒ I Cmin = 0. 5 mA
\ By applying KCL at negative terminal of I Cmin 3
⇒ V1 min = 0. 7 + 0. 855 + × 15 × 10
OPAMP, we get: 25
0.5×10
−3

5−3 5−V o 15
⇒ V1 min = 0. 7 + 0. 855 + × 15
25
I1 = I2 + I0 = + = 0.4 +
5 3 3
3
× 10
= 5.4 mA

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GATE
20−12
⇒ V1 min = 1. 555 + 0. 3 ⇒ V1 min = 1 ⇒ = IB + IZ
220
8
. 86V ⇒ IZ = − IB
(ii)
220
⇒ I Cmax = (5 − VCEmin ) mA −3 −3
⇒ I Z = 36. 36 × 10 − 0. 221 × 10
⇒ I Cmax = (5 − 1) mA
⇒ I Z = 36. 14 mA
⇒ I Cmax = 4 mA

⇒ V1 max = 0. 7 + 0. 855 +
I Cmax
× 15
Q9 Text Solution:
25

3
× 10
−3
4×10
⇒ V1 max = 0. 7 + 0. 855 + × 15
25

3
× 10

⇒ V1 max = 1. 555 + 2. 4 ⇒ V1 max = 3

. 96V

Range will be ⇒ 1. 86V ≤ V1 ≤ 3. 96V

Q7 Text Solution:

VB = 0 V

VE = 0 + 0. 7

VE = 0. 7 V
9−VE
IE =
3
4 ×10
9−0.7
IE =
3
4 ×10

⇒ I E = 2. 075 mA
R 1 = rπ = 2. 5 kΩ
β
⇒ IC = × IE
R 2 = rπ + (β + 1) ⋅ R E = 2. 5 k + (101) β+1
α 0.992
× 25 = 5. 025 kΩ ⇒ β = =
1−α 1−0.992

Q8 Text Solution: ⇒ β = 124


124 −3
⇒ IC = × 2. 075 × 10
125

⇒ I C = 2. 058 mA
VC +9
⇒ IC =
3
2.2 ×10
−3 3
⇒ VC = −9 + 2. 058 × 10 × 2. 2 × 10

⇒ VC = −4. 47 V

⇒ VBC = VB − VC

⇒ VBC = 4. 47 V

Q10 Text Solution:


Apply KCL & Ohm's Law at node (A)
20−12
⇒ = IB + IZ
220

⇒ VE = 12 − 0. 7 = 11. 3 V
VE 11.3
⇒ IE = = = 11. 3 mA
3 3
1×10 1×10
−3
IE 11.3 ×10
⇒ IB = = = 0. 221 mA
β+1 51

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GATE

Q12 Text Solution:


In MOSFET, the gate current is zero due to SiO2
present between gate and channel. So, input
impedance is high due to the small leakage
current of gate capacitor.

Q13 Text Solution:


Small signal equivalent circuit is

I ref
I =
2
1+
β

0−VB
I ref =
3 1 3
(0.5×10 + ×10 )
2 1
fL =
1
2πCeq R eq
VB = −5 + 0. 7 = − 4. 3 V
4.3 3
I ref = = 4. 3 mA Ceq = CC and R eq = (0. 2 × 10 )
1
3
1×10
4.3
I = = 4. 216 mA 3 ∣∣ 1
2
+ (1. 2 × 10 )
1+
100
∣∣ gm

3 3
R eq = (0. 2 × 10 ) + (1. 2 × 10 ∣∣0. 373
Q11 Text Solution: ∣∣

3
× 10 )
3 3
R eq = (0. 2 × 10 ) + 0. 2846 × 10

R eq = 0. 4846 kΩ

Ceq = CC = 9. 4 μF
1

1
fL =
1
2πReq Ceq

1
fL =
1 3 −6
2π×0.4846×10 ×9.4×10

fL = 34. 957 Hz
1

Q14 Text Solution:


1 W 2
ID = ⋅ μn ⋅ Cox ⋅ [VGS − VTH ]
2 L
∂I D W
gm = = μn ⋅ Cox ⋅ [VGS − VTH ]
∂VGS L

M1 and M2 are connected in series gm = μn ⋅ Cox ⋅


L
[VGS − VTH ]
−−−−−−−−−−−−−
...(i)
W
ID = ID gm = √ 2I D ⋅ μn ⋅ Cox ⋅
1 2 L
1 W 2 1 2I D
2
× μn × Cox ×
L
(VGS
1
− VTH ) =
2
× μn
gm =
VGS −VTH
...(ii)
W 2
× Cox ×
L
(VGS
2
− VTH ) Case (i):
2 2 −−−−−−−−−−−−−
W
(6 − V2 − 1) = (V2 − 0 − 1) gm = √ 2I D ⋅ μn ⋅ Cox ⋅
L

5 − V2 = V2 − 1 ⇒ V2 = 3 V 2 W
gm = 2I D ⋅ μn ⋅ Cox ⋅
1 W 2 L
ID = I1 = × μn Cox × (VGS − VTH ) 2
g m ×L
2 2 L 2

2
W =
1 −3 2I D ⋅μn ⋅Cox
I1 = × 0. 04 × 10 × 3 × (3 − 0 − 1)
2 −6 −6
(4×10 )×(0.5 ×10 )

I 1 = 0. 24 mA = 240 μA W = = 20 μm
−3 −3
2×0.25×10 ×0.2×10

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GATE

Case (ii):
2I D
gm =
(VGS −VTH )
2I D
VGS − VTH =
gm

2I D
VGS = VTH +
gm
−3
2×0.25×10
VGS = 0. 5 +
−3
2×10

VGS = 0. 75 V

Q15 Text Solution:

VD −0
ID =
R
VD 1
R = =
ID −6
180×10

R = 5. 55 kΩ
1 W 2
ID = × μ0 ⋅ Cox ⋅ [VSG − VTH ]
2 L
−6 1 −6
180 × 10 = × 100 × 10
2

W 2
× [(1. 8 − 1) − 0. 5]
−6
0.18×10
W 2
180 = 50 × [0. 3]
−6
0.18×10
−6
1−VD 50×0.18×10
ID = W = = 7. 2 μm
RD 50×(0.09)

1−VD 1−0.3
RD =
ID
=
0.1 ×10
−3 Q17 Text Solution:
0.7
RD = = 7 kΩ
−3
0.1 ×10
VS +1
ID =
RS

VS +1
RS =
ID

1 W 2
ID = ⋅ μn ⋅ Cox ⋅ [VGS − VTH ]
2 L
−3 1 −3
0. 1 × 10 = × 0. 4 × 10
2

5 2
× [VGS − 0. 5]
0.4
2 0.1×2×0.4
[VGS − 0. 5] = = 0. 04
0.4×5

VGS − 0. 5 = 0. 2

VGS = 0. 7 V
At Node a
VS = VG − VGS = 0 − 0. 7
5k
Va = (1 + ) ⋅ V1
VS = − 0. 7 V 0.5k

− 0.7+1 Va = 11V1 …(1)


RS = = 3 kΩ
−3 5k
0.1 ×10
Vb = (1 + ) ⋅ V2
0.5k

Q16 Text Solution: Vb = 11V2 …(2)


Vo = Vb – V a …(3)
By equation (1), (2) & (3)
Vo = 11(V2 – V1)

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GATE

Vo = (2 – A – B cos ωt)
= 22 – 11A – 11 B cos ωt
where, given Vo = A0 + B0 cos ωt
A0 = – 11(A – 2)
B0 = – 11B

Q18 Text Solution:

0.5k
VL = Vz = × 10 = 5V < 6. 7V
2 1k

VL − VL = 6. 76 − 5 = 1. 76 V
1 2

Q19 Text Solution:


Lets draw the circuit and analyze it:
Vz = Vz + I z ⋅ rz
0

6. 8V = Vz + 5m × 20
0

Vz = 6. 7 V
0

• VG = 3V, VS = 0 V, VD = V­C
VDS = VC, VGS = 3V
∵ VGS > Vth → ON
Initially at t = 0, VDS = VC = 0 and no current
10−VL
1
VL −6.7
1
VL −0
1 flows through MOSFET and all the current from 5
= +
500 20 2000
V source will flow from capacitor and capacitor
⇒ 40 − 4VL = 100VL − 670 + VL
starts charging and thus Vc↑ & VDS↑.
1 1 1

⇒ 710 = 105VL
• As soon as VDS increases from a value,
1

710
VL = V
MOSFET current IDS start flowing and capacitor
1 105

VL = 6. 76 V
1
will charge through a lower current.
• Till capacitor voltage reaches to VGS – Vth = 2
V, VDS will be less then
(VGS – Vth) and MOSFET will be in triode region
and gm = 2KnVDS = 2 KnVc.
• As soon as Vc = (VGS – Vth) MOSFET enters into
saturation and further increase in Vc [VDS]

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GATE

above (VGS – Vth), MOSFET will remain in


saturation region and thus for
Vc ≥ (VGS – Vth) → gm = 2Kn[VGS – Vth] →
maximum value of transconductance.
(gm)max = 2Kn [3 – 1] = 4Kn = 1 mA/V

Q20 Text Solution:


When the input is positive then both diode D1
and D2 are ON thus the circuit will become as
shown in figure (a) thus C1 and C2 will charge
with 20 V as VS has maximum value equal to 20.
thus when Vi = 2 sin ωt output will be

We can see that here V0 = 0


Now when capacitor are charged with 20V and
input goes below 20V then diode D1 and D2 will
turn OFF and circuit-will become as shown in
figure (b)

The V0 = high when θ1 < θ < θ2

−1 0.5 −1 −0.2
⇒ sin ( ) < θ < sin ( )
2 2

0.252 rad < θ < 3.241 rad


So out of cycle of 2π output is high for 2.989 rad
Here also we can see that V0 = 0V thus we can Duty Cycle=
2.989
× 100 = 47. 57%

see that V0 is always zero.
Q22 Text Solution:
Q21 Text Solution: The op-amp is in negative feedback and
The V0 V/s Vi characteristic of non Inverting V0
VA =
2
by (voltage division rule)
Schmitt trigger is
VA = VB by virtual short concept.

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GATE

Now KCL at B and for oscillation we need


5−VB VB V B −V 0 C2
= + gm R D = = 0. 5
20k 50k 20k C1

Multiply above equation by 100 k we get gm =


0.5
=
0.5
= 1. 25 × 10
−4
A/
V
RD 4000

25 – 5VB = 2VB + 5VB – 5V0


V0
⇒ 25 = 12VB − 5V0 = 12 × − 5V 0
2

= V0

⇒ V0 = 25V

Q23 Text Solution:


The parallel LC circuit will oscillate at
1 1
ω0 = =
√LC √10−3 ×10−9

6
ω 0 = 10 rad / sec

at resonant condition parallel LC network is Q25 Text Solution:


open circuited and circuit can be redrawn as We can see that
shown, loop gain is I D = 2mA =
1
μn Cox
ω
(VGS + Vth )
2

2 L
4 2
⇒ 2 = (VGS − Vth )
2

⇒ (VGS − Vth ) = 1

VGS = 2V

2
Vf = V0 ×
2+R x

and V0
15
= Vf (1 + )
2
17
V0 = Vf ( )
2

For sustained oscillations we need |AB| = 1


17 2
× = 1
2 2+R x We can see that
R x + 2 = 17 3V0
VG = thus
5
R x = 15 kΩ 3V0
VGS = − V0 = 2
5

Q24 Text Solution: ⇒ V0 = −5V.

We can see that the circuit is Colpitts oscillator Let current in diode is i, since op-amp is ideal so
with ω 0 =
1
current in 10kΩ will also be i,
√LC eq

Ceq =
C1 C2
= 2 nF
Since VA = 0 (Virtual ground) so
C1 +C2 V A −V 0
1 = i
ω0 = 10k
√1×10−3 ×2×10−9 0−(−5)
6 = i
10 5 10k
= rad /sec = 7. 07 × 10 rad / sec
√2

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GATE

i = 0.5 mA.

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