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Assignment_2_CMOS_ASIC

The document provides an overview of standard cell libraries, specifically focusing on Liberty and LEF files that contain essential information about cell timing, power, electrical characteristics, and physical dimensions. It outlines the types of data to be extracted using Unix commands, including cell counts, drive strengths, pin capacitances, operating conditions, and physical design parameters. The document emphasizes the need for pipelined grep commands to gather and tabulate this data effectively.

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sureshkini0913
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3 views

Assignment_2_CMOS_ASIC

The document provides an overview of standard cell libraries, specifically focusing on Liberty and LEF files that contain essential information about cell timing, power, electrical characteristics, and physical dimensions. It outlines the types of data to be extracted using Unix commands, including cell counts, drive strengths, pin capacitances, operating conditions, and physical design parameters. The document emphasizes the need for pipelined grep commands to gather and tabulate this data effectively.

Uploaded by

sureshkini0913
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Standard Cell Libraries

For the exercises below, you will use Liberty (‘dotlib”) and LEF files for standard cell libraries.

Liberty files contain timing, power and electrical information for each cell. Timing information includes
things like:
1. input to output delay for combinational cells
2. setup & hold time for sequential cells

Power information includes things like leakage power when the cell is not switching, and internal power
when the cell is switching.

Electrical information includes things like pin capacitances.

Liberty files also contain Boolean expressions for the functionality of each cell. There can be other
information in the Liberty file as well, such as cell area. T

The section in the dotlib file pertaining to a particular cell starts with the line “cell (<cell_name>)”

LEF files contain physical information such as:


1. cell dimensions (width and height)
2. physical locations, metal layers and shapes of pins
3. shapes and layers of power and ground rails

The section in the LEF file pertaining to a particular cell starts with the line “MACRO (<cell_name>)”.

The LEF format also supports the recording of information on the metal layers used for routing. This
information may be part of the same file that contains information on the cells, but is sometimes put in
a separate file. If there is a separate file, it is called the “technology LEF” or “techlef” file for short.

Using pipelined unix commands like grep, determine and tabulate the data requested below. When
using grep, you will likely need to use the -A and -B options to get the lines you need.

(A) Cell counts and types


RAK Nangate_OCL Nangate_15nm Skywater HS
Total No. of Cells
Flip-flops (DFFs)
Total no. of DFFs
No. of DFFs with reset
No. of DFFs with set
No. of negative edge-
triggered DFFs
NAND gates
Count of 2-input NAND gates
Count of 3-input NAND gates
Count of 4-input NAND gates
Muxes
Count of 2-input muxes*
Count of 3-input muxes*
Count of 4-input muxes*
*
Note: when we say a “2-input” mux, we mean it has two “data inputs”. The “select input” is not
counted.

(B) Cell Drive Strengths


RAK Nangate_OCL Nangate_15nm Skywater HS
Inverter
Total count
Max drive strength
Min drive strength
Buffer
Total count
Max drive strength
Min drive strength
NAND2
Total count
Max drive strength
Min drive strength
DFFs
Total count
Max drive strength
Min drive strength
(C) Cell pin capacitances and areas in the Skywater HS Library
For each function in the first column, list all the cells (different drive strengths) and their area and input
pin capacitances in the table below. Insert rows as necessary. For any gate with more than one input,
the input pin capacitance will be different for different inputs. For the “Input Pin Cap” column, select any
one input, but be consistent and use the same input for each cell.

Function Cell Name Cell Area Input Pin Cap


Inverter

Buffer

NAND2

(D) Operating Conditions (P-V-T)


In the skywater HS and MS libraries, for what P-V-T conditions are dotlibs available? Report this in the
following table, adding rows as required:
dotlib file name P V (volts) T (oC)

You will likely need to use a series of pipelined grep commands with and without the “-v” option.

(E) Physical Design


Extract data from the LEF files, including techlef, to fill out the following table:

RAK NangateOpenCellLibrary Nangate_15nm


Cell height
No. of metal layers
Routing pitch
Cell height in routing
tracks

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