EE3404 (MP&MC)

[Regulation-2021]

Microprocessor & Microcontroller

(Second Year, 4th Semester EEE)

Unit 3
Interfacing Basics and ICs
MP&MC/EE3404 Lecture Notes
by
Dr.I.William Christopher
Professor/EEE Dept./LICET

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 Course Objectives
▪ To study the addressing modes & instruction set of 8085
& 8051

▪ To develop skills in simple program writing in assembly

languages

▪ To introduce commonly used peripheral/interfacing ICs.

▪ To study and understand typical applications of micro-

processors.

▪ To study and understand the typical applications of

micro-controllers
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 Course Outcomes
Upon successful completion of the course, the students should have
the:
C01 Ability to write assembly language program for microprocessor
and microcontroller
C02 Ability to design and implement interfacing of peripheral with
microprocessor and microcontroller
C03 Ability to analyze, comprehend, design and simulate
microprocessor based systems used for control and monitoring.
C04 Ability to analyze, comprehend, design and simulate
microcontroller based systems used for control and monitoring.
C05 Ability to understand and appreciate advanced architecture
evolving microprocessor field

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 Units of Microprocessor & Microcontroller
The Course deals with the following Units:
Unit –I : Introduction to 8085 Architecture

Unit –II : 8085 Instruction Set and Programming

Unit –III : Interfacing Basics and ICs

Unit –IV : Introduction to 8051 Microcontroller

Unit –V : Introduction to RISC Based Architecture

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 Text and Reference Books
Textbooks:
1) Ramesh S. Gaonkar, ‘Microprocessor Architecture Programming and
Application’, Pen ram International (P)ltd., Mumbai, 6th Education, 2013.
2) Muhammad Ali Mazidi & Janice Gilli Mazidi, ‘The 8051 Micro Controller
and Embedded Systems’, Pearson Education, Second Edition 2011.
3) Muhammad Ali Mazidi & Janice Gilli Mazidi, ‘The PIC Micro Controller
and Embedded Systems’, 2010
Reference Books:
1) Douglas V. Hall, “Micro-processors & Interfacing”, Tata McGraw Hill 3rd
Edition, 2017.
2) Krishna Kant, “Micro-processors & Micro-controllers”, Prentice Hall of
India, 2007.
3) Mike Predko, “8051 Micro-controllers”, McGraw Hill, 2009
4) Kenneth Ayala, ‘The 8051 Microcontroller’, Thomson, 3rd Edition 2004.
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 Unit-I: Introduction to 8085 Architecture

Topics to be discussed:
▪ Functional Block Diagram

▪ Memory Interfacing

▪ I/O Ports and Data Transfer Concepts

▪ Timing Diagram

▪ Interrupt Structure

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 Unit-II: 8085 Instruction Set and Programming
Topics to be discussed:
▪ Instruction Format and Addressing Modes
▪ Assembly Language Format
▪ Data Transfer, Data Manipulation &
Control Instructions
▪ Programming:
✓Loop structure with Counting & Indexing
✓Look up table
✓Subroutine instructions
✓Stack
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 Unit-III: Interfacing Basics and ICs
Topics to be discussed:
▪ Study of Architecture and programming of ICs:
✓ 8255 – PPI (Programmable Peripheral Interface)
✓ 8259 – PIC (Programmable Interrupt Controller)
✓ 8251 – USART (Universal Synchronous and
Asynchronous Receiver Transmitter)
✓ 8279 – Programmable Keyboard/Display
Interface
✓ 8254/53 – (Programmable Interval Timer/Counter)
▪ Interfacing with 8085
✓A/D and D/A converter interfacing
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 Unit-IV: Introduction to 8051 Microcontroller
Topics to be discussed:
▪ Functional Block Diagram
▪ Instruction Format And Addressing Modes
▪ Interrupt Structure
▪ Timer
▪ I/O Ports
▪ Serial Communication
▪ Simple Programming
▪ Keyboard And Display Interface
▪ Temperature Control System
▪ Stepper Motor Control
▪ Usage of IDE for Assembly Language Programming
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 Unit-V: Introduction to RISC Based Architecture
Topics to be discussed:
▪ PIC16 /18 Architecture
▪ Memory Organization
▪ Addressing Modes
▪ Instruction Set
▪ Programming Techniques
▪ Timers
▪ I/O Ports
▪ Interrupt Programming
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 8255A PPI (Programmable Peripheral Interface)

• It is a Programmable, Parallel I/O Device

• It can be programmed to transfer data under various
conditions from simple I/O to interrupt I/O.
• It is a 40 pin IC.
• It has 24 I/O pins that can be grouped into
- Two 8-bit parallel ports A & B
- Two 4-bit ports C i.e Cupper & Clower
• Functions of these ports are defined by writing a control
word in the control register.

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 Functions of 8255 PPI
All the functions of the 8255A, classified according
to two modes.
1. BSR Mode (Bit Set/Reset mode)
- Used to set or reset the bits in ports C.

2. I/O Mode
- Mode 0 – Simple I/O Ports
- Mode 1 – Handshake I/O port
- Mode 2 - Bi-directional I/O port

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 Ports Of 8255A PPI

Port A

Port Cupper
8255A PPI
Port Clower

Port B

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 Pin Configuration of 8255 PPI

37-40 PA7 – PA0

D7 – D 0 27 - 34
1-4
RD 5
WR 36 10-13 PC7 – PC4
CS 6 8255 PPI
14-17 PC3 – PC0
A1 8
A0 9
RESET 35 PB7 – PB0
18 - 25
+5V 26
7
GND

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 Pin Configuration of 8255 PPI

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Functional
Block
Diagram of
8255 PPI

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 8255A Chip Select Logic & I/O Port Addresses

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 8255 I/O Ports & their Modes

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 MODE O – Simple I/O Port:

• Ports A & B are used as two simple 8-bit I/O ports

and port C as two 4-bit ports.
• Each port can be programmed to function as simply
an input port or an output port.
• Outputs are latched.
• Inputs are not latched.
• Ports do not have handshake or interrupt capability.
• Used to interface DIP switches, Hexa-Keypad, LEDs
and 7-Segment LEDs to the processor.

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 MODE 1– Hand Shake I/O Port:
• Ports A & B are used as two simple 8-bit I/O ports.
• Port C pins are used for Handshake signals.
• Handshake signals are exchanged between the
processor and peripherals prior to data transfer .
• Interrupt logic is supported.
• Input & Outputs are latched.
• Handshake signals:
• Signals are exchanged between I/O device and
port or port and processor for checking or
informing various condition of the device.
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 MODE 1 Control Signals

• Input Control Signals

• Output Control Signals

- STB (Strobe Input)

- OBF (Output Buffer Full)
- IBF (Input Buffer Full)
- ACK (Acknowledge)
- INTR (Interrupt Request)
- INTR (Interrupt Request)
- INTE (Interrupt Enable)
- INTE (Interrupt Enable)

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 8255A Control Word Format in the I/O Mode

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 8255A Control Word Format in the I/O Mode

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 8255A Control Word Format in the BSR Mode

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 8255A Control Word Format in the BSR Mode

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 8255A Control Word Format in the BSR Mode

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 8255A Mode-1 : Input Configuration

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 8255A Mode-1 : Input Configuration
Flow Charts

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 8255A Mode-1 : Output Configuration

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Interfacing the 8255A Mode-1(Strobed Input/Output)

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 8255A Mode-2: Bidirectional Input/Output

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 8255A PPI: Interfacing Example-01
Interfacing a Keyboard and 7-segment LED
Problem Statement

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 8255A PPI: Interfacing Example-01
Interfacing a Keyboard and 7-segment LED

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 8255A PPI: Interfacing
Example-01
Interfacing a Keyboard and
7-segment LED
Flowchart Key Check Subroutine

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 8255A PPI: Interfacing Example-02
Bidirectional Communication b/w two Computers
Problem Statement

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 8255A PPI: Interfacing Example-02
Bidirectional Communication b/w two Computers
Interfacing Diagram

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 8255A PPI: Interfacing
Example-02
Bidirectional Communication
b/w two Computers
Flowchart of Master Program

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 8255A PPI: Interfacing
Example-02
Bidirectional Communication
b/w two Computers
Flowchart of Slave Program

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 8251A – USART
Universal Synchronous Asynchronous
Receiver Transmitter
Features of 8251:
• A programmable chip designed for synchronous/ asynchronous
serial data communication.
• It is a programmable serial I/O chip.
• It is an enhanced version of 8251.
• It is packaged in a 28-pin DIP IC.
• It includes 5 sections:
✓ Read /write control logic
✓ Transmitter section
✓ Receiver section
✓ Data bus Buffer
✓ Modem control.
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 Pin out of 8251A

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 Functional Block diagram of 8251A

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 8251A- Expanded Block Diagram
Control Logic and Registers

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 8251A- Expanded Block Diagram
Transmitter and Receiver Sections

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 8251A- Mode Word Format

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 8251A- Command Word Format

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 8251A- Status Word Format

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 8251A- Points to be remember

Summary of control signals for the 8251A:

CS C/D RD WR Function
0 1 1 0 MP writes inst. in the control register (* MP –Microprocessor)
0 1 0 1 MP reads status from the status register
0 0 1 0 MP output’s data to the data buffer
0 0 0 1 MP accepts data from the data buffer
1 X X X USART is not selected

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 8251A- Points to be remember
Transmitter Section:
▪ This section accepts parallel data on the TxD-line from the MP and
converts them into serial data.
▪ It has 2 registers:
1) Buffer register – to hold 8-bits
2) Outputregister – to convert 8-bits into a stream of serial bits.
Receiver Section:
▪ This section accepts serial data on the RxD-line from a peripheral
and converts them into parallel data.
▪ It has 2 registers:
1) Input register
2) Input buffer register
Modem Control:
▪ It allows to interface a MODEM to 8251 USART
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 8259A – PIC (Programmable Interrupt Controller)
Features of 8259:
• It is a 28pin IC packaged in DIP.
• It is designed to work with Intel microprocessors 8085,8086
& 8088.
• It can manage 8 interrupts according to the instruction
written into its control registers.
• The interrupt vector addresses are programmable.
• The priorities of interrupts are programmable.
– The different operating modes which decide the priorities
are
1) Automatic Rotation mode
2) Specific Rotation mode
3) Fully Nested mode
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 8259A – PIC (Programmable Interrupt Controller)
Features of 8259:
• The interrupts can be masked or unmasked individually.
• It can be expanded to 64 priority levels by cascading
additional 8259As.
• It can read the status of Pending Interrupts, In-Service
Interrupts, and masked interrupts.
• It can set up to accept either the level-triggered or edge-
triggered interrupt request.

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 Pinout and Pin descriptions of 8259A

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 Functional Block diagram of 8259A
• 8259 includes the following blocks
✓Control logic
✓Read/write logic
✓Data bus buffer
✓In-Service Register (ISR)
✓Interrupt –Request Register (IRR)
✓Interrupt Mask Register (IMR)
✓Priority Resolver (PR)
✓Cascade buffer/ comparator
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 Functional Block diagram of 8259A

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 Functional Block diagram of 8259A
▪ Interrupt Request Register (IRR)
✓It has 8-input lines(IR0-IR7) for interrupts.
✓when these lines go high, the requests are stored in the
register.
▪ In Service Register (ISR) stores all the levels that are
currently being serviced.
▪ Interrupt Mask Register (IMR) stores the masking bits of
the interrupt lines to be masked.
▪ Priority Resolver (PR) examines these registers and
determines whether INT should be sent to the
Microprocessor.
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 8259A- Points to be remembered
▪ Cascade buffer/comparator is used to expand the
number of interrupt levels by cascading two or more
8259As.
▪ 8259A programmed by using two control words called
1) ICW (Initialization Command Word)
2) OCW (Operational Command Word)
▪ After the completion of the interrupt service, an End-Of-
Interrupt (EOI) command is issued.

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 8259A- Interrupt Priority Modes
Fully Nested Mode

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 8259A- Interrupt Priority Modes
Automatic Rotation Mode

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 8259A- Interrupt Priority Modes
Specific Rotation Mode

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 8259A- Interrupt Priority Modes
End of Interrupt (EoI)

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 8259A- Additional Features

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 Initialization Command Words for 8259A
ICW1

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 Initialization Command Words for 8259A
CALL Address Intervals

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 Schematic of an Interrupt System
Using 8259A

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 8259A- Example for Instructions

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 8259A- Example for Instructions

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 8259A- Example for Instructions

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 References
• Ramesh.S.Gaonkar, “Microprocessor Architecture, Programming and its
Applications with the 8085” Penream Int.Pub (India).Fourth edition.

• Mohammed Rafiquzzaman, “Microprocessors – Theory and Applications

: Intel and Motorola “, Prentice Hall International, 1999.

• Charles M.Gilmore , “ Microprocessors : Principles and Applications”

Tata McGraw- Hill Edition,Third Reprint 2000.

• A.Nagoor Kani, “Microprocessor(8085) and its Applications”, RBA

Publications, Fourth Reprint 2006.

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