RAJ KUMAR GOEL INSTITUTE OF

TECHNOLOGY , Ghaziabad
Computer Organization And Architecture
BCS-302

Unit: II

COA

Dr. Vinish Kumar

B Tech :3th Sem Professor
CSE(AI&ML)
Vinish Kumar COA Unit Number:1 1
 Course Outcomes
Course outcome: After completion of this course students will be able
to:

Study of the basic structure and operation of a

CO 1 K1, K2
digital computer system.
Analysis of the design of arithmetic & logic unit
CO 2 and understanding of the fixed point and floating- K2, K4
point arithmetic operations.
Implementation of control unit techniques and the
CO 3 K3
concept of Pipelining
Understanding the hierarchical memory system,
CO 4 K2
cache memories and virtual memory
Understanding the different ways of
CO 5 communicating with I/O devices and standard I/O K2, K4
interfaces
 CO 2

Analysis of the design of arithmetic & logic

unit and understanding of the fixed point and
floating-point arithmetic operations
 Combinational and Sequential Circuits
Combinational circuits are defined as the time independent circuits which do not
depends upon previous inputs to generate any output are termed as combinational
circuits.

Sequential circuits are those which are dependent on clock cycles and depends
on present as well as past inputs to generate any output.
 Adder
Adder :- A combinational circuit that performs the addition of bits is called an
Adder. Each computer has an adder located in its CPU(ALU) that is responsible
for the process of addition ,calculation of memory address and many other work.
There are two types of Adder..
Half Adder
Full Adder
Half Adder:-A combinational circuit that performs the addition of two bits is
called a Half Adder. It receives two inputs and produces two outputs Sum and
Carry. The block diagram for a half adder is as follows.
Adder
 Adder
Full Adder:- A combinational circuit that performs the addition of three bits is
called a Full Adder. It receives three inputs and produces two outputs Sum and
Carry. The Block diagram for the Full Adder is shown below.
Adder
 Adder
Full Adder Using 2 half Adder
 Adder
Disadvantage of Full Adder:

In parallel adders, carry output of each full adder is given as a carry input to the next
higher-order state. Hence, these adders it is not possible to produce carry and sum outputs
of any state unless a carry input is available for that state.

So, for computation to occur, the circuit has to wait until the carry bit propagated to all
states. This induces carry propagation delay in the circuit.

Consider the 4-bit ripple carry adder circuit above. Here the sum S3 can be produced as soon as
the inputs A3 and B3 are given. But carry C3 cannot be computed until the carry bit C2 is
applied whereas C2 depends on C1. Therefore to produce final steady-state results, carry must
propagate through all the states. This increases the carry propagation delay of the circuit.

The propagation delay of the adder is calculated as “the propagation delay of each gate times
the number of stages in the circuit”. For the computation of a large number of bits, more
stages have to be added, which makes the delay much worse. Hence, to solve this situation,
Carry Look-ahead Adder was introduced.
 Carry Look-ahead Adder
Carry Look-ahead Adder :- is the faster adder circuit. It reduces the propagation delay,
which occurs during addition, by using more complex hardware circuitry. It is designed by
transforming the ripple-carry Adder circuit such that the carry logic of the adder is changed
into two-level logic. (Predict the Carry)
 Carry Look-ahead Adder

Carry Generate Gi =1. It depends on Ai and Bi inputs. Gi is 1 when both Ai and Bi are
1. Hence, Gi is calculated as Gi = Ai. Bi.
Carry propagated Pi is associated with the propagation of carry from Ci to Ci+1. It is
calculated as Pi = Ai Bi
Using the Gi and Pi terms the Sum Si and Carry Ci+1 are given as below –
Si = Pi Gi.
Ci+1 = Ci.Pi +Gi.
Therefore, the carry bits C1, C2, C3, and C4 can be calculated as
 C1 = C0.P0+G0.
 C2 = C1.P1+G1 = ( C0.P0+G0).P1+G1.
 C3 = C2.P2+G2 = (C1.P1+G1).P2+G2.
 C4 = C3.P3+G3 = C0.P0.P1.P2.P3 + P3.P2.P1.G0 + P3.P2.G1 + G2.P3 + G3.
Carry Look-ahead Adder

C1 = C0P0 + G0

C2 = C0P0P1 + G0P1 + G1
Carry Look-ahead Adder

 C2 = C1.P1+G1 = ( C0.P0+G0).P1+G1.
 C3 = C2.P2+G2 = (C1.P1+G1).P2+G2.
 C4 = C3.P3+G3 = C0.P0.P1.P2.P3 +
P3.P2.P1.G0 + P3.P2.G1 + G2.P3 +
G3
Carry Look-ahead Adder

 C1 = C0P0 + G0
 C2 = C1.P1+G1 = ( C0.P0+G0).P1+G1.
 C3 = C2.P2+G2 = (C1.P1+G1).P2+G2.
 C4 = C3.P3+G3 = C0.P0.P1.P2.P3 +
P3.P2.P1.G0 + P3.P2.G1 + G2.P3 +
G3
Carry Look-ahead Adder
 Carry Look-ahead Adder

Advantages and Disadvantages of Carry Look-Ahead Adder :

Advantages –

•The propagation delay is reduced.

•It provides the fastest addition logic.

Disadvantages –
•The Carry Look-ahead adder circuit gets complicated as the
number of variables increase.
•The circuit is costlier as it involves more number of hardware.

https://www.youtube.com/watch?v=6Z1WikEWxH0
 MULTIPLICATION OF TWO NUMBERS
Multiplication of two fixed point binary number in signed magnitude representation is
done with process of successive shift and add operation.

In the multiplication process we are considering successive bits of the multiplier, least
significant bit first.
If the multiplier bit is 1, the multiplicand is copied down else 0’s are copied down.
The numbers copied down in successive lines are shifted one position to the left from
the previous number.
Finally numbers are added and their sum form the product.
The sign of the product is determined from the sign of the multiplicand and multiplier.
If they are alike, sign of the product is positive else negative.
 MULTIPLICATION OF TWO NUMBERS
Hardware Implementation for Multiplying Binary Numbers

1.Initially multiplicand is stored in B register and multiplier is stored in Q register.

2.Sign of registers B (Bs) and Q (Qs) are compared using XOR functionality (i.e., if both the
signs are alike, output of XOR operation is 0 unless 1) and output stored in As (sign of A
register).Note: Initially 0 is assigned to register A and E flip flop. Sequence counter is
initialized with value n, n is the number of bits in the Multiplier.
3. Now least significant bit of multiplier is checked. If it is 1 add the content of register A with
Multiplicand (register B) and result is assigned in A register with carry bit in flip flop E.
Content of E A Q is shifted to right by one position, i.e., content of E is shifted to most
significant bit (MSB) of A and least significant bit of A is shifted to most significant bit of Q.
4. If Qn = 0, only shift right operation on content of E A Q is performed in a similar fashion.
5. Content of Sequence counter is decremented by 1.
6. Check the content of Sequence counter (SC), if it is 0, end the process and the final product
is present in register A and Q, else repeat the process.
MULTIPLICATION OF TWO NUMBERS
Flowchart for Multiplying Binary Numbers
 MULTIPLICATION OF TWO NUMBERS
Multiplicand = 10111
Multiplier = 10011
2’s Compliment Representation
 MULTIPLICATION OF TWO NUMBERS
Booth algorithm gives a procedure for multiplying binary integers in signed
2’s complement representation in efficient way, i.e., less number of
additions/subtractions required.

Hardware Implementation

https://www.youtube.com/watch?v=meSn0UXmgac
MULTIPLICATION OF TWO NUMBERS
BOOTH.S MULTIPLICATION ALGORITHM
MULTIPLICATION OF TWO NUMBERS
MULTIPLICATION OF TWO NUMBERS
MULTIPLICATION OF TWO NUMBERS
MULTIPLICATION OF TWO NUMBERS
MULTIPLICATION OF TWO NUMBERS
MULTIPLICATION OF TWO NUMBERS
MULTIPLICATION OF TWO NUMBERS
MULTIPLICATION OF TWO NUMBERS
MULTIPLICATION OF TWO NUMBERS
 Array Multiplier
• The multiplication of two binary numbers can be done with one micro
operation by means of a combinational circuit (called Array Multiplier) that
forms the product bits all at once.
• This is a fast way of multiplying two numbers since all it takes is the time for
the signals to propagate through the gates that form the multiplication array.
• However, an array multiplier requires a large number of gates, and for this
reason it was not economic.
• For Multiplier j bits
Multiplicand k bits
j x k AND gates are required
(j - 1) k-bit adders to produce a product of j + k bits.
Array Multiplier
Multiplier j bits
Multiplicand k bits
j x k AND gates
(j - 1) k-bit adders to
produce a product of
j + k bits.
j=2,k=2
AND Gates 2*2=4
1,2 bit adders
2+2 =4 bit product
Array Multiplier
Multiplier j bits
Multiplicand k bits
j x k AND gates
(j - 1) k-bit adders to
produce a product of
j + k bits.
j=3,k=4
AND Gates 3*4=12
2,4bit adders
3+4=7bit product
Array Multiplier
Multiplier j bits
Multiplicand k bits
j x k AND gates
(j - 1) k-bit adders to
produce a product of
j + k bits.
j=3,k=4
AND Gates 3*4=12
2,4bit adders
3+4=7bit product
 Division Algorithm
The Division of two fixed-point binary numbers in the signed-magnitude
representation is done by the cycle of successive compare, shift, and subtract
operations.
Division Algorithm
Division Algorithm
Division Algorithm
Division Algorithm

Final Remainder: 00110

Final Quotient: 11010
 Floating Point Arithmetic operation
A floating point number in computer registers consists of two parts a
Mantissa m and Exponent e. The two parts represent a number obtained from
multiplying m times a radix r raised to the value of e
mxre
For example a decimal number 537.25 is represented in a register with m=53725 and
e=3 and radix(r ) =10

.53735 x 10 3

Consider the addition of two real decimal numbers as fixed point numbers:
1234.00
+ 56.78
1290.78
Now if we try to add the same numbers written in floating point notation, we see that
simply adding the mantissas will not make sense unless the exponents are equal:
0.1234 * 104
+ 0.5678 * 102
 Floating Point Arithmetic operation
Thus, the following steps must be carried out before adding / subtracting
two floating point numbers:
1. Make the exponents of the two numbers equal by making the smaller
exponent equal to the larger and dividing the mantissa of the smaller
number by the same factor by which its exponent was increased, in order to
preserve the actual value of the number.
2. Add / subtract the mantissas.
3. If necessary, re-normalize the result (this is called post-normalization).

We apply those steps to the example above:

1. 0.1234 * 104
+ 0.5678 * 102 = + 0.005678 * 104
2. 0.1234 * 104
+ 0.005678 * 104
0.129078 * 104
3. The result is already normalized.
Floating Point Arithmetic operation
 Floating Point Arithmetic operation
Addition and Subtraction : Algorithm for Addition and Subtraction of two
numbers is divided into 4 parts:-
1. Check for Zeros
2. Align the mantissa
3. Add or Subtract the mantissas
4. Normalize the result
 Floating Point Arithmetic operation
Multiplication : Multiplication of two numbers is divided into 4 parts:-
1. Check for Zeros
2. Add the exponents
3. Multiply the mantissas
4. Normalize the product
 Floating Point Arithmetic operation
Division : Division of two numbers is divided into 5 parts:-
1. Check for Zeros
2. Initialize registers and evaluate the sign
3. Align the dividend
4. Subtract the exponents
5. Divide the mantissas
 Arithmetic operation
The arithmetic microoperations can be implemented in one composite arithmetic circuit.
The basic component of an arithmetic circuit is the parallel adder. By controlling the
data inputs to the adder, it is possible to obtain different types of arithmetic operations.
The output of the binary adder is calculated from the following arithmetic sum:
D =A+ Y + C
Arithmetic operation
 Arithmetic operation
Logic microoperations specify binary operations for strings of bits stored in registers. These
operations consider each bit of the register separately and treat them as binary variables.
 Arithmetic operation
Applications of Logic microoperations: - They very useful for manipulating individual
bits or a portion of a word stored in a register. They can be used to change bit values, delete
a group of bits, or insert new bit values into a register. The following examples show how
the bits of one register (designated by A) are manipulated by logic microoperations as a
function of the bits of another register (designated by B). In a typical application, register A
is a processor register and the bits of register B constitute a logic operand extracted from
memory and placed in register B
selective-set
1010 A before
1100 B (logic operand)
1110 A after
the exclusive-OR microoperation can be used to selectively complement bits of a register.
selective-clear
1010 A before
1100 B (logic operand)
0010 A after
The corresponding logic microoperation is A + A /\ B
 Arithmetic operation
Mask operation
1010 A before
1100 B (logic operand)
1000 A after masking
The mask operation is an AND microoperation
Insert operation
0110 1010 A before
0000 1111 B (mask)
0000 1010 A after masking
and then insert the new value:
0000 1010 A before
1001 0000 B (insert)
1001 1010 A after insertion
The mask operation is an AND microoperation and the insert operation is an OR microoperation
 Arithmetic operation
Shift microoperations :- are used for serial transfer of data. They are also used in
conjunction with arithmetic, logic, and other data-processing operations. The
contents of a register can be shifted to the left or the right.
 Arithmetic operation
Arithmetic Logic Shift Unit:- Instead of having individual registers performing
the microoperations directly, computer systems employ a number of storage
registers connected to a common operational unit called an arithmetic logic unit,
perform a microoperation, the contents of specified registers are placed in the
inputs of the common AW. The AW performs an operation and the result of the
operation is then transferred to a destination register. The AW is a combinational
source registers circuit so that the entire register transfer operation from the
performed through the ALU and into the destination register can be performed
during one clock pulse period. The shift microoperations are often overall in a
separate unit, but sometimes the shift unit is made part of the ALU.
Arithmetic operation
Arithmetic operation
IEEE Standard for Floating Point Numbers
IEEE Standard for Floating Point Numbers
IEEE Standard for Floating Point Numbers
IEEE Standard for Floating Point Numbers
IEEE Standard for Floating Point Numbers