Computer Organization And Architecture

Unit 2
Arithmetic And Logic Unit

Arithmetic And Logic Unit :- "ALU" stands for Arithmetic Logic Unit, a
fundamental component of a computer's central processing unit (CPU). It performs
arithmetic and logical operations, which are the basic building blocks of all
computations a computer carries out.

Key Functions of an ALU:

1. Arithmetic Operations: Addition, subtraction, multiplication, division.
2. Logical Operations: Comparisons (greater than, less than, equal to), AND, OR,
NOT, XOR.
3. Bitwise Operations: Operations on binary numbers, such as shifting bits left
or right.

How it Works:
 Inputs: The ALU receives input data in the form of binary numbers, along with
control signals that specify which operation to perform.
 Operations: Using logic gates and circuitry, the ALU processes the inputs
based on the control signals.
 Output: The result of the operation is sent to other components of the CPU or
stored in memory.

Importance of the ALU:

The ALU is critical to a computer's ability to execute instructions, making it the "brain"
of computation within the CPU. Whether it's simple calculations in a calculator app or
complex tasks like processing graphics, the ALU is at work behind the scenes.
Adders : - Adders are digital circuits designed to perform the addition of binary
numbers. They are fundamental components in various digital systems, including
arithmetic logic units (ALUs), processors, and calculators.

Half Adder :- A Half Adder is a combinational logic circuit that performs the
addition of two single-bit binary numbers, producing two outputs: Sum and Carry.

Key Features:
 Inputs: Two binary digits, typically labeled as A and B.
 Outputs:
1. Sum: The result of A+B without carry-over.
2. Carry: The carry-out bit, generated when A and B are both 1.

Logic Functions:
 Sum: Sum=A⊕B (XOR gate)
 Carry: Carry=A⋅B (AND gate)

Truth Table for Half Adder:

A B Sum (A ⊕ B) Carry (A ⋅ B)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Circuit Diagram:
1. Sum: Implemented using an XOR gate.
 2. Carry: Implemented using an AND gate.

Full Adder :- Full Adder is the circuit that consists of two EX-OR gates, two AND
gates, and one OR gate. Full Adder is the adder that adds three inputs and produces
two outputs which consist of two EX-OR gates, two AND gates, and one OR gate. The
first two inputs are A and B and the third input is an input carry as C-IN. The output
carry is designated as C-OUT and the normal output is designated as S which is SUM.

Logic Functions:
 Sum: Sum=A⊕B⊕Cin
(XOR gate used twice)
 Carry-out: Cout=(A⋅B)+(B⋅Cin)+(A⋅Cin)
(Combination of AND and OR gates)

Truth Table for Full Adder:

Carry-out (Cout
A B Cin Sum (A⊕B⊕Cin)
)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Multipliers :- Multipliers are essential components in digital circuits for performing
arithmetic operations. They come in various types, each suited for different
applications based on speed, complexity, power consumption, and area
requirements. Here's an overview of the main types of multipliers:

1. Array Multiplier
• Description: Uses a grid-like arrangement of AND gates and adders to
generate and sum partial products. It's based on the straightforward approach
of binary multiplication.
• Features:
• Simple to implement.
• High regularity in structure.
• Suitable for small-scale multiplications.
• Advantages: Easy to design and implement.
• Disadvantages: High area usage and significant propagation delay for large
operands.
• Applications: Basic processors and small embedded systems.

2. Booth Multiplier
• Description: Reduces the number of addition and subtraction operations by
encoding the multiplier bits, particularly useful for signed numbers in 2's
complement form.
• Features:
• Handles both positive and negative numbers efficiently.
• Works well with signed 2's complement representation.
• Advantages: Reduces the number of partial products, making it faster than
array multipliers.
• Disadvantages: Complex control logic.
• Applications: Signal processing and systems requiring efficient multiplication
of signed numbers.

3. Wallace Tree Multiplier

• Description: A fast multiplier that uses a tree-like structure to reduce the
number of adders and levels required to sum partial products.
• Features:
• Reduces critical path delay.
 • Employs carry-save adders (CSAs).
• Advantages: High-speed performance.
• Disadvantages: Complex to design and requires more interconnects,
increasing power consumption.
• Applications: High-speed digital signal processors (DSPs) and processors.

4. Serial Multiplier
• Description: Multiplies numbers by processing one bit at a time, typically in
sequential clock cycles.
• Features:
• Requires less hardware.
• Slower than parallel multipliers.
• Advantages: Low area and power consumption.
• Disadvantages: Slow processing speed.
• Applications: Low-power embedded systems.

5. Parallel Multiplier
• Description: Operates on all bits simultaneously to produce results faster.
Includes array and Wallace tree multipliers as examples.
• Features:
• High-speed operation.
• Requires more hardware.
• Advantages: Fast and efficient for high-performance applications.
• Disadvantages: High power and area requirements.
• Applications: High-speed processors and real-time systems.

6. Carry-Save Multiplier
• Description: Uses carry-save adders to reduce the delay caused by carry
propagation in addition.
• Features:
• Optimized for high-speed operations.
• Advantages: Faster than conventional array multipliers.
• Disadvantages: Relatively complex structure.
• Applications: High-speed computation systems like GPUs and DSPs.

7. Logarithmic Multiplier
• Description: Multiplies numbers using logarithmic transformations, where
multiplication is reduced to addition of logarithms.
• Features:
• Ideal for approximate computing.
 • Advantages: Energy-efficient for approximate operations.
• Disadvantages: Lower accuracy due to approximation.
• Applications: Image processing, machine learning, and neural networks.

8. Vedic Multiplier
• Description: Based on ancient Indian mathematics (Vedic sutras). Uses unique
methods to perform multiplication quickly and efficiently.
• Features:
• Optimized for small-sized multiplications.
• Advantages: Simple, scalable, and faster than traditional methods for small
operands.
• Disadvantages: Less efficient for large numbers without optimizations.
• Applications: Small embedded systems and arithmetic logic units.

9. Modified Booth Multiplier

• Description: An enhancement of the Booth multiplier, optimized for reducing
the number of operations further.
• Features:
• Uses encoding schemes to reduce partial products.
• Advantages: More efficient than the basic Booth multiplier.
• Disadvantages: Increased complexity in control logic.
• Applications: High-speed arithmetic and DSP systems.

10. Approximate Multiplier

• Description: Trades accuracy for power and speed by approximating the
multiplication process.
• Features:
• Suitable for applications where exact results are unnecessary.
• Advantages: Energy-efficient and fast.
• Disadvantages: Reduced precision.
• Applications: Machine learning, AI, image processing, and neural networks.
Comparison of Multiplier Types:
Multiplier Complexit Area Power
Speed Applications
Type y Usage Consumption
Array Moderat Basic processors, small
Simple High High
Multiplier e embedded systems
Booth Moderat Signal processing,
Fast Moderate Moderate
Multiplier e signed operations
Wallace Tree Very High-performance DSPs
Complex High High
Multiplier Fast and processors
Serial Very
Slow Low Low Low-power systems
Multiplier Simple
Parallel Very
Complex High High Real-time systems
Multiplier Fast
Vedic Moderat
Fast Moderate Moderate Arithmetic units
Multiplier e

Carry Look-Ahead Adder :- A Look-Ahead Carry Adder is a type of

digital binary adder designed to compute the carry signals in parallel to
speed up the addition process. It reduces the delay caused by sequential
carry propagation by using generate (G) and propagate (P) signals to
determine the carry for each bit position simultaneously, enabling faster
addition of multi-bit binary numbers.

• Generate (G) and Propagate (P) Signals:

• Generate (G): A carry is generated when both bits being added are 1.
Gi=Ai⋅Bi
• Propagate (P): A carry is propagated if at least one of the bits being added is 1.
Pi=Ai+Bi
 • Carry Calculation: The carry for a particular bit position (Ci+1) is determined
using the generate and propagate signals: Ci+1=Gi+(Pi⋅Ci) This allows the carry
to be computed directly for any bit position without waiting for previous
carries.

The carry output Boolean function of each stage in a 4 stage carry look-ahead
adder can be expressed as
C1 = C0.P0+G0.

C2 = C1.P1+G1 = ( C0.P0+G0).P1+G1.

C3 = C2.P2+G2 = (C1.P1+G1).P2+G2.

C4 = C3.P3+G3 = C0.P0.P1.P2.P3 + P3.P2.P1.G0 + P3.P2.G1 + G2.P3 + G3

Multiplication : Signed Operand Multiplication : -

Signed multiplication is a process of multiplying two numbers that can be either

positive or negative. In binary arithmetic, signed numbers are typically

represented using two's complement representation.

* Multiplicand

• The number that is being multiplied.

• It can be thought of as the base value that is repeated or scaled by the
multiplier.
• For example, in 3×4, the multiplicand is 3.

* Multiplier

• The number by which the multiplicand is multiplied.

• It determines how many times the multiplicand is added or scaled.
• For example, in 3×4, the multiplier is 4.

Multiplicand vs. Multiplier in Binary Multiplication

In binary arithmetic:

• The multiplicand is represented as the input value to be repeated.

• The multiplier dictates how many times the multiplicand is shifted and added.
For example: If A=1010 (10 in decimal) is the multiplicand and B=0011 (3 in decimal)
is the multiplier, the result is A×B=11110 (30 in decimal).

1. Registers: Two Registers B and Q are used to store multiplicand and multiplier
respectively. Register A is used to store partial product during multiplication.

Sequence Counter register (SC) is used to store number of bits in the multiplier.

2. Flip Flop: To store sign bit of registers we require three flip flops (A sign, B sign
and Q sign). Flip flop E is used to store carry bit generated during partial product
addition.

3. Complement and Parallel adder: This hardware unit is used in calculating

partial product i.e, perform addition required.
Flowchart of Multiplication:

Signed Multiplication Algorithm Explanation

1. Setup:

• Multiplicand is stored in the B register.

• Multiplier is stored in the Q register.
• Sign bits of B (Bs) and Q (Qs) are compared using an XOR operation:
• If the signs are the same, As (sign of result) = 0 (positive result).
• If the signs are different, As=1 (negative result).
• A register and E flip-flop are initialized to 0.
• A sequence counter (SC) is initialized to n (number of bits in the
multiplier).
2. Check the Least Significant Bit (LSB) of Q (Multiplier):

• If Qn=1:
• Add the Multiplicand (B) to the A register.
• Store the result in A, with any carry bit saved in the E flip-flop.
 • If Qn=0:
• Skip the addition.
3. Right Shift Operation:

• Shift the contents of E,A,Q (combined as one logical unit) to the right by
one position:
• The value in E moves to the most significant bit (MSB) of A.
• The LSB of A moves to the MSB of Q.
4. Decrement the Sequence Counter (SC):

• Subtract 1 from SC.

5. Repeat or End:

• If SC=0, stop the process. The final product is stored in A (higher bits)
and Q (lower bits).
• Otherwise, repeat from Step 2.
6. Final Adjustment:

• If As=1 (negative result), take the two's complement of the result to get
the correct signed product.

Booth’s Algorithm :-
Booth's algorithm is a method used to multiply binary numbers in signed 2's
complement format, designed to make the process more efficient by reducing the
number of additions or subtractions required. It works by taking advantage of
patterns in the multiplier, such as strings of consecutive 0's or 1's, to minimize
operations. Here's a breakdown of the approach in simpler terms:

1. No action for 0's: If a string of 0's is found in the multiplier, no operation is

needed for those bits — only shifting is done.

2. Handling consecutive 1's: If there's a string of 1's in the multiplier, you can
treat the sequence as a larger number and perform fewer operations,
essentially reducing the number of steps needed.

3. Deciding when to add or subtract:

• If you encounter a 1 after a 0 in the multiplier (i.e., the first "1" in a series
of 1's), subtract the multiplicand from the current result.
• If you encounter a 0 after a 1 (the first "0" in a series of 0's), add the
multiplicand to the current result.
• If the current multiplier bit is the same as the previous bit (i.e., no
change), then do nothing to the result.
The main idea is to look at the bits of the multiplier and decide whether to add,
subtract, or leave the partial product unchanged based on these patterns, and then
shift the result as needed. This helps speed up the multiplication process compared
to traditional methods.

Booth’s Algorithm Flowchart – We name the register as A, B and Q, AC,

BR and QR respectively. Qn designates the least significant bit of multiplier
in the register QR. An extra flip-flop Qn+1is appended to QR to facilitate a

double inspection of the multiplier. The flowchart for the booth algorithm is
shown below.
Array Multiplier :-
An array multiplier is a type of digital circuit used to perform binary multiplication. It
is a straightforward implementation of the multiplication process, and it uses an
array of AND gates and adders to compute the product of two binary numbers.

Basic Working of an Array Multiplier:

The multiplication of two binary numbers is similar to the long multiplication method
you might use with decimal numbers. For two binary numbers, the process consists
of the following steps:

1. Partial Product Generation: For each bit of the multiplier, you generate a
partial product by ANDing it with each bit of the multiplicand. This step
produces multiple rows of partial products, depending on the number of bits in
the two numbers being multiplied.

2. Addition of Partial Products: Once the partial products are generated, they
need to be added together to get the final result. This addition is done using
binary adders, such as full adders or half adders.

3. Final Sum: After the partial products are added, the final sum gives the result
of the multiplication.

Structure of an Array Multiplier:

• AND Gates: These are used to compute the partial products. Each bit of the
multiplier is ANDed with each bit of the multiplicand.
• Full Adders/Half Adders: These are used to add the partial products. The carry
from one addition is passed to the next adder.
• Rows and Columns: The array of AND gates and adders is arranged in a grid
or array, where the number of rows corresponds to the number of bits in the
multiplier, and the number of columns corresponds to the number of bits in
the multiplicand.

Example of an Array Multiplier (for 4-bit numbers):

Let’s say we want to multiply two 4-bit binary numbers:

• A=a3a2a1a0 (multiplicand)
• B=b3b2b1b0 (multiplier)

Step 1: Generate partial products using AND gates:

Each bit of B (the multiplier) is ANDed with each bit of A (the multiplicand). The result
is a set of partial products:
 • P0=a0⋅b0,a0⋅b1,a0⋅b2,a0⋅b3
• P1=a1⋅b0,a1⋅b1,a1⋅b2,a1⋅b3
• P2=a2⋅b0,a2⋅b1,a2⋅b2,a2⋅b3
• P3=a3⋅b0,a3⋅b1,a3⋅b2,a3⋅b3

Step 2: Add the partial products using adders:

Once the partial products are generated, the next task is to add them together using
binary addition. The rows of partial products are aligned, and the sums are calculated
in the form of a large binary number.

Step 3: Result:
The result of the addition of the partial products gives the final product of the
multiplication.

Advantages and Disadvantages of Array Multipliers:

• Advantages:

• Simple to understand and implement.

• Well-suited for hardware implementation.
• It can be designed with a fixed number of adders and gates, making it
predictable in terms of resources used.
• Disadvantages:

• The number of gates and adders increases rapidly as the bit-length of

the numbers increases. This results in a large area and high power
consumption, especially for larger bit-width multiplications.
• The delay due to the many stages of addition (propagation delay
through multiple adders) can become significant, especially for large
multiplications.

Division and logic algorithm :-

Division algorithms are used in digital systems to perform division operations, where
a dividend is divided by a divisor to produce a quotient and sometimes a remainder.
Division is generally more complex than addition, subtraction, or multiplication, as it
involves iterative approximation or manipulation of bits.

Here are common types of division algorithms:

1. Restoring Division Algorithm

This is a straightforward binary division technique that mimics long division.
Steps:
1. Initialize: Set the remainder to 0 and the quotient to 0.
2. Shift Left: Shift the current remainder and the next bit of the dividend into the
remainder register.
3. Subtract the Divisor: Subtract the divisor from the remainder.
• If the result is non-negative, set the corresponding quotient bit to 1.
• If the result is negative, restore the original remainder (by adding the
divisor back), and set the quotient bit to 0.
4. Repeat: Continue the process for the number of bits in the dividend.
5. Output: The quotient is in the quotient register, and the remainder is in the
remainder register.

Advantages:
• Simple to implement.
• Well-suited for small systems.

Disadvantages:
• Requires restoring the original remainder when subtraction results in a
negative value, which adds an extra step.

2. Non-Restoring Division Algorithm

This algorithm eliminates the need to restore the remainder, making it faster than the
restoring division method.

Steps:
1. Initialize: Set the remainder to 0 and the quotient to 0.
2. Shift Left: Shift the remainder and the next bit of the dividend into the
remainder register.
3. Condition Check:
• If the remainder is non-negative, subtract the divisor.
• If the remainder is negative, add the divisor.
4. Set Quotient Bit:
• If subtraction was performed, set the quotient bit to 1.
• If addition was performed, set the quotient bit to 0.
5. Repeat: Continue for the number of bits in the dividend.
6. Final Adjustment:
• If the remainder is negative after all iterations, add the divisor once to
get the final remainder.
7. Output: The quotient and adjusted remainder.
Advantages:
• Faster than the restoring division algorithm since it skips the restoring step.
• Efficient in hardware implementations.

Disadvantages:
• Slightly more complex control logic than restoring division.

3. Signed Division (Booth’s Approach for Division)

This algorithm handles signed binary numbers in 2's complement form, extending
techniques like Booth’s algorithm used for multiplication.

Steps:
1. Convert the dividend and divisor to positive if they are negative, keeping track
of their signs.
2. Perform binary division using restoring or non-restoring methods.
3. Adjust the quotient's sign based on the original signs of the dividend and
divisor.
4. Adjust the remainder's sign to match the dividend's sign.

Advantages:
• Handles signed operations efficiently.

Disadvantages:
• Requires additional checks and adjustments for signed values.

4. Digit-by-Digit (Decimal or Binary) Division

This method determines the quotient digit-by-digit, similar to how humans perform
decimal long division.

Steps:
1. Divide the leading digits of the dividend by the divisor to estimate the next
digit of the quotient.
2. Multiply the estimated quotient digit by the divisor and subtract it from the
current dividend portion.
3. Bring down the next digit from the dividend and repeat.
4. Continue until all digits of the dividend are processed.

Advantages:
• Suitable for operations where precision matters, such as floating-point division.

Disadvantages:
• Iterative and time-consuming.
5. Newton-Raphson Division (Iterative Approximation)
This algorithm approximates division using reciprocal values. It is widely used in
floating-point arithmetic.

Concept:
• Division is represented as Q=D×R, where Q is the quotient, D is the divisor, and
R is the reciprocal of D.
• The reciprocal R is calculated iteratively using Newton-Raphson iteration: Rn+1
=Rn(2−D×Rn)
• Once R converges, the quotient is computed as Q=Dividend×R.

Advantages:
• Very fast for high-precision division.
• Suitable for floating-point units (FPUs).

Disadvantages:
• Requires additional hardware or software for iterative approximation.

6. SRT Division (Speed-Radix-Two Division)

SRT division is named after its inventors (Sweeney, Robertson, and Tocher). It uses a
lookup table to simplify partial product estimation.

Concept:
• The quotient is calculated using a radix-based representation (typically radix-2
or radix-4).
• The process involves generating partial remainders and using them to
determine the next quotient digit from a precomputed table.

Advantages:
• Reduces the number of iterations compared to other methods.
• Efficient for hardware implementation in processors.

Disadvantages:
• Requires additional logic for table lookup.
Comparison of Division Algorithms
Complexit
Algorithm Speed Applications
y
Basic hardware and
Restoring Division Slow Simple
educational tools
Non-Restoring Faster than
Moderate Hardware implementation
Division Restoring
Signed Division Moderate Moderate Processors and ALUs
Digit-by-Digit Division Slow Simple Software-based division
Newton-Raphson
Very Fast Complex Floating-point arithmetic
Division
SRT Division Fast Moderate High-speed CPUs and FPUs

Restoring Division Algorithm for Unsigned Integer :-

Restoring division is usually performed on the fixed point fractional numbers. When we
perform division operations on two numbers, the division algorithm will give us two things,
i.e., quotient and remainder. This algorithm is based on the assumption that 0 < D < N. With
the help of digit set {0, 1}, the quotient digit q will be formed in the restoring division
algorithm. The division algorithm is generally of two types, i.e., fast algorithm and slow
algorithm. Goldschmidt and Newton-Raphson are the types of fast division algorithm, and
STR algorithm, restoring algorithm, non-performing algorithm, and the non-restoring
algorithm are the types of slow division algorithm.

In this section, we are going to perform restoring algorithm with the help of an unsigned
integer. We are using restoring term because we know that the value of register A will be
restored after each iteration. We will also try to solve this problem using the flow chart and
apply bit operations.
Here, register Q is used to contain the quotient, and register A is used to contain the
remainder. Here, the divisor will be loaded into the register M, and n-bit divided will be
loaded into the register Q. 0 is the starting value of a register. The values of these types of
registers are restored at the time of iteration. That's why it is known as restoring.

Now we will learn some steps of restoring division algorithm, which is described as follows:

Step 1: In this step, the corresponding value will be initialized to the registers, i.e., register
A will contain value 0, register M will contain Divisor, register Q will contain Dividend, and N
is used to specify the number of bits in dividend.

Step 2: In this step, register A and register Q will be treated as a single unit, and the value
of both the registers will be shifted left.

Step 3: After that, the value of register M will be subtracted from register A. The result of
subtraction will be stored in register A.

Step 4: Now, check the most significant bit of register A. If this bit of register A is 0, then
the least significant bit of register Q will be set with a value 1. If the most significant bit of A
is 1, then the least significant bit of register Q will be set to with value 0, and restore the
value of A that means it will restore the value of register A before subtraction with M.
 Step 5: After that, the value of N will be decremented. Here n is used as a counter.

Step 6: Now, if the value of N is 0, we will break the loop. Otherwise, we have to again go to
step 2.

Step 7: This is the last step. In this step, the quotient is contained in the register Q, and the
remainder is contained in register A.

For example:

In this example, we will perform a Division restoring algorithm.

1. Dividend = 11
2. Divisor = 3

N M A Q Operation

4 00011 00000 1011 Initialize

00011 00001 011_ Shift left AQ

00011 11110 011_ A=A-M

Q[0] = 0 And restore

00011 00001 0110
A

3 00011 00010 110_ Shift left AQ

00011 11111 110_ A=A-M

00011 00010 1100 Q[0] = 0

2 00011 00101 100_ Shift left AQ

00011 00010 100_ A=A-M

00011 00010 1001 Q[0] = 1

1 00011 00101 001_ Shift left AQ

00011 00010 001_ A=A-M

00011 00010 0011 Q[0] = 1

So we should not forget to restore the value of the most significant bit of A, which is 1. So,
register A contains the remainder 2, and register Q contains the quotient 3.
Floating Point Arithmetic Operation :-
Floating-point arithmetic is used to represent and manipulate real numbers in
computer systems, enabling a wide range of numerical computations with varying
magnitudes and precision. Unlike fixed-point arithmetic, which represents numbers
with a fixed number of digits after the decimal point, floating-point arithmetic can
handle very small and very large values efficiently by dynamically adjusting the
position of the decimal (or binary) point.

Floating-Point Representation
Floating-point numbers are generally represented in the IEEE 754 standard, which
consists of three main components:

1. Sign (S):
• A single bit that determines the sign of the number.
• 0 for positive numbers and 1 for negative numbers.
2. Exponent (E):
• Encodes the magnitude or scale of the number, often stored in a biased
format to allow both positive and negative exponents.
3. Mantissa (M) (or significand):
• Represents the significant digits of the number. In normalized form, the
leading digit is implicitly 1 (not stored explicitly in binary representation).

IEEE 754 Formats:

1. Single-Precision (32-bit):
• 1 bit for sign, 8 bits for exponent, 23 bits for mantissa.
2. Double-Precision (64-bit):
• 1 bit for sign, 11 bits for exponent, 52 bits for mantissa.

A floating-point number in IEEE 754 format is represented as:

Value=(−1)S×(1.M)×2E−Bias

• Bias is a constant used to interpret the exponent (e.g., 127 for single-precision,
1023 for double-precision).

Floating-Point Arithmetic Operations :-

1. Addition and Subtraction

2. Multiplication

3. Division
FLOATING POINT ADDITION :-
To understand floating point addition, first we see addition of real numbers in
decimal as same logic is applied in both cases.

For example, we have to add 1.1 * 103 and 50.

We cannot add these numbers directly. First, we need to align the exponent and then,
we can add significant.

After aligning exponent, we get 50 = 0.05 * 103

Now adding significant, 0.05 + 1.1 = 1.15
So, finally we get (1.1 * 103 + 50) = 1.15 * 103
Here, notice that we shifted 50 and made it 0.05 to add these numbers.
Now let us take example of floating point number addition
We follow these steps to add two numbers:

1. Align the significant

2. Add the significant

3. Normalize the result

Let the two numbers be

x = 9.75
y = 0.5625

Converting them into 32-bit floating point representation,

9.75’s representation in 32-bit format = 0 10000010 00111000000000000000000

0.5625’s representation in 32-bit format = 0 01111110 00100000000000000000000
Now we get the difference of exponents to know how much shifting is required.

(10000010 – 01111110)2 = (4)10

Now, we shift the mantissa of lesser number right side by 4 units.

Mantissa of 0.5625 = 1.00100000000000000000000

(note that 1 before decimal point is understood in 32-bit representation)

Shifting right by 4 units, we get 0.00010010000000000000000

Mantissa of 9.75 = 1. 00111000000000000000000
Adding mantissa of both

0. 00010010000000000000000
+ 1. 00111000000000000000000
————————————————-

1. 01001010000000000000000
In final answer, we take exponent of bigger number

So, final answer consist of :

Sign bit = 0
Exponent of bigger number = 10000010
Mantissa = 01001010000000000000000
32 bit representation of answer = x + y = 0 10000010 01001010000000000000000

FLOATING POINT SUBTRACTION :-

Subtraction is similar to addition with some differences like we subtract mantissa

unlike addition and in sign bit we put the sign of greater number.

Let the two numbers be

x = 9.75
y = – 0.5625

Converting them into 32-bit floating point representation

9.75’s representation in 32-bit format = 0 10000010 00111000000000000000000
– 0.5625’s representation in 32-bit format = 1 01111110 00100000000000000000000
Now, we find the difference of exponents to know how much shifting is required.

(10000010 – 01111110)2 = (4)10

Now, we shift the mantissa of lesser number right side by 4 units.
Mantissa of – 0.5625 = 1.00100000000000000000000
(note that 1 before decimal point is understood in 32-bit representation)

Shifting right by 4 units, 0.00010010000000000000000

Mantissa of 9.75= 1. 00111000000000000000000
Subtracting mantissa of both

0. 00010010000000000000000
– 1. 00111000000000000000000
————————————————

1. 00100110000000000000000
Sign bit of bigger number = 0
So, finally the answer = x – y = 0 10000010 00100110000000000000000

In this continuation of the previous set, we will cover some more concepts and
operations involved in computer arithmetic:
 1.Signed vs. unsigned numbers: In computer arithmetic, numbers can be either

signed or unsigned. Unsigned numbers only represent positive values, while

signed numbers can represent both positive and negative values. Signed numbers

are typically represented using two’s complement notation.

2.Shift operations: Shift operations are used to move the bits of a number left or

right. A left shift multiplies the number by 2 raised to the power of the number of

shifted bits, while a right shift divides the number by 2 raised to the power of the

number of shifted bits.

3.Logical vs. arithmetic shifts: Shift operations can be either logical or arithmetic.

Logical shifts insert zeros into the vacant bit positions, while arithmetic shifts

preserve the sign bit when shifting a signed number.

4.Carry and borrow: In addition and subtraction operations, carry and borrow

refer to the bit that is carried over or borrowed from the next digit position when

the result of an operation exceeds the number of bits available.

5.Boolean algebra: Boolean algebra is a branch of mathematics that deals with

logical operations on binary variables. It is widely used in computer arithmetic for

operations such as bitwise AND, OR, and XOR.

6.Fixed-point arithmetic: Fixed-point arithmetic is used to perform arithmetic

operations on numbers with a fixed number of decimal places. It is commonly

used in applications such as digital signal processing.

7.Division algorithms: There are various algorithms used to perform division in

computer arithmetic, including the restoring division algorithm, non-restoring

division algorithm, and SRT division algorithm.

8.Multiplication algorithms: There are also various algorithms used to perform

multiplication in computer arithmetic, including the Booth’s algorithm, the array

multiplier, and the Wallace tree multiplier.

Overall, computer arithmetic is a complex and important field that underlies many
aspects of modern computing. It involves a wide range of concepts and operations,
from basic addition and subtraction to advanced algorithms for multiplication and
division.

Floating-Point Multiplication:-
Floating-point multiplication involves multiplying two numbers represented in
floating-point format. It operates on the mantissa, exponent, and sign of the
numbers separately, following specific steps to ensure proper computation while
adhering to the IEEE 754 standard.

Steps for Floating-Point Multiplication

1. Determine the Sign:

• XOR the sign bits of the two numbers.

• Result:
• Positive if the signs are the same.
• Negative if the signs are different.
2. Add the Exponents:

• Add the exponents of the two numbers.

• Subtract the bias to adjust for the representation: Eresult=E1+E2−Bias
• Bias values:
• 127 for single-precision.
• 1023 for double-precision.
3. Multiply the Mantissas:

• Multiply the significands of the two numbers.

• The result may exceed the normalized range (1.0≤M<2.0), requiring
normalization.
4. Normalize the Result:

• If the product of the mantissas is not in normalized form (leading digit

not 1), shift the mantissa and adjust the exponent.
5. Handle Special Cases:

• Zero: Multiplication by zero results in zero.

• Infinity: Multiplying by infinity results in infinity (sign depends on
operand signs).
• NaN: Multiplication involving NaN produces NaN.
6. Round the Result:

• Apply rounding to fit the mantissa into the available bits.

 7. Format the Result: Combine the sign, exponent, and mantissa into the final
floating-point representation.

Example: Multiply 6.75 and 0.25

Step 1: Represent the Numbers in IEEE 754 Format

• 6.75 (Single-Precision):

• Binary: 110.11 = 1.1011×22

• Sign = 0, Exponent = 2+127=129, Mantissa = 101100...0
• Representation: 01000000110110000000000000000000
• 0.25 (Single-Precision):

• Binary: 0.01 = 1.0×2−2

• Sign = 0, Exponent = −2+127=125, Mantissa = 000000...0
• Representation: 00111110100000000000000000000000
Step 2: Perform Multiplication
1. Determine the Sign:

• Sign = 0(positive).
2. Add Exponents:

• 129+125−127=127.
3. Multiply Mantissas:

• Mantissas: 1.1011×1.0=1.1011.
• Result = 1.1011.
4. Normalize the Result:

• Already normalized: 1.1011×20.

5. Result:

• Sign = 0, Exponent = 127, Mantissa = 101100...0.

• Representation: 00111111110110000000000000000000.

Step 3: Convert Back to Decimal

• (−1)0×1.1011×20=1.6875.
• Decimal = 6.75×0.25=1.6875.

Floating-Point Division:-
Floating-point division is the process of dividing two floating-point numbers,
following IEEE 754 standard representation. It operates on the sign, exponent, and
mantissa separately to calculate the result. Careful handling of normalization,
rounding, and special cases is required.

Steps for Floating-Point Division

1. Determine the Sign:

• XOR the sign bits of the dividend and divisor.

• Result:
• Positive if the signs are the same.
• Negative if the signs are different.
2. Subtract the Exponents:

• Subtract the exponent of the divisor from the exponent of the dividend
and adjust for bias: Eresult=Edividend−Edivisor+Bias
• Bias values:
• 127 for single-precision.
• 1023 for double-precision.
3. Divide the Mantissas:
 • Divide the mantissas (significands) of the dividend and divisor.
• The result may fall out of the normalized range (1.0≤M<2.0).
4. Normalize the Result:

• If the result of the mantissa division is not normalized, shift the mantissa
and adjust the exponent accordingly.
5. Round the Result:

• Apply rounding to fit the mantissa into the available precision bits.
6. Handle Special Cases:

• Zero:
• Dividing zero by a non-zero number results in zero.
• Dividing a non-zero number by zero results in infinity.
• Infinity:
• Dividing infinity by a finite number results in infinity.
• Dividing a finite number by infinity results in zero.
• NaN:
• Division involving NaN produces NaN.
7. Format the Result:

• Combine the calculated sign, exponent, and mantissa into the final
floating-point representation.
Example: Divide 6.75 by 0.25
Step 1: Represent the Numbers in IEEE 754 Format
• 6.75 (Single-Precision):

• Binary: 110.11 = 1.1011×22

• Sign = 0, Exponent = 2+127=129, Mantissa = 101100...0
• Representation: 01000000110110000000000000000000
• 0.25 (Single-Precision):

• Binary: 0.01 = 1.0×2−2

• Sign = 0, Exponent = −2+127=125, Mantissa = 000000...0
• Representation: 00111110100000000000000000000000

Step 2: Perform Division

1. Determine the Sign:

• Sign = 0(positive).
2. Subtract Exponents:

• 129−125+127=131.
3. Divide Mantissas:

• Mantissas: 1.1011÷1.0=1.1011.
• Result = 1.1011.
4. Normalize the Result:

• Already normalized: 1.1011×24.

5. Result:

• Sign = 0, Exponent = 131, Mantissa = 101100...0.

• Representation: 01000001110110000000000000000000.

Step 3: Convert Back to Decimal

• (−1)0×1.1011×24=27.0.
• Decimal = 6.75÷0.25=27.0.
Micro operations :-
Micro operations are the basic operations executed at the hardware level, performed
on data within CPU registers or between registers and memory. These low-level
instructions define how higher-level CPU instructions (machine-level instructions) are
executed step by step.

Types of Microoperations
1. Data Transfer Microoperations
These operations move data from one location to another, such as between registers
or between registers and memory.

• Purpose: Transfer information without alteration.

• Example:
• R1←R2: Copy the content of R2 into R1.
• Memory[MAR]←R1: Store the value of R1 into memory at the address
stored in the Memory Address Register (MAR).

2. Arithmetic Microoperations
These perform basic arithmetic calculations like addition, subtraction, increment, and
decrement.

• Examples:
• Addition: R1←R2+R3 Add the contents of R2 and R3, store the result in
R1.
• Subtraction: R1←R2−R3 Subtract R3 from R2, store the result in R1.
• Increment: R1←R1+1 Increase the content of R1 by 1.
• Decrement: R1←R1−1 Decrease the content of R1 by 1.

3. Logical Microoperations
These perform bitwise logical operations on the binary data of registers.

• Operations:
• AND: R1←R2ANDR3 Perform bitwise AND on R2 and R3, store the result
in R1.
• OR: R1←R2ORR3 Perform bitwise OR on R2 and R3, store the result in R1.
• XOR: R1←R2XORR3 Perform bitwise XOR on R2 and R3, store the result in
R1.
• NOT: R1←NOTR2 Perform bitwise negation (complement) on R2, store
the result in R1.
4. Shift Microoperations
These operations shift the binary content of a register to the left or right. Shifting can
be logical, arithmetic, or circular.

• Types:
1. Logical Shift:

• Fills vacated bit positions with 0.

• Example:
• Logical left shift: R1←shlR1.
• Logical right shift: R1←shrR1.
2. Arithmetic Shift:

• Preserves the sign bit (used for signed numbers).

• Example:
• Arithmetic right shift: The leftmost bit remains unchanged
to maintain the number's sign.
3. Circular Shift (Rotate):

• Bits that are shifted out from one end are reintroduced at the
opposite end.
• Example:
• Circular left shift: Rotate bits left.
• Circular right shift: Rotate bits right.

Detailed Examples
1. Data Transfer Microoperation:

• Instruction: R1←R2.
• Meaning: The content of register R2 is copied into R1. The original value
in R2 remains unchanged.
2. Arithmetic Microoperation:

• Instruction: R1←R2+R3.
• Meaning: Add the contents of R2 and R3, and store the result in R1.
3. Logical Microoperation:

• Instruction: R1←R2XORR3.
• Meaning: Perform bitwise XOR on the binary contents of R2 and R3, and
store the result in R1.
4. Shift Microoperation:

• Instruction: R1←shlR1.
 • Meaning: Perform a logical left shift on R1, moving all bits one position
to the left, and filling the rightmost position with 0.

Arithmetic Logic Unit Design :-

The Arithmetic Logic Unit (ALU) is the heart of any CPU. An ALU performs three kinds
of operations, i.e.

• Arithmetic operations such as Addition/Subtraction,

• Logical operations such as AND, OR, etc. and

• Data movement operations such as Load and Store

ALU derives its name because it performs arithmetic and logical operations. A simple

ALU design is constructed with Combinational circuits. ALUs that perform

multiplication and division are designed around the circuits developed for these

operations while implementing the desired algorithm. More complex ALUs are

designed for executing Floating point, Decimal operations and other complex

numerical operations. These are called Coprocessors and work in tandem with the

main processor.

The design specifications of ALU are derived from the Instruction Set Architecture.

The ALU must have the capability to execute the instructions of ISA. An instruction

execution in a CPU is achieved by the movement of data/datum associated with the

instruction. This movement of data is facilitated by the Datapath. For example, a

LOAD instruction brings data from memory location and writes onto a GPR. The

navigation of data over datapath enables the execution of LOAD instruction. We

discuss Datapath more in details in the next chapter on Control Unit Design. The

trade-off in ALU design is necessitated by the factors like Speed of execution,

hardware cost, the width of the ALU.

Combinational ALU
A primitive ALU supporting three functions AND, OR and ADD is explained in figure

11.1. The ALU has two inputs A and B. These inputs are fed to AND gate, OR Gate and

Full ADDER. The Full Adder also has CARRY IN as an input. The combinational logic

output of A and B is statically available at the output of AND, OR and Full Adder. The

desired output is chosen by the Select function, which in turn is decoded from the

instruction under execution. Multiplexer passes one of the inputs as output based on

this select function. Select Function essentially reflects the operation to be carried out

on the operands A and B. Thus A and B, A or B and A+B functions are supported by

this ALU. When ALU is to be extended for more bits the logic is duplicated for as

many bits and necessary cascading is done. The AND and OR logic are part of the

logical unit while the adder is part of the arithmetic unit.

The simplest ALU has more functions that are essential to support the ISA of the CPU.
Therefore the ALU combines the functions of 2's complement, Adder, Subtractor, as
part of the arithmetic unit. The logical unit would generate logical functions of the
form f(x,y) like AND, OR, NOT, XOR etc. Such a combination supplements most of a
CPU's fixed point data processing instructions.