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Lab1 Quartus

The document provides a comprehensive guide for installing and using Quartus software for FPGA design at National Taiwan University. It covers installation steps, project creation, code compilation, and programming the FPGA, along with common debugging issues. Additionally, it outlines necessary configurations and potential errors to watch for during the design process.

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歐信泓
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14 views18 pages

Lab1 Quartus

The document provides a comprehensive guide for installing and using Quartus software for FPGA design at National Taiwan University. It covers installation steps, project creation, code compilation, and programming the FPGA, along with common debugging issues. Additionally, it outlines necessary configurations and potential errors to watch for during the design process.

Uploaded by

歐信泓
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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NTUEE DCLAB

Quartus Installation & Design Flow

Graduate Institute of Electronics Engineering


National Taiwan University
Outline
• Quartus installation
– Install devices
– License setup
– Install USB driver
• Quartus design flow
– Create new project
– Import qsf
• Put your code to FPGA
– Compile and program
• Debugging and compiling FAQ

NTU / DCS Lab 2


Download & Run Installer
• Download library and installation files
– Register and download from Altera website
– Or download from https://reurl.cc/G58KeD

NTU / DCS Lab 3


Install Devices
• Tools -> Install Devices
• Choose the library (qdz files) you downloaded
– Note that DE2-115 belongs to Cyclone IV family

NTU / DCS Lab 4


License Setup
• Tools -> License Setup
• This is only available when you are using NTU IP

[email protected]

NTU / DCS Lab 5


Install USB Driver for Windows
• The driver is under drivers/usb-blaster/ directory under
Quartus installation path
• Plus the USB cable and open following path
– 我的電腦 -> (右鍵)內容 -> 硬體 -> 裝置管理員
• Choose your device and the driver from the directory

NTU / DCS Lab 6


Outline
• Quartus installation
– Install devices
– License setup
– Install USB driver
• Quartus design flow
– Create new project
– Import qsf
• Put your code to FPGA
– Compile and program
• Debugging and compiling FAQ

NTU / DCS Lab 7


Create New Project
• File -> New Project Wizard
• The name of the top-level design is “DE2_115”

NTU / DCS Lab 8


Add Files
• Add files
– *.sv
– *.sdc

NTU / DCS Lab 9


Set the Device
• Select EP4CE115F29C7

NTU / DCS Lab 10


A Subtle Configuration
• Some error might occur if this step is skipped

NTU / DCS Lab 11


Import qsf
• Assignment -> Import Assignments
– Select the given qsf file (/src/DE2_115/DE2_115.qsf)

NTU / DCS Lab 12


Outline
• Quartus installation
– Install devices
– License setup
– Install USB driver
• Quartus design flow
– Create new project
– Import qsf
• Put your code to FPGA
– Compile and program
• Debugging and compiling FAQ

NTU / DCS Lab 13


Compile Your Code
• Press “Ctrl+L” or the purple play button
– Converts the code to the format that FPGA recognizes
– Including synthesis, place and route, fitting, etc.
– Generates a sof file (/output_files/DE2_115.sof)

• Check if there are errors or warnings


– Modify your code if necessary
NTU / DCS Lab 14
Before Programming FPGA
• Make sure
– Blaster USB cable is connected
– Power of FPGA is on
– The switch on the bottom left is set to RUN

NTU / DCS Lab 15


Program the FPGA
• Hardware Setup -> Add File -> Run -> Success

• If you prefer CLI, check this link


NTU / DCS Lab 16
Outline
• Quartus installation
– Install devices
– License setup
– Install USB driver
• Quartus design flow
– Create new project
– Import qsf
• Put your code to FPGA
– Compile and program
• Debugging and compiling FAQ

NTU / DCS Lab 17


My Verilog Pass Simulation but Don’t Work on FPGA
• Some code can not be compiled to hardware
– Modify your code if there is any WARNING about Combinational
Loop or Inferred Latch

• Common warnings/errors of code that is not synthesizable


– 22011 Combinational Loop
– 22013 Asynchronous Loop
– 22014 Synchronous Loop
– 22051 (Verilog) Generated Reset
– 22052 (Verilog) Generated Clock
– 22082 Port Not Connected
– 23003 Inferred Latch
– 23006 (Verilog) Incomplete Case Expression with Default Clause
– 23007 (Verilog) Case Statement Not Fully Specified
– 25001 Signal with No Driver

NTU / DCS Lab 18

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