Volume 8, Issue 7, July 2023 International Journal of Innovative Science and Research Technology

ISSN No:-2456-2165

Implementation of Luby Transform Error

Correcting Codes on FPGA
1
K. L. Sudha, 2Ganesh Gowda, 3Gagan K.P, 4Adarsh Reddy P.
1
Professor, 2,3,4UG Students,
Dept.of ECE DSCE, Bengaluru, INDIA

Abstract:- Luby Transform (LT) codes are rate less distribution. Paper [5] revisits the fountain codes and
codes which are a type of fountain codes. They provide proposes a research work which uses fountain coding in
good performance over other fountain codes because, encoding processes for wireless channel transmissions. An.
more efficient encoding and decoding algorithms can be improved encoding scheme for LT codes is designed in
devised for this code. These codes are rate less codes paper [6] by classifying the information nodes according to
because they allow for flexible and adaptive rate their degrees to reduce the error floor. Paper by Khaled F
allocation during the encoding process. With this, any [7] proposes memory based LT codes for 5G network and
desired code rate can be achieved by controlling the beyond. Fountain codes and their applications in wireless
number of parity symbols generated during the communication system have been dealt in paper [8].
encoding process. This paper explains the encoding and Systematic LT codes have been used as channel coding
decoding aspects of LT codes in detail and generation technique by authors of paper [9] to transfer AES encrypted
and decoding is performed using MATLAB. Hardware Image on BPSK over AWGN channel. Paper [10] explains
implementation of LT code is attempted on FPGA by the usage of LT codes for error correction in storage devices
using Verilog code. As it is shown, the codes are very and has shown that the performance of Lower Triangular
simple to implement and can be used as a more powerful Matrix-LT codes perform better compared to the traditional
error correcting codes. schemes such as RSD used in Distributed Storage System.
Authors of paper[11] have implemented LT codes on
Keywords:- Forward error correction, Rate less codes, Arduino board and NRF transceivers.Maintaining the
Verilog, FPGA. Integrity of the Specifications
I. INTRODUCTION III. LT ENCODING AND DECODING
Forward error correction in wireless communication is A. Encoding algorithm:
one of the important aspects to see that reliable transmission The LT code works by dividing the original message
happens over noisy channel. Rate less codes are types of into a set of small packets, each of which is independently
codes which adjust its rate as per the channel conditions and encoded using a random linear code. This means that each
were originally developed to attain efficient transmission in packet is multiplied by a randomly generated matrix of
erasure channels. Luby transform (LT) codes are the first coefficients, resulting in a unique code word for that packet.
practical realization of rate less codes which was suggested The coefficients used in this process are chosen from a finite
by Luby in his paper [1], published in 2002. It is a type of field, such as GF(2). Actually it is a linear block code which
Fountain code. In the fountain codes, the transmitter sends is generated with a sparse generator.
encoded blocks over the channel which alters the number of
encoded bits depending on the channel’s properties [3].
Raptor codes [2] are the extension of LT CODE.

II. LITERATURE REVIEW

M. Luby introduced LT codes in 2002[1] which are

rate less codes. He gave encoding and decoding algorithms
and showed that they provide a flexible and adaptive
mechanism for adjusting the code rate, and can achieve
near-optimal error correction performance with a small
number of parity symbols. David J.C MacKay[2] proposed
an improved LT coded and called it as Raptor code where in
an extra layer of channel coding is introduced. Paper [3]
studies the performance of two classes of rateless codes-LT
and Raptor codes on noisy channels and concludes that
Raptor codes outperform LT codes, and have good
performance on a wide variety of noisy channels. Authors of
paper [4] proposes a modified encoding scheme for LT
codes that maximizes the minimum variable-node degree for
transmission over binary erasure channels. The proposed
scheme leads to an almost-regular variable-node degree

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Volume 8, Issue 7, July 2023 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165

Fig. 1(a): Message partitioning and packet forming Fig. 1(b):flow chart for encoding

The generator matrix for an LT (Luby Transform)  Solving the linear system: The receiver uses the
code is generated using a random linear code construction. submatrix to solve a linear system of equations, where
The construction process involves the following steps: the unknowns are the message packets. This involves
 Message partitioning: The original message to be encoded inverting the submatrix (if it is full rank) or solving the
is divided into a set of packets, each of which is assigned system using a linear solver.
a unique identifier. Red dots in fig(1a) indicates that the  Message reconstruction: Once the linear system is
sequence of bits are divided in to 8 message blocks. solved, the receiver obtains estimates for the message
 Coefficient generation: A set of random coefficients is packets. If the estimates are correct, the original message
generated for each packet, using a pseudorandom number can be reconstructed by concatenating the packets in
generator. The coefficients are typically chosen from a their correct order.
finite field. This is called degree distribution. This is done  Iterative decoding: If the original message is not
with codebook creation and generation of random correctly reconstructed, the receiver can repeat the
numbers. decoding process with additional received packets. This
 Packet encoding: Each packet is multiplied by its involves constructing a new submatrix of the generator
corresponding set of coefficients based on degree matrix that includes the new packets and the rows that
distribution, to create a unique code word. The code were not used in the previous iteration. The linear system
words for all packets are concatenated to form the is then solved again to obtain improved estimates for the
generator matrix for the LT code. Code words are shown message packets.
as blue square boxes in fig(1)
The actual decoding process (shown in fig 2a and b )
The generator matrix is then used to encode the first identifies received packets with degree one, where each
message into a set of coded packets, which are transmitted of these packets is a symbol. These symbols are placed into
to the receiver. At the receiver, the coded packets are a buffer denoted as a ripple. Then, each of these symbols rj
decoded using a probabilistic decoding algorithm, which is taken out from the ripple to decode all the other packets
relies on the properties of the generator matrix to recover with a degree more than one. For a packet ci, if it contains rj
the original message with high probability. , an XOR operation is performed between rj and ci which
results in reducing the degree of ci by one as the symbol rj is
B. Decoding algorithm for LT code eliminated from packet ci. Moreover, after the XOR
The decoding algorithm for an LT (Luby Transform) operation, if the degree of ci becomes one, then ci is reduced
code is a probabilistic algorithm that uses the generator to a symbol. This newly recovered symbol is then moved
matrix of the code to recover the original message with high into the ripple if it is not found in the ripple.
probability. The decoding process involves the following
steps:
 Packet reception: The receiver collects a set of coded
packets transmitted by the sender. Each packet includes
an identifier and a set of coefficients.
 Matrix construction: A submatrix of the generator matrix
is constructed using the identifiers of the received
packets. The submatrix includes only the rows
corresponding to the received packets, and its columns
correspond to the coefficients used to generate the
packets.

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Volume 8, Issue 7, July 2023 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165

Fig. 2(a): Decoding algorithm with flow chart

The process of taking a symbol out from the ripple for Otherwise, the process is said to be successful since all
decoding other packets and placing newly recovered symbols are decoded.
symbols into the ripple is repeated until the ripple is
exhausted. The ecoding process fails if there is at least one The simulation of encoding and decoding of LT code
symbol yet to be discovered when the ripple is empty. is done in MATLAB simulation tool. Figures 3,4,5 shows
the encoding process and decoded messages.

Fig. 3: Creation of Message blocks

Fig. 4: Generating Code book

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Volume 8, Issue 7, July 2023 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165

Fig. 5: Random number generation, Encoded, Decoded data

IV. IMPLEMENTATION ON FPGA algorithms using Verilog code. The DE10-Lite presents a
robust hardware design platform built around the Altera
FPGA (Field-Programmable Gate Array) boards are MAX 10 FPGA. The MAX 10 FPGA shown in fig(6) is
highly versatile and powerful devices that offer numerous well equipped to provide cost effective, single-chip
benefits across a wide range of applications. They allow solutions in control plane or data path applications and
users to create hardware designs by programming the industry-leading programmable logic for ultimate design
underlying logic gates and interconnections. They provide flexibility.
excellent performance by allowing parallel processing
capability and re-configurability. FPGA boards are valuable Verilog code is dumped into DE10 Lite FPGA board
tools that combine the flexibility of software with the in Quartus Prime Integrated Development Environment
performance of hardware. Their customizable nature, high (IDE) with modelsim simulation tool. The software will
performance, and suitability for a wide range of applications perform synthesis, place and route, and generate the
make them an excellent choice for prototyping, accelerating programming file when Verilog code is compiled (fig(7).
computations, and implementing specialized hardware After configuring the FPGA, verification and testing is done
designs. In this work, LT codes encoding and decoding is for the program. Fig(8) shows the encoded data after
implemented on DE10 Lite FPGA Board by writing the running the Verilog code.

Fig. 6: DE10 Lite FPGA Board

Fig. 7: Verilog code

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Volume 8, Issue 7, July 2023 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165

Fig. 8: Luby transform codes generation and decoding

The advantage of the LT approach is that it can REFERENCES

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Volume 8, Issue 7, July 2023 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
Triangular Matrix-Luby Transform Codes”
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