Unit-3

Combinational Logic
Circuit Design
 Outline
 Looping
• Combinational circuits:
• analysis procedure/design procedure
• Binary adder-subtractor
• Half adder/Full adder/Half subtractor/Full subtractor
• Binary adder-subtractor
• Code converters
• Binary to Gray Code Converter
• Decoders/Encoders
• Multiplexers
• 2X1, 4X1,8X1 etc..
• Implementation of Boolean function/Logic function generators using mux
• Memories:
• random-access memory
• memory decoding.
Section - 1
Section - 1
Half Adder
 A combinational circuit which adds two one-bit binary numbers is called a half-adder.
Inputs Outputs
A
A B Sum Carry S=A⊕B
B
0 0 0 0
0 1 1 0
C = AB
1 0 1 0
1 1 0 1
 The sum column resembles like an output of the XOR gate.
 The carry column resembles like an output of the AND gate.
 Limitations:
 In multi-digit addition we have to add two bits along with the carry of previous digit addition. Such addition
requires addition of 3 bits. This is not possible in half-adders.

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Combinational circuit

• A combinational circuit consists of logic gates whose outputs at any time are
determined from only the present combination of inputs.

• In contrast, sequential circuits

employ storage elements in addition to logic gates.
• Their outputs are a function of the
inputs and the state of the storage elements. Because the state of the storage elements
is a function of previous inputs, the outputs of a sequential circuit depend not only on
present values of inputs, but also on past inputs, and the circuit behavior must be
specified by a time sequence of inputs and internal states.
• Logic circuits for digital systems may be combinational or sequential

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Combinational circuit
The design procedure of combinational circuits involves the following steps:

1. From the specifications of the circuit, determine the required number of inputs
and outputs and assign a symbol to each

2. Derive the truth table that defines the required relationship between inputs and output.

3. Obtain the simplified Boolean functions for each output as a function of the input variables.

4. Draw the logic diagram and verify the correctness of the design (manually or by simulation).

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Full Adder
 The full-adder adds the bits A and B and the carry from the previous column called carry-in Cin
and outputs the sum bit S and the carry bit called carry-out Cout.(3 one-bit binary numbers )

Inputs Outputs
S = A’B’Cin + A’BCin’ + AB’Cin’ + ABCin
A B Cin S Cout
= (AB’ + A’B)Cin’ + (AB + A’B’)Cin
0 0 0 0 0 = (A ⊕ B)Cin’ + (A ⊕ B)’Cin
0 0 1 1 0 = A ⊕ B ⊕ Cin
0 1 0 1 0
0 1 1 0 1
Cout = A’BCin + AB’Cin + ABCin’ + ABCin
1 0 0 1 0
= AB + (A ⊕ B)Cin
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Full Adder – Logical Diagram
S = A ⊕ B ⊕ Cin
Cout = AB + (A ⊕ B)Cin

A
B S = A ⊕ B ⊕ Cin

Cin
Cout = AB + (A ⊕ B)Cin

Half Adder Half Adder

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Half Subtractor
 Subtracts one bit from the other and produces the difference.
 Other output is to specify if 1 is borrowed.

Inputs Outputs
A
A B d b d=A⊕B
B
0 0 0 0
0 1 1 1
b = A’B
1 0 1 0
1 1 0 0
 Limitation:
 Half subtractor can be used only for LSB subtraction.

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Full Subtractor
 Full subtractor is a combinational circuit with 3 inputs (A, B, bi)
 Subtraction = A – B – bi

Inputs Outputs d = A’B’bi + A’Bbi’ + AB’bi’ + ABbi

A B bi d b = (AB’ + A’B)bi’ + (AB + A’B’)bi
0 0 0 0 0 = (A ⊕ B)bi’ + (A ⊕ B)’bi
0 0 1 1 1 = A ⊕ B ⊕ bi
0 1 0 1 1
0 1 1 0 1 b = A’B’bi + A’Bbi’ + A’Bbi + ABbi
1 0 0 1 0 = A’B(bi + bi’) + (AB + A’B’)bi
1 0 1 0 0 = A’B + (A ⊕ B)’bi
1 1 0 0 0
1 1 1 1 1

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Full Subtractor – Logical Diagram
d = A ⊕ B ⊕ bi
b = A’B + (A ⊕ B)’bi

A
B d = A ⊕ B ⊕ bi

bi
b = A’B + (A ⊕ B)’bi

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Binary Parallel Adder

1 1 1 0 0 1 1 0
B4 A4 B3 A3 B2 A2 B1 A1

0 0 0
0
C3 C2 C1
FA4 FA3 FA2 FA1 Cin

C4 S4 S3 S2 S1
1 0 1 1 1

Example: A = 1010, B = 1101

A4 A3 A2 A1 = 1010
B4 B3 B2 B1 = 1101

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Binary Parallel Subtractor
1 1 0 1 1 0 1 1
B4 A4 B3 A3 B2 A2 B1 A1

0 1 0 0
1 0 1
C3 C2 C1 Cin= 1
FA4 FA3 FA2 FA1

Cout S4 S3 S2 S1
1 0 0 1 0

Example: A = 1101, B = 1011

A4 A3 A2 A1 = 1101
B4 B3 B2 B1 = 1011
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Binary Adder-Subtractor

B4 A4 B3 A3 B2 A2 B1 A1

M Bi O/P
0 0 0
C3 C2 C1 Cin
FA4 FA3 FA2 FA1 0 1 1
1 0 1
1 1 0
C4 S4 S3 S2 S1

When M = 0, Circuit is an adder.

When M = 1, Circuit becomes a subtractor.

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Combinational circuit
The procedure involves the following steps:
 From the specifications of the circuit, determine the required number of inputs and outputs and
assign a symbol to each
 Derive the truth table that defines the required relationship between inputs and outputs.
 Obtain the simplified Boolean functions for each output as a function of the input variables
 Draw the logic diagram and verify the correctness of the design (manually or by simulation)

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• Section – 2
• Code converters
 4-bit Binary 4-bit Gray
Binary to Gray Code Converter
B4 B3 B2 B1 G4 G3 G2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
𝐺4 = ෍ 𝑚(8,9,10,11,12,13,14,15) 0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
𝐺3 = ෍ 𝑚(4,5,6,7,8,9,10,11) 0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
𝐺2 = ෍ 𝑚(2,3,4,5,10,11,12,13) 0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
𝐺1 = ෍ 𝑚(1,2,5,6,9,10,13,14) 1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Binary to Gray Code Converter
 K-Map for G4, G3, G2, G1 function and their minimization are as follows:

𝐺4 = ෍ 𝑚(8,9,10,11,12,13,14,15) 𝐺3 = ෍ 𝑚(4,5,6,7,8,9,10,11)
B4B3 B4B3
00 01 11 10 00 01 11 10
B2B1 B2B1
0 4 12 8 0 4 12 8
00 1 1 00 1 1
1 5 13 9 1 5 13 9
01 1 1 01 1 1
3 7 15 11 3 7 15 11
11 1 1 11 1 1
2 6 14 10 2 6 14 10
10 1 1 10 1 1
G4 = B4 G3 = B4’B3 + B4B3’ = B4 ⨁ B3
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Binary to Gray Code Converter

𝐺2 = ෍ 𝑚(2,3,4,5,10,11,12,13) 𝐺1 = ෍ 𝑚(1,2,5,6,9,10,13,14)
B4B3 B4B3
00 01 11 10 00 01 11 10
B2B1 B2B1
0 4 12 8 0 4 12 8
00 1 1 00
1 5 13 9 1 5 13 9
01 1 1 01 1 1 1 1
3 7 15 11 3 7 15 11
11 1 1 11

2 6 14 10 2 6 14 10
10 1 1 10 1 1 1 1

G2 = B3’B2 + B3B2’ = B3 ⨁ B2 G1 = B2’B1 + B2B1’ = B2 ⨁ B1

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Binary to Gray Code Converter
 Logic diagram for binary to Gray code converter is as follows:

G4 = B4 B4 G4
G3 = B4’B3 + B4B3’ = B4 ⨁ B3 G3
B3
G2 = B3’B2 + B3B2’ = B3 ⨁ B2
G2
G1 = B2’B1 + B2B1’ = B2 ⨁ B1 B2

G1
B1

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BCD to Excess-3 Code Converter
8421 BCD XS - 3
B4 B3 B2 B1 X4 X3 X2 X1
0 0 0 0 0 0 1 1
𝑋4 = ෍ 𝑚 5,6,7,8,9 + 𝑑(10,11,12,13,14,15)
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1 𝑋3 = ෍ 𝑚 1,2,3,4,9 + 𝑑(10,11,12,13,14,15)
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 𝑋2 = ෍ 𝑚 0,3,4,7,8 + 𝑑(10,11,12,13,14,15)
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1 𝑋1 = ෍ 𝑚 0,2,4,6,8 + 𝑑(10,11,12,13,14,15)
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
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BCD to Excess-3 Code Converter

𝑋4 = ෍ 𝑚 5,6,7,8,9 + 𝑑(10,11,12,13,14,15) 𝑋3 = ෍ 𝑚 1,2,3,4,9 + 𝑑(10,11,12,13,14,15)

 K-MapB4for
B3 X4, X3, X2, X1 function and their minimizationBare
4B3
as follows:
00 01 11 10 B2B1 00 01 11 10
B2B1 0 4
0 4 12 8 12 8
00 x 1 00 1 x
1 5 13 9 1 5 13 9
01 1 x 1 01 1 x 1
3 7 15 11 3 7 15 11
11 1 x x 11 1 x x
2 6 14 10 2 6 14 10
10 1 x x 10 1 x x
X4 = B4 + B3B2 + B3B1 X3 = B3B2’B1’ + B3’ B1 + B3’ B2
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BCD to Excess-3 Code Converter

𝑋2 = ෍ 𝑚 0,3,4,7,8 + 𝑑(10,11,12,13,14,15) 𝑋1 = ෍ 𝑚 0,2,4,6,8 + 𝑑(10,11,12,13,14,15)

B4B3 B4B3
00 01 11 10 B2B1 00 01 11 10
B 2B 1
0 4 12 8 0 4 12 8
00 1 1 x 1 00 1 1 x 1
1 5 13 9 1 5 13 9
01 x 01 x
3 7 15 11 3 7 15 11
11 1 1 x x 11 x x
2 6 14 10 2 6 14 10
10 x x 10 1 1 x x
X2 = B2’B1’ + B2B1 X1 = B1’
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BCD to Excess-3 Code Converter
 Logic diagram for a BCD to Excess-3 is as follows
B4
B3
B2 X4
B3
B1
B3
B2’
B1’
B3’
B1 X3
B3’
B2
B2’
B1’
X2
B2
B1
B1’ X1
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Comparators
 A comparator is a logic circuit used to compare the magnitudes of two
binary numbers.
 Comparator circuit provides 3 outputs
1. A=B
2. A>B
3. A<B
 X-NOR gate is a basic comparator (the output is 1 if and only if the input
bits coincide).
 2 binary numbers are equal if and only if all their corresponding bits
coincide.
 E.g. A3A2A1A0 and B3B2B1B0 are equal if and only if A3=B3, A2=B2, A1=B1 and
A0=B0

Equality = (A3⨀B3) (A2⨀B2) (A1⨀B1) (A0⨀B0)

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1-bit Magnitude Comparator
 Let the 1-bit numbers be A = A0 and B = B0
A < B(L)
 If A0 = 1 and B0 = 0 then A > B
A > B : G = A0B0’
A0
 If A0 = 0 and B0 = 1 then A < B A = B(E)
B0
A < B : L = A0’B0
 If A0 = 1 and B0 = 1 (coincides) then A = B
A = B : E = A 0 ⨀ B0 A > B(G)

A0 B0 L E G
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
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2-bit Magnitude Comparator
 Let the two 2-bit numbers be A = A1A0 and B = B1B0
1. If A1 = 1 and B1 = 0, then A > B or
2. If A1 and B1 coincide and A0 = 1 and B0 = 0, then A > B.
A > B : G = A1B1’ + (A1 ⊙ B1) A0B0’
1. If A1 = 0 and B1 = 1, then A < B or
2. If A1 and B1 coincide and A0 = 0 and B0 = 1, then A < B.
A < B : L = A1’B1 + (A1 ⊙ B1) A0’B0
1. If A1 and B1 coincide and if A0 and B0 coincide then A = B.
A = B : E = (A1 ⊙ B1)(A0 ⊙ B0)

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2-bit Magnitude Comparator
A1
B1’
A0 A > B(G)
B0’

A1
B1
A = B(E)
A0
B0

B0 A0’
A < B(L)
A1’
B1

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3-bit parity generator using even parity bit

Inputs Outputs
AB
parity bit 00 01 11 10
A B C (f) C
0 0 0 0 0 1 1 A
0 0 1 1 B f
C
0 1 0 1 1 1 1
0 1 1 0
1 0 0 1 𝑓 = 𝐴′ 𝐵 ′ 𝐶 + 𝐴′ 𝐵𝐶′+ 𝐴𝐵𝐶 + 𝐴𝐵′𝐶′
1 0 1 0 𝑓 = 𝐴′ 𝐵 ′ 𝐶 + 𝐵𝐶 ′ + 𝐴(𝐵𝐶 + 𝐵 ′ 𝐶 ′ )
1 1 0 0 𝑓 = 𝐴′ 𝐵 ⨁ 𝐶 + 𝐴 𝐵 ⨁ 𝐶 ′
1 1 1 1 𝑓 =𝐴⊕𝐵⨁𝐶

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Parity Generator
 Binary data, when transmitted and processed is susceptible to noise that can alter its 1s to 0s
and 0s to 1s.
 To detect such errors, an additional bit called parity bit is added to the data bits and the word
containing the data bits and the parity bit is transmitted.
 At the receiving end the number of 1s in the word received are counted and the error, if any, is
detected.

Even Parity Odd Parity

0 0 1 1 0 0 1 0

Data Parity bit Data Parity bit

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Section - 3
Multiplexer
 A multiplexer(MUX) is a device that allows digital information from several sources to be
routed onto a single line for transmission over that line to a common destination.
 Consider an integer ‘m’, which is constrained by the following relation:
m = 2n, where m and n are both integers.
 A m-to-1 Multiplexer has
 m Inputs: I0, I1, I2, ................ I(m-1)
 One Output: Y
 n Control inputs: S0, S1, S2, ...... S(n-1)
 One (or more) Enable input(s)
Such that Y may be equal to one of the inputs, depending upon the control inputs.

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4-to-1 Multiplexer
2n inputs

I0 Select Inputs Output

I1 I0 S1 S0 Y
4x1
Y 0 0 I0
I2 MUX 1 output
0 1 I1
I3
1 0 I2
1 1 I3
Enable (G)
S1 S0
0 0 Y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3
n control inputs

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4 x 1 MUX Actual Circuit
I3

I2

Y
I1

I0

S1 S0 Enable (G)

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Logic function /Boolean function generator using Multiplexer
CASE 1: No. of input variables and no.of selection inputs are same
How to solve?
 The first step is to select the multiplexer. If the given expression has n
variables, then determine the multiplexer using the formula 2n : 1.
 Connect the inputs, that correspond to the given minterms to logic 1.
 Connect all the other inputs to the ground(logic 0).
 Connect the input variables(A, B, C) as the selection lines.

36
Logic function /Boolean function generator using Multiplexer
 Implement the boolean expression F(A, B, C) = ∑ m(2, 3, 6, 7) using a
multiplexer.

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Logic function /Boolean function generator using Multiplexer
 Implement the following function using 8 to 1 MUX
F(x,y,z) = σ𝑚(0,2,3,5)

S2 S1 S0
F z S0
x y z
y S1
0 0 0 1 x S2
0 0 1 0
1 D0
0 1 0 1 0 D1 8x1
0 1 1 1 1 D2 MUX Output = F
1 D3
1 0 0 0 0 D4
1 0 1 1 1 D5
1 1 0 0 0 D6
0 D7
1 1 1 0

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Logic function /Boolean function generator using Multiplexer
How to solve?
CASE 2: If the boolean expression has n+1 variables, we take only n variables as the
selection line of the multiplexer.
• From the given set of n+1 input variables, the n least significant variables are used
as selection line inputs.
• The 2n inputs for 2n : 1 multiplexer are derived by using an implementation table.
• The implementation table has all the inputs(D0, D1, D2, D3,…) for the multiplexer,
under which, all the minterms are listed in two rows.
• The first row consists of all minters where MSB( A) is complemented, and the
second row has the remaining minterms where MSB(A)is in uncomplemented
form.
• The minterms in the given boolean expression alone are circled.

39
Logic function /Boolean function generator using Multiplexer
 Implement the boolean expression F(A, B, C) = ∑ m(0, 2, 5, 6) using
4 : 1 multiplexer.

40
Logic function /Boolean function generator using Multiplexer
Implement F(A, B, C, D) = ∑ m(0, 1, 5, 6, 8, 10, 12, 15) using 8 : 1
multiplexer.
Solution:
 In the given boolean expression, there are 4 variables. We should use 24 : 1 = 16
: 1 multiplexer. But as per the question, it is to be implemented with 8 : 1 mux.
 For 8 : 1 multiplexer, there should be 3 selection lines. So from the given 4
variables, the 3 least significant variables(B, C, D) are used as selection line
inputs.

41
Logic function /Boolean function generator using Multiplexer
Implement F(A, B, C, D) = ∑ m(0, 1, 5, 6, 8, 10, 12, 15) using 8 : 1
multiplexer.
 The 8 inputs are derived using the implementation table shown below

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Logic function /Boolean function generator using Multiplexer
Implement F(A, B, C, D) = ∑ m(0, 1, 5, 6, 8, 10, 12, 15) using 8 : 1
multiplexer.
From the derived input, 8 : 1 multiplexer can be drawn as below

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Logic function generator using Multiplexer (Method)
 Multiplexer with n-data select inputs can implement any function of n + 1 variables.
 The first n variables of the function as the select inputs and to use the least significant input
variable and its complement to drive some of the data inputs.

 If the single variable is denoted by D, each data output of the multiplexer will be D, D’, 1, or 0.
 Suppose, we wish to implement a 4-variable logic function using a multiplexer with three data
select inputs.

 Let the input variables be A, B, C, and D; D is the LSB.

 A truth table for the function F(A, B, C, D) is constructed with ABC has the same value twice
once with D = 0 and again with D = 1.

44
Logic function generator using Multiplexer (Method)
 The following rules are used to determine the connections that should be
made to the data inputs of the multiplexer.
1. If F = 0 both times when the same combination of ABC occurs, connect logic 0 to
the data input selected by that combination.
2. If F = 1 both times when the same combination of ABC occurs, connect logic 1 to
the data input selected by that combination.
3. If F is different for the two occurrences of a combination of ABC, and if F = D in
each case, connect D to the data input selected by that combination.
4. If F is different for the two occurrences of a combination of ABC, and if F = D’ in
each case, connect D’ to the data input selected by that combination.

45
Logic function generator using Multiplexer (Method)
 Implement the following function using 8 to 1 MUX
F = σ𝑚( 0,1,2,3,4,10,11,14,15)

46
Special Cases
 Design of a 8X1 Mux using 2X1 Mux.
 Design of a 8X1 Mux using 4X1 Mux.
 Design of a DE-MUX

47
Todays class
 Combinational circuit Design processor
 Example: BCD to EX-3 code converter
 Example: Design of a 1-bit Full-Adder using 4X1 MUX
 DE-MUX –Introduction
 Design of a 1X2 DE-MUX
 Design of a 1X4 DE-MUX
 Design of a 1-bit Full-Subtractor 1x8 DE-MUX

48
Example: Design of a 1-bit Full-Adder using 4X1 MUX

49
Design of a 1-bit Full-Adder using 4X1 MUX

50
51
Demultiplexer
 A demultiplexer(DEMUX) is a device that allows digital information from
one source to be routed onto a multiple lines for transmission over
different destinations.
 Consider an integer ‘m’, which is constrained by the following relation:
m = 2n, where m and n are both integers.
 A 1-to-m Demultiplexer has
 One Input: D
 m Outputs: O0, O1, O2, ................ O(m-1)
 n Control inputs: S0, S1, S2, ...... S(n-1)
 One (or more) Enable input(s)
Such that D may be transfer to one of the outputs, depending upon the
control inputs.

52
53
Demultiplexer

54
Design of a 1X2 DE-MUX

55
Design of a 1X2 DE-MUX

56
Design of a 1X4 DE-MUX

57
58
Design of a 1-Bit Full subtractor using 1X8 De-MUX
 Assignment 3

59
Application of MUX

60
Design of a Higher order Mux using Lower order
 8x1 Mux using 2x1 Mux
 8x1 Mux using 4x1 Mux

61
Section – 4
Decoder
 A decoder is a logic circuit that accepts a set of inputs which represents a binary number and activates the only
output that corresponds to the input number.
 In other words, a decoder circuit looks at its inputs, determines which binary number is present there, and
activates the specific output which corresponds to that number; all other outputs remain inactive.
 Decoder detects a particular code.
 Converts code into signal.(n-bit code into 2^n signal lines)
 In its general form, a decoder has N input lines to handle N bits and M output lines such that only one output line is
activated for each one of the possible combinations of inputs.

I0 O0
I1 O1
I2 O2
. .
N inputs Decoder .
M outputs M = 2N
.
. .
IN-2 OM-2
IN-1 OM-1

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(2X4 decoder)TWO to FOUR line decoder with enable input

64
Assignment
 3X8 Decoder

65
3 to 8 decoder using 2 to 4 decoders.
 In this section, let us implement 3 to 8(2^n=m2) decoder using 2
to 4 (2^n=m1)decoders.
 Required number of lower order decoders=m2/m1
 Required number of lower order decoders=8/4=2
 m1 is the number of output lines of lower order decoder
 m2 is the number of output lines of higher order decoder

66
3-Line to 8-Line Decoder
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7
A B C
A’B’C’ A’B’C A’BC’ A’BC AB’C’ AB’C ABC’ ABC
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

• 3 to 8 line decoder can be implemented using AND gates to achieve active-HIGH output.
• For active-LOW outputs, NAND gates are used.
• Binary to Octal converter

67
3-Line to 8-Line Decoder

68
Implementation of a 4X16 decoder with 3X8 Decoder
 Implementation of a 4X16 decoder with 3X8 Decoder
 Assignment-3

69
4 to 16 decoder using 3 to 8 decoders.

• Decoders with enable inputs can be connected together to form a larger

decoder
• circuit.
• Figure shows two 3-to-8-line decoders with enable inputs connected to form
• a 4-to-16-line decoder.
• When w = 0, the top decoder is enabled and the other is disabled.
• The bottom decoder outputs are all 0’s, and the top eight outputs generate
minterms 0000 to 0111.
• When w 1, the enable conditions are reversed: The bottom decoder
• outputs generate minterms 1000 to 1111, while the outputs of the top decoder
are all0’s.
• This example demonstrates the usefulness of enable inputs in decoders and
othercombinational logic components.

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Implementation of a full adder with a Decoder
 A decoder provides the 2^n minterms of n input variables.
 Each asserted output of the decoder is associated with a unique pattern of
input bits. Since any Boolean function can be expressed in sum-of-minterms
form.
 A decoder that generates the minterms of the function, together with an
external OR gate that forms their logical sum, provides a hardware
implementation of the function.

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Implementation of a full adder with a Decoder

Inputs Outputs
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Encoder
 Device to convert familiar numbers or symbols into coded format.
 It has a number of input lines, only one of which is activated at a given time, and produces an
N-bit output code depending on which input is activated.
 Figure shows the block diagram of an encoder with M inputs and N outputs.

I0 O0
I1 O1
I2 O2
. .
M=2^N inputs
. Encoder .
N outputs M = 2N
. .
IM-2 ON-2
IM-1 ON-1

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8x3 (Octal to Binary) Encoder

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75
Priority Encoder
 A priority encoder is a logic circuit that responds to just one input in accordance with some
priority system, among all those that may be simultaneously HIGH.
 The most common priority system is based on the relative magnitudes of the inputs; whichever
decimal input is the largest, is the one that is encoded.
 For example, if both decimal 3 and decimal 4 are activated simultaneously, then a priority
encoder would encode decimal 4.
Inputs Outputs 𝐴 = ෍ (1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15)
𝑚
D0 D1 D2 D3 A B V
0 0 0 0 x x 0 𝐵 = ෍ (1, 3, 4, 5, 7, 9, 11, 12, 13, 15)
𝑚
1 0 0 0 0 0 1
x 1 0 0 0 1 1 𝑉 = ෍ (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
𝑚

x x 1 0 1 0 1
x x x 1 1 1 1
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Priority Encoder
𝐴 = ෍ (1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15) 𝐵 = ෍ (1, 3, 4, 5, 7, 9, 11, 12, 13, 15)
𝑚 𝑚

D0D1 D0D1
00 01 11 10 00 01 11 10
D2D3 D2D3
0 4 12 8 0 4 12 8
00 x 00 x 1 1
1 5 13 9 1 5 13 9
01 1 1 1 1 01 1 1 1 1
3 7 15 11 3 7 15 11
11 1 1 1 1 11 1 1 1 1
2 6 14 10 2 6 14 10
10 1 1 1 1 10

A = D3 + D2 B = D3 + D2’ D1

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Priority Encoder
𝑉 = ෍ (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
𝑚

D0D1 D3 B = D3 + D2’ D1
00 01 11 10
D2D3
0 4 12 8 D2
00 0 1 1 1 D1

1 5 13 9
01 1 1 1 1 A = D3 + D2

3 7 15 11
11 1 1 1 1 V = D3 + D2 + D1 + D0
D0
2 6 14 10
10 1 1 1 1

V = D3 + D2 + D1 + D0

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