DSP Lab Manual r2021
DSP Lab Manual r2021
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II YEAR/ IV SEMESTER
REGULATION 2021
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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
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II YEAR/ IV SEMESTER
REGULATION 2021
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VISION:
MISSION:
VISION:
To impart latest knowledge and skills so as to kindle innovation and creativity among
students.
MISSION:
To develop and sustain a culture of research while promoting values, ethics and
professionalism
To Develop competent technocrats who strives continuously in pursuit of professional
excellence in the field of Electronics and Communication Engineering
To Offer well-balanced curriculum to acquire professional competencies
To Develop the state-of-the-art infrastructure and research for effective teaching
learning process
To Strengthen the soft skills especially for rural students through co-curricular and
extracurricular activities
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
research.
To develop attitude in lifelong learning, applying and adapting new ideas and
Problem analysis: Identify, formulate, review research literature, and analyze Complex
PO2 engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
Modern tool usage: Create, select, and apply appropriate techniques, resources, and
PO5 modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
The engineer and society: Apply reasoning informed by the contextual knowledge to
PO6 assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
Ethics: Apply ethical principles and commit to professional ethics and responsibilities
PO8 and norms of the engineering practice.
PO12 Life-long learning: Recognize the need for have the preparation and ability to engage in
independentandlife-longlearninginthebroadestcontextoftechnological change
PROGRAM SPECIFIC OUTCOMES (PSOs):
All the students must follow the instructions strictly as appended below:
All the students should enter the lab class with proper uniform.
Bring the observation note book and lab manual during all the lab class.
Before entering the next lab classes ensure that the experiment is
neatly written in the respective record note book and the same should
be checked / corrected by the faculty in charge.
Get completed signature in the index page of the record note book
from the faculty in charge when all the experiments are completed.
3 0
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COURSE OBJECTIVES:
● To learn discrete fourier transform, properties of DFT and its application to linear filtering
● To understand the characteristics of digital filters, design digital IIR and FIR filters and
apply
these filters to filter undesirable signals in various frequency bands
● To understand the effects of finite precision representation on digital filters
● To understand the fundamental concepts of multi rate signal processing and its
applications
● To introduce the concepts of adaptive filters and its application to communication
Engineering
10. Design and demonstration of FIR Filter for Low pass, High pass, Band pass and Band
stop filtering
11. Design and demonstration of Butter worth and Chebyshev IIR Filters for Low pass, High
pass, Band pass and Band stop filtering
TOTAL: 30 PERIODS
COURSE OUTCOMES:
At the end of the course students will be able to:
CO1: Apply DFT for the analysis of digital signals and systems
CO2: Design IIR and FIR filters
CO3: Characterize the effects of finite precision representation on digital filters
CO4: Design multirate filters
CO5: Apply adaptive filters appropriately in communication systems
INDEX
MARKS
PAGE
EX. FACULTY
NO
Ex. No : 1
AIM:
SOFTWARE REQUIRED:
ALGORITHM:
EXPONENTIAL RESPONSE
Start the program
Enter the value of N
Generates the corresponding values of n to get the exponential response
Plot the output.
UNITRAMPRESPONSE:
Start the program
Enter the value of N
Generates the corresponding values of n to get the unit ramp response
Plot the output.
SINEWAVE:
Start the program
Enter the value of N
Generates the corresponding values of n to get the sine wave using sin function
Plot the output.
COSINE WAVE:
Start the program
Enter the value of N
Generates the corresponding values of n to get the cosine wave using cos function
Plot the output.
FLOWCHART:
GENERATION OF ELEMENTARY DISCRETE - TIME SEQUENCES
PROGRAM:
clc;
clear all;
close all;
%EXPONENTIAL WAVE%
N=8;
n=0:1:N-1;
x=exp(n);
subplot(3,3,4);
stem(n,x );
xlabel('n');
ylabel('x(n)');
title('EXPONENTIAL WAVEFORM');
%SINE WAVE%
N=8;
n=0:1:N-1;
x=sin(.2*pi*n);
subplot(3,3,5);
stem(n,x);
xlabel('n');
ylabel('x(n)');
title('SINE WAVE');
%COSINE WAVE%
N=8;
n=0:1:N-1;
x=cos(.2*pi*n);
subplot(3,3,6);
stem(n,x);
xlabel('n');
ylabel('x(n)');
title('COSINE WAVE');
OUTPUT:
Sample Viva questions:
1. What is a signal?
2. How discrete signal varies from digital signal?
3. Why digital signal is preferred for effective communication?
4. Is digital signals are easy to process?
RESULT:
Thus the generation of various discrete time sequences has been performed using MATLAB progr
Ex. No : 2.A
LINEAR CONVOLUTION USING CONVOLUTION FUNCTION
Date :
AIM:
SOFTWARE REQUIRED:
ALGORITHM:
PROGRAM:
clc;
clear all;
close all;
x=input('Enter the first input sequence x(n)');
h=input('Enter the second input sequence h(n)');
n1=length(x);
n2=length(h);
n=n1+n2-1;
y=conv(x,h);
disp('Linear Convolution Output is:');
disp(y);
t1=0:n1-1;
subplot(2,2,1);
stem(t1,x);
xlabel('n');
ylabel('Amplitude');
title('First input sequence:');
t2=0:n2-1;
subplot(2,2,2);
stem(t2,h);
xlabel('n');
ylabel('Amplitude');
title('Second input sequence:');
t=0:1:n-1;
subplot(2,2,3);
stem(t,y);
xlabel('n');
ylabel('Amplitude');
title('Output sequence:');
OUTPUT:
RESULT:
Thus the linear convolution of two sequences using convolution function was performed and
executed successfully.
Ex. No : 2.B
AIM:
SOFTWARE REQUIRED:
ALGORITHM:
FLOWCHART :
PROGRAM:
clc;
clear all;
close all;
x=input('Enter the first input sequence x(n):');
h=input('Enter the second input sequence h(n):');
n1=length(x);
n2=length(h);
n=n1+n2-1;
X=fft(x,n);
H=fft(h,n);
Y=X.*H;
y=ifft(Y);
disp('linear convolution output is:');
disp(y);
t1=0:n1-1;
subplot(1,3,1);
stem(t1,x);
xlabel('n');
ylabel('Amplitude');
title('first input sequence');
t2=0:n2-1;
subplot(1,3,2);
stem(t2,h);
xlabel('n');
ylabel('Amplitude');
title('second input sequence');
t=0:1:n-1;
subplot(1,3,3);
stem(t,y);
xlabel('n');
ylabel('Amplitude');
title('output sequence');
OUTPUT:
1. What is convolution?
2. Is convolution mandatory in processing discrete signals?
3. Is linear convolution better than the circular convolution?
4. What the methods used in linear and circular convolution?
RESULT:
Thus the linear convolution of two sequences using FFT was performed and executed using
MATLAB.
Ex. No : 2. C
AIM:
SOFTWARE REQUIRED:
ALGORITHM:
Start the program
Enter the two input sequences x(n) and h(n)
Find the length of the input and output sequences
If the length of sequences are not same , perform zero padding to the sequence with
less length
Find FFT of x(n) & h(n) to get X(K) & H(K)
Multiply X(K) & H(K) to get Y(K)
Find IFFT of Y(K) to get convolution output y(n).
Display the output
Plot the input & output sequences
Stop the program
FLOWCHART:
PROGRAM
clc;
clear all;
close all;
x1=input('enter the 1st input sequence');
x2=input('enter the 2nd input sequence');
n1=length(x1);
n2=length(x2);
if(n1<n2)
x1=[zeros(1,n2-n1)];
elseif(n2<n1)
x2=[zeros(1,n1-n2)];
else
x1=x1;
x2=x2;
end;
n1=length(x1);
n2=length(x2);
A=fft(x1,n1);
B=fft(x2,n2);
Y=A.*B;
y=ifft(Y);
n=length(y);
disp('circular convolution output is:');
disp(y);
t1=0:n1-1;
subplot(1,3,1);
stem(t1,x1);
xlabel('n-->');
ylabel('amplitude-->');
title('first input sequence');
t2=0:n2-1;
subplot(1,3,2);
stem(t2,x2);
xlabel('n-->');
ylabel('amplitude-->');
title('second input sequence');
t=0:1:n-1;
subplot(1,3,3);
stem(t,y);
xlabel('n-->');
ylabel('amplitude-->');
title('output sequence');
OUTPUT
1. What is convolution?
2. Is convolution mandatory in processing discrete signals?
3. Is linear convolution better than the circular convolution?
4. What the methods used in linear and circular convolution?
RESULT:
Thus the circular convolution of two sequences using FFT was performed and executed using
MATLAB.
Ex. No : 3
AIM:
SOFTWARE REQUIRED:
ALGORITHM:
AUTO CORRELATION:
Start the program
Enter the value of sequence
Generate the corresponding values of y to get the convolution using conv function
Plot the output
CROSS CORRELATION:
Start the program
Enter the value of sequence
Generate the corresponding values of y to get the convolution using conv function
Plot the output
PROGRAM:
%AUTOCORRELATION%
clc;
clear all;
close all;
x=input('Enter the sequence');
y=xcorr(x,x);
figure;
subplot(2,1,1);
stem(x);
ylabel('amplitude');
xlabel('n');
subplot(2,1,2);
stem(fliplr(y));
y
xlabel('n');
ylabel('amplitude');
disp('the resultant signal is ');
fliplr(y);
%CROSS CORRELATION%
clc;
close all;
clear all;
x=input('Enter the first sequence');
h=input('Enter the second sequence');
y=xcorr(x,h);
figure;
subplot(3,1,1);
stem(x);
xlabel('n');
ylabel('amplitude');
subplot(3,1,2);
stem(h);
ylabel('amplitude');
xlabel('n');
subplot(3,1,3);
stem(fliplr(y));
y
ylabel('amplitude');
xlabel('n');
title('The resultant signal is ');
fliplr(y)
OUTPUT:
AUTO CORRELATION:
Enter the sequence [2 3 4 5]
The resultant signal is
y = 10.0000 23.0000 38.0000 54.0000 38.0000 23.0000 10.0000
CROSS CORRELATION:
enter the first sequence [1 2 3 4]
enter the second sequence [2 4 6 8]
y =8.0000 22.0000 40.0000 60.0000 40.0000 22.0000 8.0000
RESULT:
Thus the auto-correlation and cross-correlation between the sequences are performed and executed
using MATLAB
Ex. No : 4
AIM:
To perform the frequency analysis of DFT for the given sequence using FFT.
SOFTWARE REQUIRED:
ALGORITHM:
FLOW CHART:
PROGRAM:
clc;
clear all;
x=input ('Enter the sequence :');
n=length (x);
y=fft(x,n);
di sp('output sequence is:');
disp(y);
m=abs(y);
disp('magnitude function is:');
disp(m);
p=angle(y);
disp('phase function is:’);
disp(p);
subplot(1,3,1);
t1=0 : n-1;
stem(t1,x);
xlabel('n-->');
ylabel('amplitude -->');
title('input sequence');
subplot(1,3,2);
t2=0 : n-1;
stem (t2,m);
xlabel('n-->');
ylabel('amplitude -->');
title('magnitude plot');
subplot(1,3,3);
t3=0 : n-1;
stem(t3,p);
xlabel('n-->');
ylabel('phase -->');
title('phase plot');
OUTPUT:
RESULT:
Thus the frequency analysis of DFT computation using FFT was performed and executed
using MATLAB.
Ex. No : 5. A
AIM:
To design a FIR Low pass filter using rectangular window and to plot the frequency response.
SOFTWARE REQUIRED:
FLOWCHART:
PROGRAM:
clc;
clear all;
close all;
N=input('enter the order of filter');
wc=(pi/2);
a=(N-1)/2;
for n=1:N
if((n-1)==a)
hd(n)=(wc/pi);
else
hd(n)=(sin(wc*(n-1-a)))/(pi*(n-1-a));
end;
w(n)=1;
end;
h=w.*hd;
a=0:0.01:pi;
b=freqz(h,1,a);
mag=20*log(abs(b));
plot(a/pi,mag);
grid;
xlabel('normalized frequency\omega^pi');
ylabel('magnitude in db');
title('low pass filter');
OUTPUT:
RESULT:
Thus the FIR low pass filter using rectangular window was designed and executed using MATLAB.
Ex.no: 5. B
To design a FIR high pass filter using hamming window and to plot the frequency response.
SOFTWARE REQUIRED:
ALGORITHM:
FLOW CHART:
PROGRAM:
clc;
clear all;
close all;
N=input('enter the order of filter');
wc=(pi/2);
a=(N-1)/2;
for n=1:N
if((n-1)==a)
hd(n)=(pi-wc)/pi;
else
hd(n)=sin(pi*(n-1-a))-sin(wc*(n-1-a))/(pi*(n-1-a));
end;
w(n)=0.54-(0.46*cos(2*pi*(n-1)/(N-1)));
end;
h=w.*hd;
a=0:0.01:pi;
b=freqz(h,1,a);
mag=20*log(abs(b));
plot(a/pi,mag);
grid;
xlabel('normalized frequency\omega^pi');
ylabel('magnitude in db');
title('high pass filter');
OUTPUT:
RESULT:
Thus the FIR high Pass Filter using hamming window was designed and executed using MATLAB.
Ex. no: 5. C
AIM:
To design a FIR band pass filter using hanning window and to plot the frequency response.
SOFTWARE REQUIRED:
ALGORITHM:
FLOWCHART:
PROGRAM:
clc;
clear all;
close all;
N=input('enter the order of filter');
wc1=(pi/4);
wc2=(3*pi)/4;
a=(N-1)/2;
for n=1:N
if((n-1)==a)
hd(n)=(wc2-wc1)/pi;
else
hd(n)=(sin(wc2*(n-1-a))-sin(wc1*(n-1-a)))/(pi*(n-1-a));
end;
w(n)=0.5+(0.5*cos(2*pi*(n-1-a)/(N-1)));
end;
h=w.*hd;
a=0:0.01:pi;
b=freqz(h,1,a);
mag=20*log(abs(b));
plot(a/pi,mag);
grid;
xlabel('normalized frequency\omega^pi');
ylabel('magnitude in db');
title('bandpass filter');
OUTPUT:
RESULT:
Thus the FIR BPF using Hanning window was designed and executed using MATLAB.
Ex. no: 5. D
AIM:
To design a FIR band stop filter using hanning window and to plot the frequency response.
SOFTWARE REQUIRED:
ALGORITHM:
Start the program
Get the cut-off frequency& order of the filter
For the given specifications, find the desired impulse response hd(n)
Find the corresponding window coefficients w(n) for the given order of the filter
Find the filter coefficients & transfer function for the given specifications
Obtain the magnitude response & phase response
Plot the magnitude response and phase response
Stop the program
FLOW CHART:
PROGRAM:
clc;
clear all;
close all;
N=input('enter the order of filter');
wc1=(pi/4);
wc2=(3*pi)/4;
a=(N-1)/2;
for n=1:N
if((n-1)==a)
hd(n)=1-(wc1+pi-wc2)/pi;
else
hd(n)=(sin(wc1*(n-1-a))-sin(wc2*(n-1-a)))/(pi*(n-1-a));
end;
w(n)=0.5+(0.5*cos(2*pi*(n-1-a)/(N-1)));
end;
h=w.*hd;
a=0:0.01:pi;
b=freqz(h,1,a);
mag=20*log(abs(b));
plot(a/pi,mag);
grid;
xlabel('normalized frequency\omega^pi');
ylabel('magnitude in db');
title('bandstop filter');
OUTPUT:
RESULT:
Thus the FIR-Band Stop Filter using Hanning window was designed and executed using
MATLAB.
Ex. no: 6. A
AIM:
To design an IIR butterworth low pass filter and to plot magnitude & phase response.
SOFTWARE REQUIRED:
ALGORITHM:
FLOWCHART:
PROGRAM:
clc;
clear all;
close all;
ap=0.5;
as=50;
fp=1000;
fs=2000;
f=5000;
wp=2*fp/f;
ws=2*fs/f;
wn=[wp,ws];
%TO FIND THE CUT OFF FREQ & ORDER OF FILTER
[n,wn]=buttord(wp,ws,ap,as);
[b,a]=butter(n,wn,'low');
w=0:0.01:pi;
h=freqz(b,a,w);
p=angle(h);
mag=20*log10(abs(h));
subplot(2,1,1);
plot(w/pi,mag);
grid;
xlabel('normalized frequency');
ylabel('magnitude in db-->');
title('magnitude response(low pass filter)');
subplot(2,1,2);
plot(w/pi,p);
grid;
xlabel('normalized frequency-->');
ylabel('phase in radians-->');
title('phase response(low pass filter)');
OUTPUT:
Sample Viva questions:
RESULT:
Thus the IIR butterworth low pass filter was designed and executed using MATLAB.
Ex. no: 6. B
AIM:
To design an IIR Butterworth high pass filter and to plot magnitude & phase response.
SOFTWARE REQUIRED:
ALGORITHM:
Start the program
Get the pass band attenuation(ap) & stop band attenuation (as)
Get the pass band frequency (fp) & stop band frequency (fs) & sampling frequency
Find the order of the Butterworth highpass filter
Find the filter coefficients & transfer function for the given specifications
Obtain the magnitude response & phase response
Plot the magnitude response and phase response
Stop the program
FLOWCHART:
PROGRAM:
clc;
clear all;
close all;
ap=0.5;
as=50;
fp=1000;
fs=2000;
f=5000;
wp=2*fp/f;
ws=2*fs/f;
wn=[wp,ws];
OUTPUT:
Sample Viva questions:
RESULT:
Thus the IIR Butterworth High Pass Filter was designed and executed using MATLAB.
Ex. no: 6. C
AIM:
To design an IIR Butterworth Band pass filter and to plot magnitude & phase response.
SOFTWARE REQUIRED:
ALGORITHM:
FLOWCHART:
PROGRAM:
clc;
clear all;
close all;
ap=0.5;
as=50;
fp=1000;
fs=2000;
f=5000;
wp=2*fp/f;
ws=2*fs/f;
wn=[wp,ws];
[n]=buttord(wp,ws,ap,as);
[b,a]=butter(n,wn,'bandpass');
w=0:0.01:pi;
h=freqz(b,a,w);
p=angle(h);
mag=20*log10(abs(h));
subplot(2,1,1);
plot(w/pi,mag);
grid;
xlabel('normalized frequency');
ylabel('magnitude in db-->');
title('magnitude response(band pass filter)');
subplot(2,1,2);
plot(w/pi,p);
grid;
xlabel('normalized frequency-->');
ylabel('phase in radians-->');
title('phase response(band pass filter)');
OUTPUT:
Sample Viva questions:
RESULT:
Thus the IIR Butterworth band pass filter was designed and executed using MATLAB.
Ex. no: 6. D
AIM:
To design an IIR butterworth band stop filter and to plot magnitude & phase response.
SOFTWARE REQUIRED:
ALGORITHM:
FLOWCHART:
PROGRAM:
clc;
clear all;
close all;
ap=0.5;
as=50;
fp=1000;
fs=2000;
f=5000;
wp=2*fp/f;
ws=2*fs/f;
wn=[wp,ws];
[n]=buttord(wp,ws,ap,as);
[b,a]=butter(n,wn,'stop');
w=0:0.01:pi;
h=freqz(b,a,w);
p=angle(h);
mag=20*log10(abs(h));
subplot(2,1,1);
plot(w/pi,mag);
grid;
xlabel('normalized frequency');
ylabel('magnitude in db-->');
title('magnitude response(band stop filter)');
subplot(2,1,2);
plot(w/pi,p);
grid;
xlabel('normalized frequency-->');
ylabel('phase in radians-->');
title('phase response(bandstop filter)');
OUTPUT:
Sample Viva questions:
RESULT:
Thus the IIR Butterworth Band Stop Filter was designed and executed using MATLAB.
Ex. no: 6. E
To design and execute Chebyshev Type-I analog Low pass filter using MATLAB.
SOFTWARE REQUIRED:
ALGORITHM
PROGRAM:
clc;
close all;clear all;
format long
rp=input('enter the passband ripple...');
rs=input('enter the stopband ripple...');
wp=input('enter the passband freq...');
ws=input('enter the stopband freq...');
fs=input('enter the sampling freq...');
w1=2*wp/fs;w2=2*ws/fs;
[n,wn]=cheb1ord(w1,w2,rp,rs,'s');
[b,a]=cheby1(n,rp,wn,'s');
W=0:.01:pi;
[h,om]=freqs(b,a,W);
M=20*log10(abs(h));
An=angle(h);
subplot(2,1,1);
plot(om/pi,M);
ylabel('Gain in dB --.');
xlabel('(a) Normalised frequency --.');
subplot(2,1,2);
plot(om/pi,An);
xlabel('b) Normalised frequency --.');
ylabel('Phase in radians --.');
OUTPUT:
RESULT:
Thus the Chebyshev Type-I analog Low pass filter was designed and executed using MATLAB.
Ex. no: 6. F
AIM:
To design and execute Chebyshev Type-II analog High pass filter using MATLAB.
SOFTWARE REQUIRED:
ALGORITHM
PROGRAM:
clc;
close all;clear all;
format long
rp=input('enter the passband ripple...');
rs=input('enter the stopband ripple...');
wp=input('enter the passband freq...');
ws=input('enter the stopband freq...');
fs=input('enter the sampling freq...');
w1=2*wp/fs;
w2=2*ws/fs;
[n,wn]=cheb2ord(w1,w2,rp,rs,'s');
[b,a]=cheby2(n,rs,wn,'high','s');
w=0:.01:pi;
[h,om]=freqs(b,a,w);
m=20*log10(abs(h));
an=angle(h);
subplot(2,1,1);
plot(om/pi,m);
ylabel('Gain in dB --.');
xlabel('(a) Normalised frequency --.');
subplot(2,1,2);
plot(om/pi,an);
xlabel('(b) Normalised frequency --.');
ylabel('Phase in radians --.');
OUTPUT:
RESULT:
Thus the Chebyshev Type-II analog HIGH pass filter was designed and executed using MATLAB
Ex. no: 7
STUDY OF ARCHITECTURE OF DIGITAL SIGNAL PROCESSOR
Date:
AIM:
ARCHITECTURE:
Texas Instruments TMS320 is a blanket name for a series of digital signal processors (DSPs) from
Texas Instruments. It was introduced on April 8, 1983 through the TMS32010 processor, which was
then the fastest DSP on the market.
The processor is available in many different variants, some with fixed-point arithmetic and some
with floating point arithmetic. The floating point DSP TMS320C3x, which exploits delayed branch
logic, has as many as three delay slots.
The flexibility of this line of processors has led to it being used not merely as a co-processor for
digital signal processing but also as a main CPU. Newer implementations support standard IEEE
JTAG control for boundary scan and/or in-circuit debugging.
The original TMS32010 and its subsequent variants is an example of a CPU with a modified
Harvard architecture, which features separate address spaces for instruction and data memory but
the ability to read data values from instruction memory. The TMS32010 featured a fast multiply-
and-accumulate useful in both DSP applications as well as transformations used in computer
graphics. The graphics controller card for the Apollo Computer DN570 Workstation, released in
1985, was based on the TMS32010 and could transform 20,000 2D vectors every second.
The 'C5x uses an advanced, modified Harvard-type architecture based on the 'C25 architecture and
maximizes processing power with separate buses for program memory and data memory. The
instruction set supports data transfers between the two memory spaces.
The functional block diagram of TMS320C5x is shown in below figure. It can be divided into four
sub-blocks they are bus structure, on-chip memory and central processing unit (CPU) and on-chip
peripherals.
BUS STRUCTURE:
Separate program and data buses allow simultaneous access to program instructions and data,
providing a high degree of parallelism. For example, while data is multiplied, a previous product can
be loaded into, added to, or subtracted from the accumulator and, at the same time, a new address
can be generated. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation
operations that can all be performed in a single machine cycle. In addition, the 'C5x includes the
control mechanisms to manage interrupts, repeated operations, and function calling.
The PAB provides addresses to program memory space for both reads and writes. The PB also
carries the instruction code and immediate operands from program memory space to the CPU. The
DB interconnects various elements of the CPU to data memory space. The program and data buses
can work together to transfer data from on-chip data memory and internal or external program
memory to the multiplier for single-cycle multiply/accumulate operations.
v. Program controller
The CPU uses the CALU to perform 2s-complement arithmetic. The CALU consists of these
elements:
v. Additional shifters at the outputs of both the accumulator and the product register (PREG)
The CPU includes an independent PLU, which operates separately from, but in parallel with, the
ALU. The PLU performs Boolean operations or the bit manipulations required of high-speed
controllers. The PLU can set, clear, test, or toggle bits in a status register, control register, or any
data memory location. The PLU provides a direct logic operation path to data memory values
without affecting the contents of the ACC or PREG. Results of a PLU function are writ-ten back to
the original data memory location.
MEMORY-MAPPED REGISTERS :
The 'C5x has 96 registers mapped into page 0 of the data memory space. All 'C5x DSPs have 28
CPU registers and 16 input/output (I/O) port registers but have different numbers of peripheral and
reserved registers. Since the memory-mapped registers are a component of the data memory space,
they can be written to and read from in the same way as any other data memory location. The
memory-mapped registers are used for indirect data address pointers, temporary storage, CPU status
and control, or integer arithmetic processing through the ARAU.
PROGRAM CONTROLLER :
The program controller contains logic circuitry that decodes the operational instructions, manages
the CPU pipeline, stores the status of CPU operations, and decodes the conditional operations.
Parallelism of architecture lets the 'C5x perform three concurrent memory operations in any given
machine cycle: fetch an instruction, read an operand, and write an operand.
i. Program counter
v. Instruction register
ON-CHIP MEMORY :
The 'C5x architecture contains a considerable amount of on-chip memory to aid in system
performance and integration:
The 'C5x has a total address range of 224K words 16 bits. The memory space is divided into four
individually selectable memory segments: 64K-word program memory space, 64K-word local data
memory space, 64K-word input/ output ports, and 32K-word global data memory space.
PROGRAM ROM :
All 'C5x DSPs carry a 16-bit on-chip maskable programmable ROM. The 'C50 and 'C57S DSPs
have boot loader code resident in the on-chip ROM, all other 'C5x DSPs offer the boot loader code
as an option. This memory is used for booting program code from slower external ROM or EPROM
to fast on-chip or external RAM. Once the custom program has been booted into RAM, the boot
ROM space can be removed from pro-gram memory space by setting the MP/MC bit in the
processor mode status register (PMST). The on-chip ROM is selected at reset by driving the
MP/MC pin low. If the on-chip ROM is not selected, the 'C5x devices start execution from off-chip
memory.
The on-chip ROM may be configured with or without boot loader code. However, the on-chip ROM
is intended for your specific program.
All 'C5x DSPs carry a 1056-word16-bit on-chip dual-access RAM (DARAM). The DARAM is
divided into three individually selectable memory blocks: 512-word data or program DARAM block
B0, 512-word data DARAM block B1, and 32-word data DARAM block B2. The DARAM is
primarily intended to store data values but, when needed, can be used to store programs as well.
DARAM blocks B1 and B2 are always configured as data memory; however, DARAM block B0
can be configured by software as data or program memory. The DARAM can be configured in one
of two ways:
ii. 544 words 16 bits configured as data memory and 512 words.16 bits configured as program
memory
DARAM improves the operational speed of the 'C5x CPU. The CPU operates with a 4-deep
pipeline. In this pipeline, the CPU reads data on the third stage and writes data on the fourth stage.
Hence, for a given instruction sequence, the second instruction could be reading data at the same
time the first instruction is writing data. The dual data buses (DB and DAB) allow the CPU to read
from and write to DARAM in the same machine cycle.
All 'C5x DSPs except the 'C52 carry a 16-bit on-chip single-access RAM (SARAM) of various sizes
. Code can be booted from an off-chip ROM and then executed at full speed, once it is loaded into
the on-chip SARAM. The SARAM can be configured by software in one of three ways:
The SARAM is divided into 1K- and/or 2K-word blocks contiguous in address memory space. All
'C5x CPUs support parallel accesses to these SARAM blocks. However, one SARAM block can be
accessed only once per machine cycle. In other words, the CPU can read from or write to one
SARAM block while accessing another SARAM block. When the CPU requests multiple accesses,
the SARAM schedules the accesses by providing a not-ready condition to the CPU and executing
the multiple accesses one cycle at a time.
The 'C5x DSPs have a maskable option that protects the contents of on-chip memories. When the
related bit is set, no externally originating instruction can access the on-chip memory spaces.
ON-CHIP PERIPHERALS :
All 'C5x DSPs have the same CPU structure; however, they have different on-chip peripherals
connected to their CPUs. The 'C5x DSP on-chip peripherals available are:
a) Clock generator
b) Hardware timer
c) Software-programmable wait-state generators
d) Parallel I/O ports
e) Host port interface (HPI)
f) Serial port
g) Buffered serial port (BSP)
h) Time-division multiplexed (TDM) serial port
i) User-maskable interrupts
CLOCK GENERATOR :
The clock generator consists of an internal oscillator and a phase-locked loop (PLL) circuit. The
clock generator can be driven internally by a crystal resonator circuit or driven externally by a clock
source. The PLL circuit can generate an internal CPU clock by multiplying the clock source by a
specific factor, so you can use a clock source with a lower frequency than that of the CPU.
HARDWARE TIMER :
A 16-bit hardware timer with a 4-bit prescaler is available. This programmable timer clocks at a rate
that is between 1/2 and 1/32 of the machine cycle rate (CLKOUT1), depending upon the timer's
divide-down ratio. The timer can be stopped, restarted, reset, or disabled by specific status bits.
A total of 64K I/O ports are available, sixteen of these ports are memory-mapped in data memory
space. Each of the I/O ports can be ad-dressed by the IN or the OUT instruction. The memory-
mapped I/O ports can be accessed with any instruction that reads from or writes to data memory.
The IS signal indicates a read or write operation through an I/O port. The 'C5x can easily interface
with external I/O devices through the I/O ports while requiring minimal off-chip address decoding
circuits.
The HPI available on the 'C57S and 'LC57 is an 8-bit parallel I/O port that pro-vides an interface to
a host processor. Information is exchanged between the DSP and the host processor through on-chip
memory that is accessible to both the host processor and the 'C57.
SERIAL PORT :
Three different kinds of serial ports are available: a general-purpose serial port, a time-division
multiplexed (TDM) serial port, and a buffered serial port (BSP). Each 'C5x contains at least one
general-purpose, high-speed synchronous, full duplexed serial port interface that provides direct
communication with serial devices such as codecs, serial analog-to-digital (A/D) converters, and
other serial systems. The serial port is capable of operating at up to one-fourth the machine cycle
rate (CLKOUT1). The serial port transmitter and receiver are double-buffered and individually
controlled by maskable external interrupt signals. Data is framed either as bytes or as words.
The TDM serial port available on the 'C50, 'C51, and 'C53 devices are a full-duplexed serial port
that can be configured by software either for synchronous operations or for time-division
multiplexed operations. The TDM serial port is commonly used in multiprocessor applications
USER-MASKABLE INTERRUPTS:
Four external interrupt lines (INT1±INT4) and five internal interrupts, a timer interrupt and four
serial port interrupts, are user maskable. When an interrupt service routine (ISR) is executed, the
contents of the program counter are saved on an 8-level hardware stack, and the contents of eleven
specific CPU registers are automatically saved (shadowed) on a 1-level-deep stack. When a return
from interrupt instruction is executed, the CPU registers' contents are restored.
RESULT
Ex. no: 8 A
AIM:
To write an assembly language program to perform addition of two numbers using direct
addressing mode.
APPARATUS REQUIRED:
1. Personal computer
2. RS232C interface cable
3. TMS320C5416 DSP Processor
ALGORITHM:
INP1 .SET 0H
INP2 .SET 1H
OUT .SET 2H
.mmregs
.text
START:
LD #140H,DP
RSBX CPL
NOP
NOP
NOP
NOP
LD INP1,A
ADD INP2,A
STL A,OUT
HLT: B HLT
INPUT:
Data Memory:
A000h 0004
A001h 0004
OUTPUT:
Data Memory:
A002h 0008
RESULT:
Thus the Assembly language program for addition of two numbers using direct addressing
mode was performed and implemented using TMS320C5416 DSP processor
Ex. no: 8 .B
AIM:
To write an assembly language program to perform subtraction of two numbers using direct
addressing mode.
APPARATUS REQUIRED:
1. Personal computer
2. RS232C interface cable
3. TMS320C5416 DSP Processor
ALGORITHM:
PROGRAM:
INP1 .SET 0H
INP2 .SET 1H
OUT .SET 2H
.mmregs
.text
START:
LD #140H,DP
RSBX CPL
NOP
NOP
NOP
NOP
LD INP1,A
SUB INP2,A
STL A,OUT
HLT: B HLT
INPUT:
DATA MEMORY:
A000h 0004
A001h 0002
OUTPUT:
DATA MEMORY:
A002h 0002
RESULT:
Thus the Assembly language program for subtraction of two numbers using direct addressing mode
was performed and implemented using TMS320C5416 DSP processor.
Ex. no: 8. C
To write an assembly language program to perform division of two numbers using direct
addressing mode.
APPARATUS REQUIRED:
1. Personal computer
2. RS232C interface cable
3. TMS320C5416 DSP Processor
ALGORITHM:
Set the data memory locations of Dividend, Divisor, Quotient and Remainder.
Start the program
Initialize the data memory page.
Reset the Complier mode (CPL) bit and fractional mode (FRCT) bit.
Delay is given by NOP (No Operation).
Dividend data is loaded into Accumulator A.
Data which is in Accumulator A is divided by divisor and the result is stored in
Accumulator A.
Lower 16 bit Result (Quotient) of Accumulator A is stored at A002H.
Higher 16 bit Result (Remainder) of Accumulator A is stored at A003H.
Halt the program.
PROGRAM:
DIVID .SET 0H
DIVIS .SET 1H
QOUT .SET 2H
REMAIN .SET 3H
.mmregs
.text
START:
STM #140H,ST0
RSBX CPL
RSBX FRCT
NOP
NOP
NOP
NOP
LD DIVID,A
RPT #0FH
SUBC DIVIS,A
STL A,QOUT
STH A,REMAIN
HLT: B HLT
INPUT
DATA MEMORY
A000H 0009
A001H 0002
OUTPUT
DATA MEMORY
A002H 0004
A003H 0001
Sample Viva questions:
RESULT:
Thus the Assembly language program for division of two numbers using direct addressing mode
was performed and implemented using TMS320C5416 DSP processor.
Ex. no: 8. D
AIM:
To write an assembly language program to perform addition of two numbers using indirect
addressing mode.
APPARATUS REQUIRED:
1. Personal computer
2. RS232C interface cable
3. TMS320C5416 DSP Processor
ALGORITHM:
PROGRAM:
.mmregs
.text
START:
LD #00H,A
STM #1000H,AR4
STM #2000H,AR5
STM #3000H,AR6
LD *AR4,A
ADD *AR5,A
STL A,*AR6+
HLT: B HLT
INPUT:
DATA MEMORY:
1000h 0002
2000h 0004
OUTPUT:
DATA MEMORY:
3000h 0006
Sample Viva questions:
RESULT:
Thus the Assembly language program for addition of two numbers using indirect addressing
mode was performed and implemented using TMS320C5416 DSP processor.
Ex. no: 8. E
AIM:
To write an assembly language program to perform subtraction of two numbers using direct
addressing mode.
APPARATUS REQUIRED:
1. Personal computer
2. RS232C interface cable
3. TMS320C5416 DSP Processor
ALGORITHM:
.mmregs
.text
START:
LD #00H,A
STM #1000H,AR4
STM #2000H,AR5
STM #3000H,AR6
LD *AR4,A
SUB *AR5,A
STL A,*AR6+
HLT: B HLT
INPUT:
DATA MEMORY:
1000h 0008
2000h 0003
OUTPUT:
DATA MEMORY:
3000h 0005
Thus the Assembly language program for subtraction of two numbers using indirect addressing
mode was performed and implemented using TMS320C5416 DSP processor.
Ex. no: 8 F
AIM:
To write an assembly language program to perform multiplication of two numbers using indirect
addressing mode.
APPARATUS REQUIRED:
1. Personal computer
2. RS232C interface cable
3. TMS320C5416 DSP Processor
ALGORITHM:
.mmregs
.text
START:
STM #0140H,ST0
STM #40H,PMST
STM #0A000H,AR0
ST #1H,*AR0
LD *AR0+,T
ST #2H,*AR0
MPY *AR0+,A
STL A,*AR0
HLT: B HLT
.END
RESULT:
Thus the Assembly language program for multiplication of two numbers using indirect addressing
mode was performed and implemented using TMS320C5416 DSP processor.
Ex. no: 9
GENERATION OF VARIOUS SIGNALS AND RANDOM
Date: NOISE
AIM:
To write a program to generate various signals and random noise using TMS320C54 processor.
APPARATUS REQUIRED:
1. Personal computer
2. RS232C interface cable
3. TMS320C5416 DSP Processor
PROCEDURE:
RESULT:
Thus the program for generation of various signals and random noise was executed successfully &
implemented using TMS320C5416 Processor.
Ex.no:12(a)
IMPLEMENT DOWN-SAMPLING OPERATION IN DSP PROCESSOR
Date:
AIM:
To perform the down sampling process for the given sequence.
SOFTWARE REQUIRED:
FLOW CHART:
Start
Stop
DOWN SAMPLING
PROGRAM:
clc;
clear all;
close all;
N=input('Enter the sequence length N:');
M=input('Enter the down sampling factor M:');
f1=0.05;
f2=0.2;
t=0:1:N-1;
x=sin(2*pi*f1*t)+sin(2*pi*f2*t);
x1=x(1:M:N);
t1=1:1:N/M;
subplot(3,1,1);
plot(t,x);
xlabel('time-->');
ylabel('amplitude-->');
title('Input analog signal');
subplot(3,1,2);
stem(t,x);
xlabel('n-->');
ylabel('amplitude-->');
title('Sampled signal');
subplot(3,1,3);
stem(t1-1,x1);
xlabel('n-->');
ylabel('amplitude==>');
title('Down sampled signal');
OUTPUT:
Enter the sequence length N:30
Enter the down sampling factor M:2
analog signal
amplitude--> 2
-2
0 5 10 15 20 25 30
time-->
sampled signal
2
amplitude-->
-2
0 5 10 15 20 25 30
n-->
Down sampled signal
2
amplitude==>
-2
0 2 4 6 8 10 12 14
n-->
RESULT:
Thus the down sampling of the given signal was performed and executed using MATLAB
Ex.no:12(b
)
IMPLEMENT AN UP-SAMPLING OPERATION IN DSP PROCESSOR
Date:
AIM:
SOFTWARE REQUIRED:
ALGORITHM:
FLOW CHART:
Start
↓
Enter the sequence
& upsampling
Perform up sampling
Display the
upsampled o/p
Stop
UPSAMPLING
PROGRAM:
clc;
clear all;
close all;
N=input('Enter the sequence length N:');
L=input('Enter the upsampling factor L:');
f1=0.01;
f2=0.2;
t=0:1:N-1;
x=sin(2*pi*f1*t)+sin(2*pi*f2*t);
x1=[zeros(1,L*N)];
t1=1:1:L*N;
j=1:L:L*N;
x1(j)=x;
subplot(3,1,1);
plot(t,x);
xlabel('time-->');
ylabel('amplitude-->');
title('Input analog signal');
subplot(3,1,2);
stem(t,x);
xlabel('n-->');
ylabel('amplitude-->');
title('sampled signal');
subplot(3,1,3);
stem(t1-1,x1);
xlabel('n-->');
ylabel('amplitude==>');
title('upsampled signal');
OUTPUT:
Enter the sequence length N:10
Enter the upsampling factor L:3
analog signal
2
amplitude--> 1
-1
0 1 2 3 4 5 6 7 8 9
time-->
sampled signal
2
1
amplitude-->
-1
0 1 2 3 4 5 6 7 8 9
n-->
upsampled signal
2
1
amplitude==>
-1
0 5 10 15 20 25 30
n-->
RESULT:
Thus the upsampling of the given signal was performed and executed using MATLAB