AXI IP -V Plan

AIonSi
Author: Vyshnavi CH
Date:

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 Version Information
S. No Date Author Version Description Issue Change
Name
1. Vyshnavi V1.00 Rs232 system controller
Ch

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

S.No Table of Content Page
No.
1 Interface 5
1.1 rs232_syscon_interface 5

2 Features 6
1.single write 6
2.single read

3. Multiple read
4. watchdog timer out, err_i response check 7
5. watchdog timeout before “ack_i
6.Watchdog timeout before bus grant

3 Stimulus 8
3.1 Direct Stimulus
3.2 Random Stimulus
3.3 Constraint Random Stimulus
4 TB Architecture 9
4.1 Block Diagram of rv232vip 9
4.2 Architecture Components of rv232 9
4.2.1 Top 10
4.2.2 Test 10
4.2.3 Environment 10
4.2.3.1 Scoreboard & Coverage
4.2.3.2 Rv232_agent

4.2.4 rv232_sequence

10
5 Checker 11
11

11

6 Functional Coverage 12
6.1 Covergroup 12
6.1.1 Covergroup write_cg 12
3

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 6.1.2 Covergroup read_cg

12

7 Assertion 13

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

1. Introduction:

o A soft-core implemented in Verilog serving as a serial-port-to-bus interface.

o Primarily designed for debugging system components such as memory, registers,

and peripheral interfaces (e.g., PS/2 mouse/keyboard interfaces).

o Enables on-chip debugging within a “system on a chip” (SOC) design.

2. Interface:

2.1 000000
 Input to DUT / Output from test bench :

logic clk_i;
logic reset_i;
logic master_bg_i;
logic rs232_rxd_i
logic ack_i
bit [DAT_DIGITS_PP 1:0] dat_io; ///inout port

logic rst_o
logic stb_o
logic cyc_o
logic [ADR_DIGITS_PP -1:0] adr_o;
logic we_o;

 Output from DUT / Input to test bench :

logic master_br_o;
logic err_i
bit [DAT_DIGITS_PP 1:0] dat_io ///inout port

logic rs232_txd_o03

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3. Functionality:
Signal Description

clk_i Clock input (45MHz)

reset_i reset

master_bg_i Bus grant from master

master_br_o Bus request from rs232_syscon

ack_i Wishbone bus cycle acknowledge

err_i Wishbone bus ycle error

stb_o Wishbone strobe output

cyc_o Wishbone cycle output(wired to stb_o in this version)

adr_o Address bus {Width of address bus in nibbles (4 =>16bits, 8 => 32 bits)}

dat_io Data bus (tri-state) {Width of data bus in nibbles}

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

Signal Description

we_o Wishbone Write enable output

rs232_rxd_i rs232 serial port data input

rs232_txd_o rs232 serial port data output

Wishbone standard interface:

Wishbone indicates
signal
cyc_o Cycle output 1 valid bus cycle is in progress.
ack_i Acknowledge input 1 Normal Termination of a bus cycle
adr_o Address output 16/32/64 s used to pass a address.
array
err_i Error input 1 an abnormal cycle termination

stb_o Strobe output a valid data transfer cycle.

we_o write enable indicates whether the current local bus

output cycle is a READ or WRITE cycle. The signal
is negated during READ cycles, and is
asserted during WRITE cycles
 Serial BAUD Rate Generation:

o Baud rate: the measure of the number of changes to the signal (per second) that
propagate through a transmission medium.

o Uses an internal signal, serial_clk_16x, which is a clock enable running at 16× the
desired BAUD rate.

o For 115,200 BAUD it is a high pulse which occurs for one single “clk_i” clock period,
at a rate of 16*115200 = 1.8432 MHz(==clk period of serial_clk_16x)

 Command Types:

Command type format function

Write(w) w aaaa dddd qq Writes a hexadecimal
value to a specified
address, with optional
quantity (auto-increments
address for multi-word
7

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 writes).

Read(r) r aaaa qq Reads a specified quantity

of words starting at a
given address.

Initialize(i) i Resets the rs232_syscon

unit (does not reset
peripherals; an explicit i
command is needed).

 Fields in the command line

field default If left out/not specified Command description (considering

for 16bit addr and data width
data Zero assumes the previous If dddd =0005 aaaa=0017
field value. Command=w 17 5
address Zero assumes the previous
field value. If Command,
w 5434540017 66677560005
aaaa = 0017
dddd = 0005
quantity 1 it assumes the value “1,” qq=0 command will do nothing. No
field bus cycles will be generated.

qq>1 the aaaa is automatically

incremented during the subsequent
iterations of the command loop.
dddd remains the same.

 Initial Power-up Display:

o On startup, the module sends the characters “0123456789ABCDEF” to the terminal.

o This display helps verify that the terminal is set to the correct BAUD rate.

 Watchdog Timer:

o Ensures timely bus transactions by monitoring bus request and cycle completion.

o It is used twice during the execution of a command.

o The first time it is used to determine if there was a timeout for obtaining

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 o the bus, and the second time it is used to determine if the bus cycle timed out, with
no “ack_i” response.

o Therefore, a slow master together with a slow peripheral could conceivably use
almost twice the time period of the watchdog timer, in order to complete the
execution of the command.

o address bus implemented here is not bi directional, so there is a need of

multiplexer inside syscon in order to select which device gets to drive the address
bus

o but this may introduce some delay on the bus. when debugging is completed, the
mux can be removed (or “hard wired” by a parameter at compile time, which will
also result in the eventual removal of the mux because of optimization in the
synthesis and routing tool

o the data bus is implemented as a tri-state bus, so that it can be bi-directional

without requiring the use of multiplexers

o Wishbone standard seems to encourage a split data bus (dat_i for input data and
dat_o for output data) but found that the Wishbone standard also allows for tri-
state connections

o reduces the number of internal interconnects needed to implement the bus.

o If a tri-state bus is unacceptable for your application, the rs232_syscon block can be
easily modified to add “dat_i” and “dat_o” ports in place of the existing “dat_io”
port, and the tri-state buffering can be removed.

 Handshaking and adding wait states/extending bus cycle:

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 o Once the bus request (br) is detected at the normal bus master, it should finish the
current operation, and then assert and keep asserting “master_bg” to rs232_syscon.

o As long as the bus grant (bg) line is asserted into rs232_syscon, then rs232_syscon
will know that it has control of the bus.

o Also, when rs232_syscon finishes generating its bus cycles, it does notcheck or wait
for the bus grant line to be deasserted. Therefore, those

o who wish to test peripherals, memory or registers without another master on the
bus, can simply tie “master_bg_i” high, or just connect it to the rs232_syscon’s
“master_br_o” and forget about that handshaking interface.

o The bus cycles generated by rs232_syscon are one clock long.

o The length of each bus cycle is extended until the “ack_i” signal is received by
rs232_syscon

4. Features:
 maximum clock speed of clk of around 45 MHz
extend the base testclass and write testcases for
 Reset
 Single Write operation(w)
 Single Read operation (r)
 Multiple read by specifying quantity field(qq) in the command
Verify whether the written locations are read out properly
observe the below read-write command inputs and the read out
data on the corresponding write address locations

10

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 w 1 55 1
w 1 5a 1
w 4 4c
w 2 140
w 3 100
w 4 5c
w 4 6c 4
w 2 150 2
w 3 f8
w 3 f0
w 3 f8
w 3 f7
w 3 48 3
r3 0003 : 0048
r08 0000 : 0000 005A 0150 0048 006C 0000 0000 0000 qq=8
8 bus
cycles /bus
operations
Address field
is
automatically
incremented
r 0 10 0000 : 0000 005A 0150 0048 006C 0000 0000 0000
0008 : 0000 005A 0150 0048 006C 0000 0000 0000
r 0 20 0000 : 0000 005A 0150 0048 006C 0000 0000 0000
0008 : 0000 005A 0150 0048 006C 0000 0000 0000
0010 : FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF
0018 : FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF
w 3 58
w 3 68 3
r 0 10 0000 : 0000 0068 0068 0068 0068 0068 0068 0068
0008 : 0000 0068 0068 0068 0068 0068 0068 0068
w 3 58 1 3
w 4 68 1
r 0 10 0000 : 0000 0068 0068 0058 0068 0068 0068 0068
0008 : 0000 0068 0068 0058 0068 0068 0068 0068
w 4 6c 1
w 4 7c 1 4
w 1 f4 1 1
r08 0000 : 0000 00F4 0068 0058 007C 0068 0068 0068

5.watchdog timer testcases

watchdog timer out, err_i response check
 watchdog timeout before “ack_i
11

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 If the watchdog timer expires before “ack_i”is received, then a
bus error message is generated for the user.
if the “err_i” signal is received, then a bus error message is
generated for the user
 Watchdog timeout before bus grant

6. wishbone standard signal testcase(doubt)

7. check for below error occurring testcases

5. Stimulus:

 Stimulus are the input data which is given to the design.

command character format

nibble data width and address width
String type(r,w,i_) ‘h aaaa ‘h dddd ‘h qq
Above format is for 16 bit data and address bus(hexadecimal representation)
 Width of address/data bus in nibbles (4 =>16bits, 8 => 32 bits)
 Stimulus can be passed directly as direct values or as random values depending on
requirement.
 There are classified into three types of stimulus and they are,

5.1 Direct Stimulus:[Yes Required]

 In Direct Stimulus we give the values directly to the stimulus without giving
random values for inputs.

12

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 5.2 Random Stimulus: [Yes Required]
 In random Stimulus we will give random data for input signals.
 Signal to be randomized:
o rand bit [ADR_DIGITS_PP-1:0] adr_o ;
o rand bit [DAT_DIGITS_PP-1:0] dat_io;

5.3 Constraint Random Stimulus: [Yes Required]

 Constraint Random Stimulus will generate meaningful stimulus for constraints
which we give in the stimulus.
o rand bit [ADR_DIGITS_PP-1:0] adr_o ;
o rand bit [DAT_DIGITS_PP-1:0] dat_io;

4. TB Architecture:

4.1 Block Diagram of RS232 syscon vip:

tb_top

rs232_if Test rs232_Syscon.v(DUT)

Assertions

5.
Test
6.

ENV
rs232_sequence
rs232_scoreboard rs232_coverage
Reference logic

rs232_agent

rs232_sequencer

rs232_driver rs232_monitor

13

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

rs232_Syscon.v(DUT)
4.2 Architecture Components of rs232 vip:
The following components are needed in architecture to verify the rs232 syscon
verification IP.
 Top
 Test
 Environment
 Scoreboard
 Coverage
 rs232 _agent
 rs232_driver
 rs232_monitor
 rs232_sequencer
 rs232 _sequence
4.2.1 Top :
Top module contains:
 rs232_test
 rs232_if

4.2.2 Test :
 In Test all the test cases are declared.

 Then, we need to create an environment.

4.2.3 Environment:
 In Environment configuration class we have agent configuration class and
agent.
 We need to create scoreboard, coverage and all agents

 Scoreboard:
In scoreboard we compare the data from rs232_agent’s monitor to verify
whether comparison is successful or not.
 Comparison logic to be happened with
1. Reset
2. Write
3. Read
4. Multiple write(doubt)
5. Multiple read(compare if the recent read address data
corresponds to last updated write data on the same addr
location (data is overwritten or not)
make use of a queue for better comparision
6.
14

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 4.2.3.1 rs232_agent:
 Create Driver class to drive the input signals.to DUT through interface
 Create Monitor class -receives pin data from the DUT through interface
 Create Sequencer to transfer data between sequence class and driver.

4.2.3.1.1 rs232_driver:
 In Driver we drive the data that is generated by sequence, and send
it to DUT by the interface rs232_interface.
4.2.3.1.2 rs232_monitor:
 Monitor collect the data from DUT using rs232_interface and send
it to scoreboard.
4.2.3.1.3 rs232_sequencer:
 In sequencer we get the data from sequence and send it to driver to
drive it to DUT.
4.2.4 rs_232_sequence:
 In Sequence we will generate the data and send it to driver.

5. Checkers
In checker we compare actual output from design with expected output from monitor
and verify the same.

6. Functional Coverage: [Yes Required]

For this Ip we need two covergroup for covering the functional coverage part.

6.1Covergroup: [Yes Required]

Covergroup will generate a specification of the coverage model.

6.1.3 Covergroup write_cg

6.1.4 Covergroup read_cg

7. Assertion:[Required]
 Assertions are used to validate the behaviour of the design.
15

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

Master_bg_o next cycle read /write operation on the bus

16

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA