MICROCONTROLLERS AND EMBEDDED SYSTEMS

o Second, ARM10 uses branch prediction, which reduces the effect of a pipeline
flush by predicting possible branches and loading the new branch address prior to
the execution ofthe instruction.
o Third, an instruction in the execute stage will complete even though an interrupt
has been raised. Other instructions in the pipeline will be abandoned, and the
processor will start filling the pipeline.

EXCEPTIONS, INTERRUPTS AND THE VECTOR TABLE:

 When an exception or interrupt occurs, the processor sets the pc to a specific memory
address. The address is within a special address range called the vector table.
o The entries in the vector table are instructions that branch to specific routines
designed to handle a particular exception or interrupt.
o The memory map address 0x00000000 (or in some processors starting at
the offset 0xffff0000) is reserved for the vector table, a set of 32-bit words.
 When an exception or interrupt occurs, the processor suspends normal execution
and starts loading instructions from the exception vector table (see the following
Table).

Table: The Vector Table

Exception/Interrupt Shorthand Address High
Address
Reset RESET 0x00000000 0x00000000
Undefined instruction UNDEF 0x00000004 0xffff0004
Software interrupt SWI 0x00000008 0xffff0008
Prefetch abort PABT 0x0000000c 0xffff000c
Data abort SABT 0x00000010 0xffff0010
Reserved – 0x00000014 0xffff0014
Interrupt request IRQ 0x00000018 0xffff0018
Fast interrupt request FIQ 0x0000001c 0xffff001c

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 Each vector table entry contains a form of branch instruction pointing to the start of a
specific routine:
o Reset vector is the location of the first instruction executed by the processor when
power is applied. This instruction branches to the initialization code.
o Undefined instruction vector is used when the processor cannot decode an
instruction.
o Software interrupt vector is called when you execute a SWI instruction. The SWI
instruction is frequently used as the mechanism to invoke an operating system
routine.
o Prefetch abort vector occurs when the processor attempts to fetch an instruction
from an address without the correct access permissions. The actual abort occurs in
the decode stage.
o Data abort vector is similar to a prefetch abort, but is raised when an instruction
attemptsto access data memory without the correct access permissions.
o Interrupt request vector is used by external hardware to interrupt the normal
execution flow of the processor. It can only be raised if IRQs are not masked in
the cpsr.
o Fast interrupt request vector is similar to the interrupt request, but is reserved for
hardware requiring faster response times. It can only be raised if FIQs are not
masked in the cpsr.

CORE EXTENSIONS:
 Core extensions are the standard hardware components placed next to the ARM core. 
 They improve performance, manage resources, and provide extra functionality and are
designedto provide flexibility in handling particular applications. 
Each ARM family has different extensions available. There are three hardware extensions:
cache andtightly coupled memory, memory management, and the coprocessor interface.

Cache and Tightly Coupled Memory:

 The cache is a block of fast memory placed between main memory and the core. It allows
for more efficient fetches from some memory types. With a cache the processor core can
run for the majority of the time without having to wait for data from slow external
memory.
 Most ARM-based embedded systems use a single-level cache internal to the processor. 

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 ARM has two forms of cache. The first is found attached to the Von Neumann–style
cores. It combines both data and instruction into a single unified cache, as shown in the
following Figure.

Figure: Von Neumann Architecture with Cache

 The second form, attached to the Harvard-style cores, has separate caches for data and
instruction, as shown in the following Figure.


Figure: Harvard Architecture with TCMs

 A cache provides an overall increase in performance, but at the expense of predictable
execution. But the real-time systems require the code execution to be deterministic— the
time taken for loading and storing instructions or data must be predictable. 

 This is achieved using a form of memory called tightly coupled memory (TCM). TCM is

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 fast SRAM located close to the core and guarantees the clock cycles required to fetch
instructions or data.
 TCMs appear as memory in the address map and can be accessed as fast memory. 

By combining both technologies, ARM processors can have both improved performance and
predictable real-time response. The following Figure shows an example core with a combination
of caches and TCMs.

Figure: Harvard Architecture with Caches and TCMs

Memory Management:
 Embedded systems often use multiple memory devices. It is usually necessary to have a
method to organize these devices and protect the system from applications trying to make
inappropriate accesses to hardware. This is achieved with the assistance of memory
management hardware.
 ARM cores have three different types of memory management hardware—
o no extensions providing no protection
o a memory protection unit (MPU) providing limited protection
o a memory management unit (MMU) providing full protection.

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 Non protected memory is fixed and provides very little flexibility. It is normally used for
small, simple embedded systems that require no protection from rogue applications. 
 MPUs employ a simple system that uses a limited number of memory regions. These
regions are controlled with a set of special coprocessor registers, and each region is
defined with specific access permissions. This type of memory management is used for
systems that require memory protection but don’t have a complex memory map. 

 MMUs are the most comprehensive memory management hardware available on the
ARM. The MMU uses a set of translation tables to provide fine-grained control over
memory. These tables are stored in main memory and provide a virtual-to-physical
address map as well as access permissions. MMUs are designed for more sophisticated
platform operating systems that support multitasking. 
Coprocessors:
 Coprocessors can be attached to the ARM processor. A coprocessor extends the
processing features of a core by extending the instruction set or by providing
configuration registers. More than one coprocessor can be added to the ARM core via the
coprocessor interface.
 The coprocessor can be accessed through a group of dedicated ARM instructions that
provide a load-store type interface.
o For example, coprocessor 15: The ARM processor uses coprocessor 15 registers
to control the cache, TCMs, and memory management.
 The coprocessor can also extend the instruction set by providing a specialized group of
new instructions.
o For example, there are a set of specialized instructions that can be added to the
standard ARM instruction set to process vector floating-point (VFP) operations.
 These new instructions are processed in the decode stage of the ARM pipeline. 
o If the decode stage sees a coprocessor instruction, then it offers it to the relevant
coprocessor.
o If the coprocessor is not present or doesn’t recognize the instruction, then the
ARM takes an undefined instruction exception, which allows you to emulate the
behavior of the coprocessor in software.

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