GOVERNMENT COLLEGE OF ENGINEERING
(AUTONOMOUS)
BARGUR - 635104
22LPEV101 – DIGITAL DESIGN WITH FPGA
UNIT – 2 : BEHAVIORAL MODELING
When to use
Blocking assignment (= ) and NonBlocking Assignment(<= )
VERILOG CODE FOR HALF ADDER USES
BOTH
BLOCKING ,NONBLOCKING ASSIGNMENT
DELAY IN PROCEDURAL ASSIGNMENTS
• In Verilog, regular delay and intra-assignment delay are two ways to
introduce timing control in behavioral modeling.
Conditional Statements in Verilog- Decision Making
• If
• If-else
• If - else if- else
• case
If-Elseif example
if - Inside an always Block (Combinational Logic)
if -with Procedural Assignment (<=) in Sequential Logic
CASE
The case statement in Verilog is used for multi-way branching,
similar to the switch statement in C.
It simplifies decision-making and is useful in designing
multiplexers, state machines, decoders, and control logic.
Syntax:
MCQS FROM BEHAVIORAL MODELING IN VERILOG
LOOPING CONSTRUCTS
• for loop
• While loop
• Repeat loop
• Forever loop
KEY DIFFERENCES BETWEEN LOOPS