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hw1 Ee143 f14 Web Soln

The document is a problem set for EE 143 Microfabrication Technology, detailing tasks related to device cross-sections, MOSFET characteristics, and fabrication yield/cost calculations. It includes specific problems on identifying transistors, analyzing circuit parameters, and calculating costs per good die for different wafer sizes. The solutions involve calculations for threshold voltage, drain current, and cost analysis based on yield percentages.

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14 views4 pages

hw1 Ee143 f14 Web Soln

The document is a problem set for EE 143 Microfabrication Technology, detailing tasks related to device cross-sections, MOSFET characteristics, and fabrication yield/cost calculations. It includes specific problems on identifying transistors, analyzing circuit parameters, and calculating costs per good die for different wafer sizes. The solutions involve calculations for threshold voltage, drain current, and cost analysis based on yield percentages.

Uploaded by

ria.na.bur.kh.adth
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE 143 MICROFABRICATION TECHNOLOGY FALL 2014

C. Nguyen

PROBLEM SET #1 (SOLUTIONS)


Issued: Tuesday, Sep. 2, 2014
Due: Wednesday, Sep. 10, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory

I. Device Cross-Sections/Symbols
1. Consider the merged MEMS-transistor integrated circuit cross-section shown
below. Identify the transistors (i.e., two MOS and one bipolar transistor) and draw
the corresponding symbols for each of the transistors on top of the figure in the
appropriate positions, i.e., with the “arrow part” of the symbol over the right region,
etc.

NMOS PMOS NPN


n-substrate bias connected
to the highest voltage

Note that the bipolar device in the circuit would have a poor performance due to its
large base width as shown below.
Emitter Base Collector
N+ P+ N+

P well

In practice, to make a lateral bipolar device (in contrast to the vertical version
discussed in lecture), the configuration of terminals would rather be arranged to
minimize the base width, such as
Emitter Collector Base
N+ N+ P+

Buried P+
P well

II. MOSFET Characteristics


2. Consider the following circuit. Assume that transistor M1 is operated in the
saturation region and that its bias voltages, V1 and V2, process parameter K (=
EE 143 MICROFABRICATION TECHNOLOGY FALL 2014
C. Nguyen

COX), and threshold voltage Vth can be changed independently. Assume there are no
non-ideal effects except channel length modulation. Indicate in the table how an
increment in each of these parameters changes the gate current I1, and the drain
current I2. Use symbols: ↑ for increase, ↓ for decrease, -- for no change.

I1 I2
I1 V1 ↑ -- 
I2 V2 V2 ↑ -- ↑
V1 M1
K↑ -- ↑
Vth ↑ -- 

3. Consider the cross-section of an NMOS device shown below.


Assume the channel length 𝐿 = 0.5 𝜇𝑚, the channel width 𝑊 = 50 𝜇𝑚, the gate
oxide thickness 𝑇𝑂𝑋 = 9 𝑛𝑚, the Fermi level Φ𝐹 = 0.4 𝑉, the zero-bias threshold
voltage 𝑉𝑡ℎ0 = 0.7 𝑉, the substrate doping concentration = 9 × 1014 𝑐𝑚−3, and the
relative permittivity of Si = 11.8 and of SiO2 = 3.9, respectively.

VG VDD VX

FOX TOX FOX


n+ n+ p+
L

p-substrate

a. Calculate the threshold voltage when VX = 0.5 V, VDD = 5 V, and VG = 2 V.


𝑉𝑆 = 0𝑉, 𝑉𝐵 = 𝑉𝑋 = 0.5 𝑉
𝑉𝑡ℎ = 𝑉𝑡ℎ0 + Υ (√𝑉𝑆𝐵 + 2|𝜙𝑓 | − √2|𝜙𝑓 |)

𝜖𝑆𝑖𝑂2
𝐶𝑜𝑥 = = 3.84 × 10−7 𝐹/𝑐𝑚2
𝑇𝑜𝑥

√2𝑞𝜖𝑆𝑖 𝑁𝐵
Υ= = 0.0452 𝑉 1/2
𝐶𝑜𝑥

𝑉𝑡ℎ = 0.7 + 0.0452(√(0 − 0.5) + 0.8 − √0.8) = 0.684 𝑉


EE 143 MICROFABRICATION TECHNOLOGY FALL 2014
C. Nguyen

b. (Continuing from a.) Calculate the drain current ID.


1 𝑊 1 50
𝐼𝐷 = 𝜇𝐶𝑜𝑥 (𝑉𝐺 − 𝑉𝑡ℎ )2 = 350 × 3.84 × 10−7 × (2 − 0.684)2
2 𝐿 2 0.5
= 11.638 𝑚𝐴

c. Repeat b. with VX = 0 V.
1 𝑊
𝐼𝐷 = 𝜇𝐶𝑜𝑥 (𝑉𝐺 − 𝑉𝑡ℎ0 )2 = 11.357 𝑚𝐴
2 𝐿

d. Now, suppose VX can be varied while other voltage biases are fixed. Calculate
the value of VX that causes the device to cut off.
Device cuts off when 𝑉𝐺 = 𝑉𝑡ℎ = 2 𝑉,
𝑉𝑡ℎ = 𝑉𝑡ℎ0 + Υ (√𝑉𝑆𝐵 + 2|𝜙𝑓 | − √2|𝜙𝑓 |)

2 = 0.7 + 0.0452 (√|(𝑉𝑆 − 𝑉𝐵 ) + 0.8| − √0.8) ⇒ 𝑉𝐵 = −878.65𝑉

* Obviously, this is an unreasonably large voltage that such transistors can’t


tolerate. However, in typical transistors the body effect parameter would be in
the range of 0.3 to 0.4 V1/2, which makes the value of VB that cuts off the device
around a reasonable -15V.

III. Fabrication Yield/Cost


4. The cost of processing a wafer in a particular process is $1,000. Assume that 85%
of the fabricated dice are good. For this problem, use the figure below (i.e., Fig.
1.1(c) in the textbook) to determine the number of dice.
a. Determine the cost per good die for a 150 mm wafer.
A 150-mm wafer has ~200 10×10-mm dies  𝑐𝑜𝑠𝑡⁄𝑔𝑜𝑜𝑑 𝑑𝑖𝑒 =

$1000⁄
200 × 0.85 = $5.88.
b. Repeat for a 200 mm wafer.
Given the same fabrication cost and yield, a larger wafer results more dies and
consequently lower cost per unit.
𝑐𝑜𝑠𝑡⁄ $1000⁄
𝑔𝑜𝑜𝑑 𝑑𝑖𝑒 = 300 × 0.85 = $3.92.
EE 143 MICROFABRICATION TECHNOLOGY FALL 2014
C. Nguyen

~300
~200

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