A flag is a single bit status register (Flip- 6.

The flags are set or reset according to

Flop) Flags are either set or reset by ALU Immediate Addressing Mode:- the result of operations in status register
according to the result by ALU.There are 1.In Immediate Addressing mode, the data and it is 8-bit.
total 5 flags:-1.Sign flag(S). 2. Zero appears immediately after opcode of
flag(Z). 3.Auxiliary Carry flag(Ac). instruction in program memory Accumulator:-1.Accumulator is 8-bit main
4.Parity flag (P) 2.In these instructions the actual data is register in 8085, used to perform the
5.Carry flag(Cy) specified within the instruction arithmetical and logical operations. In such
3.These operations are specified with either operations one of the operand is always
D7 D6 D5 D4 D3 D2 D1 D0 2 or 3 byte instructions 4.Example: ADI 05 stored in accumulator 2.lt final result of
Hb, Example: LXI 2010H operation is always stored in accumulator
Register Indirect Addressing Mode: 3.All data transfer between the CPU and
S Z - AC - P - Cy 1.In register indirect Addressing mode, the I/O devices are performed through
content of register pair points to the accumulator.
address of the Features of 8085:- 1.Intel's 8085 is an 8-bit
operand microprocessor, 8-bit data bus width
1. S-sign flag: 2.A register pair (H-L) is specified for indicates that 1 byte of data can be passed
i)After the execution of arithmetic or logic on this bus 2. 8085 chip is available in 40
addressing 16- bit address of memory
operation, if bit D7 of result is 1, the sign pin plastic ceramic DIP package 3.It has
location
flag is set to 1. 16-bit bit address bus that means it can
3. These are generally 1- byte instruction
ii) This flag is used with signed numbers.
4.Example: ADD M address a physical memory of 64 kilo bytes
iii) In a given byte, if D7 is 1, the number
5.i.e. this instruction will ass the content of 4.Address bus is divided into two groups.
will be viewed as a negative number, if it
memory location whose address is stored The least significant 8-bit of address bus
is 0, the number will be considered are transferred on same eight lines of the
in H-L pair to the content of Accumulator
positive. data bus. such bus is called multiplexed
Implicit Addressing Mode:
iv) In arithmetic operations with signed
1.In implicit Addressing mode, generally bus. Most significant bits of address are
numbers, bit D7, is reserved for
operand is not specified within transmitted on address bus.
indication of the sign, and the remaining
the instruction and it is predetermined Evolution of Microprocessor
seven bits are used to represent the
2.Generally the operand is accumulator There are five generations:- First
magnitude of a number.
3.Most of the logical group instructions Generation:
2. Z-Zero flag:
i)The zero flag is set to 1 if the ALU belong to this addressing mode 1.Intel's 4004 was the first microprocessor
4.These are single byte instruction available in the market. 2.It was a 4 bit
operation results in 0, and the flag is reset
if the result is not 0. ii)This flag is modified 5..Example: CМА 6.I.e. this instruction will PMOS (P-type metal oxide semiconductor)
by the results in the accumulator as well complement the content of microprocessor introduced in 1971. 3.it was
as in other registers. accumulator, here the actual operand is not designed to be used in calculator. 4.In
3. AC - Auxiliary Carry flag: • In an specified in the instruction, but is 1972, Intel introduced first general purpose
predetermined (Accumulator). The result is 8-bit Microprocessor Intel 8008. 5.Example:
arithmetic operation, when carry is
stored in accumulator. Intel's 4004(4-bit), 8008(8-bit).
generated by digit D3 and passed on to
digit D4 the AC flag is set. •The flag is Buses in Microcomputer:- ➤ Second Generation:-1.In 1974, Intel's
used only internally for BCD (Binary 1.As per the architecture we can see 808о. Motorola's M6800 were introduced.
Coded Decimal) different bus structure All these were 8-bit Microprocessor 2.It
4. P Parity flag: This flag tests for number conducting different lines was enhanced version of Intel 8008. 3.In
of 1 bits in accumulator. 2.Address bus: is used to carry 16 bit second generation, the development of
i) If the - accumulator holds an even address lines, it is unidirectional. microprocessor has been in a direction to
number of 1s, it is said that even parity 3.Data bus: is used to carry 8 bit data complete microprocessor system, i.e. CPU,
exists and the parity flag is set to 1. lines, it is bidirectional . ROM, RAM, clock, I/O ports all in single
ii) If the accumulator holds an odd 4.Control bus: is the bus through which package (microcontroller) 4.In 1976, Intel's
number of is (called odd parity), the parity control signals are carried, control signals 8085, 8-bit Microprocessor was introduced
flag is reset to 0. are generated by CPU. 5.Example: Intel's 8085(8-bit).
5. CY- Carry flag: What is a Microprocessor: A Third Generation:-1.in 1978, Intel
I if an arithmetic operation results in carry, microprocessor is a multipurpose, introduced first 16-bit Microprocessor 8086.
the carry flag is set, otherw reset. The carry programmable logic device that reads 2.It was enhanced version of Intel 8008. 3.lt
flag also serves as a borrow flag for binary instructions from a storage device was followed by Zilog in 1979 & Motorola in
subtraction. called memory, accepts binary data as 1980. 4. in third generation, Memory space
Direct Addressing Mode:- input and processes data according to was 64 KB. 5.The other features were full
1.In direct Addressing mode, the address those Instructions, and provides results as arithmetic execution and efficient higher
appears after opcode of Instruction in output. level language addressing6.Example:
program memory 2.The address of Primary function of the CPU of a Intel's 8086(16-bit).
operand is specified within the instruction microcomputer:- ➤Fourth Generation: 1.In 1981, Intel
3.The instructions using direct addressing 1. To fetch, decode, and execute program introduced first 32-bit Microprocessor
mode are three byte instructions. Byte 1 is instructions in the proper order. 80386. 2.It can address physical memory
opcode of instruction, Byte 2 is lower order 2. Transfer data to and from memory and to of 4GB. 3.Other 32-bit Microprocessor HP-
address and byte 3 is high order address and from I/O section. 32 announced in 1982. 4.in 1987,
4.Example: LDA 9FFF H 3. Responds to external interrupts Motorola's 68020, a 32-bit Microprocessor
5.This instruction loads accumulator 4. provide overall timing and control signals introduced. 5.Example: Intel's 80386(32-
with content of memory location 9FFF H for the entire system bit), Intel's 80486(32-bit)
Register Addressing Mode:- 5. R/W of data into memory so bi- ►Fifth Generation:- 1.In 1993, introduced
1. In register Addressing mode, the source directional bus is required. 64-bit Microprocessor.
operands are general purpose registers Function of ALU:- 1.The arithmetic and 2.Intel made improvement in
whose name is specified within the logic unit is 8-bit unit 2.It performs microprocessor design to provide greatest
instruction arithmetic, logic and rotate operatioris speed.
2. These instructions are single byte 3.lt consists of binary adder to perform 3.System can run new OS like UNIX,
instructions addition and subtraction by 2's complement LINUX etc.
3.Example: MOV A,B method 4.Speed of Microprocessor is 66 MHz to
4.i.e. This instruction transfers the content 4. The result is typically stored in 233 MHz. 5.Fifth generation processor is
of register B to accumulator called as Pentium.
accumulator without modifying the content 5. The Temporary register is used to hold 6.Example: Intel Pentium-l, Intel Pentium-
of B data during an arithmetic/logic operation 11,7.after 1996, Celeron, xenon, Dx4,13,i7
Explain the purpose of following pins in 3) S0, S1 3) It is nonmaskable interrupt. It is unaffected by
microprocessor 8085. a) These are status signals sent by any interrupt enable or mask.
Ans.: (1) ALE: microprocessor to distinguish the various (c) SOD:
1) Address Latch Enable, one special output operations or type of machine cycle in progress. 1) Serial Output Data. It is a data line for serial
signal generated by microprocessor to indicate b) Status Code for Intel 8085 is: output.
beginning of the operation. 4) HLDA: 2) The 7th bit of the accumulator is outputted on
2) It is positive going pulse generated during first a) It is signal for HOLD ACKNOWLEDGEMENT. SOD line when SIM instruction is executed.
clock cycle of machine state and it indicates that b) A HLDA output indicates to a peripheral that a 3) The SOD line eliminates the need for an output
the bits on AD7 – AD0 are address bits. HOLD request has been received and that the port in the software - controlled
3) This signal enables the lower 8-bit of the microprocessor will relinquish control of buses in serial. I/O
address from the multiplexed bus to latch into the next clock cycle. Q.Explain the functions of the following pins
external flip-flop or peripheral device. After AD, c) After the removal of HOLD request HLDA of 8085:
AD, changes over to data bus. goes low. (1) Reset out
4) ALE is never tristated. (2) INTA (3) CLKOUT
Ans.: 1) RESET OUT:
(2) RD:
(1) It indicates that the MPU is being reset.
1) This is read control signal. This is active low (2) It is connected to peripherals to reset them
signal. when MPU is reset.
2) This signal indicates that selected I/O or
2)INTA:
memory device is to be read and data is
(1)INTA is an Abbrevation for interrupt
available on data bus.
Q.Explain following Pins of 8085 Micro- acknowledgment
3) It is tristated during HOLD and HALT.
processor (2) A low an INTA indicates that the processor has
(iii) WR: (i) CLK (out) acknowledged an INTR interrupet .
1) This is write control signal. This is also active (ii) WR
low signal. (iii) RST 5.5 Q. In case of a Microprocessor Architecture,
2) This signal indicates that the data on data bus CLK OUT: explain the following terms in brief:
are to be written into selected memory or I/O (1) The whole circuitry is synchronized with clock (i) Address Bus (ii) Data Bus (iii) Control Bus
locations. (2) The speed of the system depends on the Ans.:
3) It is tristated during HOLD and HALT. clock frequency. (1) Address Bus: The address bus is group of 16
Q Describe in brief functions of following RST 5.5: This signal is used to interrupt the lines generally identified as A0 to A15. It is
pins in 8085 microprocessor. microprocessor. When an interrupt is recognized unidirectional i.e., bits flow in one direction from
(a) HOLD the next instruction is executed from a fixed microprocessing unit (MPU) to peripheral
(b) INTR location in memory Le. 002C H. it is maskable devices. The MPU uses the address bus to
(c) RESET IN interrupt. It cause internal restart to be identify a peripheral or memory location.
Ans.: (a) HOLD: automatically insert. (ii) Data Bus: The data bus is a group of 8 lines
1) It indicates that a peripheral such as DMA (Direct Q.Describe the functions of following pins of
Memory Access) controller is requesting the use of
used for data flow. These lines are bidirectional
8085: Le. data flow in both directions between MPU and
address and data buses.
2) Having received a HOLD request the microprocessor (i) SID memory and peripheral devices. MPU uses data
releases the use of the buses as soon as the current (ii) READY bus for transferring data.
machine cycle is completed. Internal processing may (iii) ALE (iii) Control Bus: Control bus provides necessary
continue. Ans.: (i) SID-1. SID (Serial Input Data). It is a timing and control signals to all the operations in
3) The processor regains the bus after the removal of data line for serial input. microprocessor. It controls the flow of data
the HOLD signal. 2. The 7 bit of the accumulator is inputed on SID between microprocessor, memory and
(b) INTR: line when RIM instruction is executed. peripherals. Control signals in bus are IO/ M, RD,
1) INTR is a level triggered maskable Interrupt Request 3. The SID line eliminates the need of an output
input signal.
WR.
2) This is a general purpose interrupt with lowest
port in the software controlled serial 1/0.
priority. Explain functions of the following pins of 8085 Q.Differentiate between hardware and
3) When interrupt signal is given on this line, the Microprocessor: software interrupts.
microprocessor executes interrupt acknowledge cycle to (i) Multiplexed address/data bus pin (AD0-AD7) Ans: 1) Hardware interrupts:
read interrupt information from interrupting device. (ii) RST 6.5 (i)Hardware Interrupts are used to handle asynchronous
4) When this arises, program counter does not (iii) CLK (OUT) events.
increment its contents. Ans.i) AD-AD, (il)These interrupts are requested by external device.
5) The INTR is enabled or disabled by software. (iii)After execution of these interrupts program counter is
i)Multiple/Multiplexed Address/Data Bus(AD0-
(c) RESET IN: not incremented.
AD7):- (iv)The microprocessor executes either interrupt
1) When the signal on this pin goes low, the 1) The signal lines AD0 to AD7 are bidirectional
program counter is set to 0000L acknowledge cycle or ideal machin cycle to acknowledge
They Serve a dual purpose. They are used as the this interrupt.
2) The buses are tristated and microprocessor low-order address bus as well as the data bus. (v) These interrupts may be non-maskable or maskable.
unit is held in reset condition as long as RESET 2) In executing an instruction, during the earlier (vi) They have lower priority than any software interrupt.
is applied. part of the cycle, these lines are used as the low- (vii) These interrupt affect on interrupts control logic.
3) It also resets interrupt enable and HLDA flip- order address bus. During later part of the cycle, (viii) It improves throughput of the system.
flop. 2) Software interrupts:
these lines are used as the data bus
Q.Describe the functions of following (i) Software interrupts are not used to handle
3) However, the low-order address bus can be
asynchronous events.
pins in 8085 microprocessor. separated from these signals by using a latch. (ii) These interrupts are not requested by external device
1) READY (ii)RST 6.5: Restart interrupt signal is used to but by microprocessor itself (iii)
2) RST 7.5 interrupt the microprocessor. When an interrupt is After execution of these interrupts, program counter is
3) S0, S1 recognised the next instruction is executed from a incremented.
fixed location in memory i.e. 6.5 x 8=0034. It is (iv) The microprocessor does not execute any interrupt
4) HLDA acknowledge cycle. It executes normal instruction cycle.
maskable interrupt. The cause an internal restart
Ans.: 1) READY (v) They cannot be masked or ignored.
a) It is a input signal used by the microprocessor to
to be automatically insert. (vi) Software interrupts has more priority than any
sense whether a peripheral is ready to transfer data or Q.Explain the functions of the following pins hardware interrupt.
not. of 8085: (vii) These interrupts does not affect on interrupt control
b) This signal is used to delay the microprocessor until a Ans.: logic.
slow responding peripheral is ready to send or accept IO / M: (viii) They does not improve throughput of the system.
data. 1) It is a status signal indicates whether the Vectored Interrupt- It means that when these interrupts
c) If READY is high, the peripheral is ready. If it is low, address bus is for I/O device or for memory. are given, it is directed to transfer the control to specific
the microprocessor waits for an integral number of clock memory location given by
cycles until it goes high.
2) When it goes high, the address on the address
TRAP-0024 H, RST 7.5-003CH, RST 6.5-0034 H & RST
d) It is used to synchronize slower peripheral to faster bus referring I/O device and when it goes low, the 5.5-002C H
microprocessor. address on the address bus referring memory. Among these interrupt TRAP is non-maskable interrupt
2) RST 7.5: 3) It is tristated during HOLD and HALT. which cannot be disabled while other four interrupts are
a) RESTART INTERRUPT: This signal is used to (b) TRAP: maskable, which can be disabled.
interrupt the microprocessor. 1) This signal is used to interrupt the Non-Vectored-Interrupt - Interrupt which does not
b) When an interrupt is recognized the next microprocessor. It has highest priority among transfer to specific memory location is called Non
instruction is executed from a fixed location in interrupts. Vectored Interrupt. INTR is non vectored interrupt
the memory i.e. 7.5x8=003CH 2) When an interrupt is recognized the next because it is only request taken by other device & does
instruction is executed from a fixed location in the not transfer control to any memory location. INTR has
c) It is maskable interrupt. lowest Priority.
d) They cause an internal restart to be memory Le. 0024 H.
automatically insert.
 5) Another new feature was the ability to work up to 1
Stack pointer (SP): Gbyte of virtual memory, and yet another feature was Question:
1) Stack pointer is a 16-bit register, which contains the added hardware multitasking. What is a Microcontroller? State three expanded
address of stack top. i.e. the memory address of last byte 6) Programs written for 8086 could run on 80286 when it features of 8052 over 8051 microcontroller
entered in stack. operated in real address mode. Answer:
2) With the help of incrementer/decrementer, the stack 1.Microcontroller: A microcontroller is a complete
pointer is decremented each time data is pushed onto 80386: microprocessor system, consisting of a microprocessor,
stack and incremented each time data is popped off the 1. The INTEL's 80386 is a 32-bit microprocessor limited amount of ROM, RAM, and parallel I/O ports, built
stack. introduced in 1985. on a single integrated circuit.
Instruction register and decoder: 2. 80386 is a logical extension of 80286. It is more highly 2. A microcontroller is, in fact, a microcomputer, but it is
1) During an instruction fetch, the first byte of the pipelined. called so because it is used to perform control functions.
instruction ie. the opcode is transferred to the 8-bit 3. The instruction set of 80386 is a superset of other 3.Expanded features of 8052 over the 8051
instruction register. members of the 8086 family. microcontroller are as follows:
2) The contents of instruction register are, in turn 4. It has a 32-bit data bus and a 32-bit nonmultiplexed - ROM:Microcontroller 8052 has 8 Kbytes of onboard
available to the instruction decoder. address bus. It can address a physical memory of ROM or EPROM, whereas 8051 has 4 Kbytes of ROM.
3) The output of decoder, gated by timing signals, \(2^{32}\), i.e., 4 GB. The 80386 memory management - RAM: Microcontroller 8052 has 256 bytes of onboard
controls the register, ALU and data/address buffers. allows it to address \(2^{40}\) or 64 TB. RAM, whereas 8051 has 128 bytes of RAM.
4) The output of decoder and internal clock generator 5. The 386 can be operated in one of the following - **Time-event Counter:** 8052 has an extra 16-bit time
produce the state and machine cycle timing signals. memory management modes: event counter, whereas 8051 has a dual 16-bit timer
Program counter (PC): i) Paged mode event counter.
1) The program counter is 16-bit register acting as a ii) Non-paged mode
pointer to next executable instruction. 6. When operated in paged mode, the 386 switches the Q.7 What are the advantages of computer
2) It always contains the 16-bit address of the memory paging unit after the segment unit. The paging unit allows networks? Distinguish between LAN and
location where next executable instruction is stored. memory pages of 4 KB each to be swapped in and out
3) The microprocessor uses this register to sequence the from disk. In non-paged mode, the memory management WAN? Ans.:
execution of instruction.
4) The PC is autoincremented after a particular
unit operates very similarly to the 286.
7. Virtual addresses are represented with selected
1. Computer network is an
instruction has been fetched by the MPU. components and an offset component, as they are with interconnected collection of
Temporary register: 80286.
1) The temporary register is used to store the data during autonomous computers or
execution of arithmetic or logic instructions.
2) This register is used internally and are not available to
80486
1. Intel's 80486 is a 32-bit microprocessor. It was
system of computers
the programmer. introduced in 1989. capable of sharing resources
Incrementer/Decrementer: 2. It has a 32-bit address bus and a 32-bit data bus.
1) Incrementer/Decrementer is a 16-bit special purpose 3. The 486 is basically a large integral circuit containing controlling services.
registers. a fast built-in math co-processor, a memory 2. The main advantages of computer
2) It is used to add or subtract one from the content of management unit (M.M.U.), and 8 Kbyte cache memory.
program counter or stack pointer. 4. 80486 has DX and SX versions. network are:
Register B (or C): 5. All 486 processors have a 32-bit data bus. The SX 1)Network provides resource sharing.
1) Register B (or C) is a general purpose 8-bit register version does not have an on-chip numeric co-processor. 2)It provides exchange of information and
along with register C (or B). 6. The 486 achieves its high-speed operation from its software.
2) It can also be used as a 16-bit register. The most faster clock-speeds, internal pipelined architecture, and 3)It provides high reliability by using other
significant 8-bits are stored in register B and the least the use of reduced instruction set computing (RISC) to machines if one machine fails in the network like
significant 8-bits are stored in register C. implement the microcode.
military banking, air and traffic control.
3) These are programmable means programmer can use 7. 486 also has 486 DX2 and 486 DX4 versions, with
them to load or transfer data. double and triple clock speeds. 4)Access to any file and data.
Serial I/O control: 5)Finally, the system saves money by using a
1) Most often I/O devices work with serial data in It looks like you've uploaded an image containing network.
transmission. information about the Pentium processor's main **The differences between WAN and LAN are
2) The 8085 has two pins to implement serial features. Here's the transcribed text for your reference: as follows:**
transmission SID (Serial Input Data) and SOD (Serial
Output Data).
3) The 8085 RIM instruction transfers data from SID to 1. **WAN (Wide Area Network):**
bit 7 of accumulator. Pentium or 80586: OR - WAN is the interconnection of LAN or MAN, and it can
4) A single serial bit may be output via SOD pin of 8085, Explain the main features of a Pentium processor. span a state, country, or even the world.
for is SIM instruction is used. 1) Pentium is a 64-bit microprocessor, introduced in - Data transfer rate is comparatively slower, such as in
Multiplexed Address/Data Bus Buffer: 1993. Kbits/sec.
(i) This is an 8-bit bidirectional buffer. 2) It has a 64-bit data bus and a 32-bit address bus. The - Links in WAN are typically established using
(ii) It is used to drive multiplexed address /data bus i.e. use of superscalar architecture incorporates a dual- telephone cables, microwave towers, or satellites.
low-order address bus (A7 –A0) and data bus (D7-D0). pipeline processor, enabling the Pentium to process - WAN experiences more short-circuit errors, noise
(ii) It is also used to tristate the multiplexed address/data more than one instruction per clock cycle. errors, and atmospheric errors compared to other
bus under certain conditions such as reset, hold, halt and 3) The addition of both data and code caches on-chip is networks.
when the bus is not in use. a feature designed to improve processing speed. - Example: A pager network.
(iv) The address/data buffers are used to drive external 4) A new advanced computing technique used in the 2. **LAN (Local Area Network):**
address and data buses respectively. Due to these Pentium is called branch prediction. The Pentium makes - LAN connects a group of computers within a small
buffers the address and data buses can be tri-stated an educated guess about the next instruction following a area, such as a room, building, or campus.
when they are not in use. conditional instruction. This prevents the instruction - Data transfer speed is comparatively higher, ranging
**Explain any two microprocessors in X-86 family in cache from running dry during conditional instructions. from thousand bits per second to 10 million bits per
brief.** 5) The Pentium has a 64-bit data bus, allowing it to second.
8086: perform data transfers with an external device twice as - Co-axial cables are commonly used to connect
1. Introduced by Intel in 1978, it's a 16-bit fast as a processor with a 32-bit data bus. computers and other devices.
microprocessor. - LAN has minimal short-circuit and noise errors due to
2. Designed as the CPU for microcomputer systems; its Q.Explain the advantages of the Pentium processor the short distance.
ALU and internal registers handle 16 binary bits at a time. with respect to the following features:** - Example: A computer lab in a college.
3. Features a 16-bit data bus and a 20-bit address bus, 1) Dual pipelining What is meant by protocol? Explain the
addressing up to 1 MB of memory. 2) On-chip caches concept of TCP/IP protocol.
4. Includes a multiplexed bus, with the least significant 8 3) Branch prediction Ans. :
bits of the address bus sharing lines with the data bus. 4) 64-bit data bus 1. A protocol is defined as an agreement between
5. Stores words in consecutive bytes; efficient single- Ans. : communication parties on how communication should
read operation depends on word alignment. 1) Dual pipelining: proceed.
6. Supports both multiplication and division operations. The use of superscalar architecture incorporates dual- 2. Protocols are rules by which computers
7. The 80186 is an enhanced version with integrated pipelining in the Pentium processor, allowing it to communicate, i.e., a protocol is a set of rules and
programmable peripheral devices and a superset process more than one instruction per clock cycle and procedures for sending and receiving data.
instruction set. achieve a high level of performance. 3. Internet protocols are called TCP/IP (Transmission
2) On-chip caches: Control Protocol/Internet Protocol) protocols. This
80286: The data and code on-chip caches improve the protocol does not belong to any one company, and the
processing speed of the Pentium processor. technology is available to everybody.
1) 80286 is a 16-bit microprocessor, introduced in 1982.
3) **Branch prediction**: 4. TCP/IP protocol uses three types of addresses for
This advanced version of 8086 is specially designed to
i) Branch prediction enables the Pentium processor to network addressing: a) Hardware or physical address
be used as a C.P.U. in multiuser/multitasking operating
make an educated guess about where the next is used by the data link and physical layers. b) Internet
systems.
Protocol (IP) address provides logical node
2) 80286 has a 16-bit data bus and a 24-bit address bus. instruction, following a conditional instruction, will be.
identification. This unique address is assigned by the
3) In 1984, IBM introduced PC/AT (Personal ii) This prevents the instruction cache from running dry
administrator and is expressed in four-part dotted
Computer/Advanced Technology) version of its PC using during a conditional instruction.
notation, e.g., 132.141.131.21.
80286. 4) 64-bit data bus: c) Logical node names are easier to remember than an
4) 286 had real and protected modes of operation. In real i) The Pentium processor features a 64-bit data bus, IP address.
mode, the processor could address only 1 Mbyte of which allows for higher speeds of data transfer.
memory, whereas in protected mode, it could address 16 ii) The data transfer speed of the Pentium processor is
Mbytes of memory. twice as fast as a processor with a 32-bit data bus.

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