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Digital Logic & Computer Organization

This document outlines the examination structure for the Digital Logic and Computer Organization course at Aditya Engineering College. It includes details on the format of the exam, with Section A consisting of 10 short answer questions and Section B requiring in-depth answers from various units. The document also specifies the topics covered in each unit, including number conversion, circuit design, memory hierarchy, and instruction formats.

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164 views2 pages

Digital Logic & Computer Organization

This document outlines the examination structure for the Digital Logic and Computer Organization course at Aditya Engineering College. It includes details on the format of the exam, with Section A consisting of 10 short answer questions and Section B requiring in-depth answers from various units. The document also specifies the topics covered in each unit, including number conversion, circuit design, memory hierarchy, and instruction formats.

Uploaded by

jahnavisindhu673
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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H.T.

No: Course Code: 231ES3T05

ADITYA ENGINEERING COLLEGE (A)


B.Tech - III Semester End Examinations (AR23)
DIGITAL LOGIC AND COMPUTER ORGANIZATION
(Common to CSE & IT)
Time: 3 hours Max. Marks: 70
1. Answer all 10 questions from Section-A. Each question carries 2 marks.
2. Answer one question from each unit in Section-B. Each question carries 10 marks.

SECTION –A 10 X 2 =20

1 a Convert the following numbers with the given radix to decimal. L2 CO1 [2M]
i) (143)8 ii) (1199)12
b Give truth tables of XOR and NOR logic gates? L2 CO1 [2M]
c Differentiate Combinational and Sequential circuits? L3 CO2 [2M]
d What is the functionality of a Bus in computer system? L2 CO2 [2M]
e What is an instruction cycle? L3 CO3 [2M]
f Give an example of signed addition and subtraction? L3 CO3 [2M]
g What is memory hierarchy? L2 CO4 [2M]
h Define Cache memory? L3 CO4 [2M]
i Explain the functionality of DMA? L2 CO5 [2M]
j Define Interrupt and give example? L3 CO5 [2M]

SECTION –B 5 X 10 =50

UNIT-I
2 a Convert the following numbers with the given radix to decimal. L2 CO1 [5M]
i) (21.95)8 ii) (4433)5 iii) (1199)12
b Minimize the given function F=∑(1,2,3,5,7,9,11,13) use K-map L3 CO1 [5M]
method
OR
3 a Design a 3 bit full adder? L3 CO1 [5M]
b What is the significance of a multiplexer? Design a 4*1 multiplexer? L3 CO1 [5M]

UNIT-II
4 a What is a shift register? Explain the modes of operations in a four bit L2 CO2 [5M]
shift register?
b Design the truth table, characteristic able and excitation table of SR L2 CO2 [5M]
Flip Flop and JK Flip Flop
OR
5 a Discuss the computer bus system. Discuss the basic computer L3 CO2 [5M]
instructions.
b Discuss Bus memory Transfer with multiplexer. L3 CO2 [5M]

(P.T.O)
UNIT-III
6 a Explain the flow chart of addition and subtraction of two binary L3 CO3 [5M]
numbers
b Explain the flow chart of Multiplication and Division of two binary L3 CO3 [5M]
numbers
OR
7 a What is instruction format? Discuss about the registers of basic L3 CO3 [5M]
computers.
b Explain Microinstruction format? L2 CO3 [5M]
UNIT-IV
8 a Discuss about the virtual memory? L3 CO4 [5M]
b Explain main memory and auxiliary memory. L3 CO4 [5M]
OR
9 a Discuss the concept of Cache memory? L2 CO4 [5M]
b Explain the significance of secondary memory devices? L2 CO4 [5M]
UNIT-V
10 a With a neat diagram discuss the concept of Direct memory access? L3 CO5 [5M]
b Discuss about parallel priority interrupt. L3 CO5 [5M]
OR
11 a Differentiate between Memory Mapped I/O and Isolated I/O. L2 CO5 [5M]
b Explain the Daisy Chaining priority with neat diagram L3 CO5 [5M]
****

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