GATE Computer Science & IT

BASIC
COMPUTER
ORGANIZATION
AND
ARCHITECTURE
Practice Questions
Booklet
ANALYSIS OF CSO IN GATE PAPER

Years Marks
2015 5
2016 8
2017 12
2018 10
2019 9
2020 10
2021 Set -1 8
2021 Set -2 9

CSO GATE SYLLABUS

 Number System: Octal, Hexadecimal and Decimal Representation,

Complements, l's Complement, 2's Complement, Fixed-Point Representation,
Floating-Point Representation, Binary Codes etc.
 Cache Memory: Associative Mapping, Direct Mapping, Set-Associative
Mapping and Writing into Cache etc.
 Instruction Sets: Addressing Modes and Formats: Three-Address Instructions,
Two -Address Instructions, One-Address Instructions and Zero-Address
Instructions, Data Transfer and Manipulation Instruction etc.
 Assembly Language: Rules of the Language, Translation to Binary etc.
 Instruction Pipelining: Ideal Instruction Pipeline, Data Dependency, Handling
of Branch Instructions etc.
 External Memory: Disk Structure and Disk Data transfer.
 Input-Output Organization: Input-Output Interface, Memory-Mapped I/O,
Modes of Transfer, Programmed Interrupt-Initiated I/O, Priority Interrupt,
Direct Memory Access (DMA), DMA Controller and DA Transfer etc.
 ALU, Data‐Path and Control Unit.

CSO GATE REFERENCE BOOKS

 Computer Organization by Carl Hamature

 Computer System and Architecture by M. Morris Mano
 Computer Organization and Architecture by William Stallings
 Computer Organization and Design by David A. Patterson and John L.
Hennessy

TABLE OF CONTENTS

S. No. CHAPTERS P. No.

1 NUMBER SYSTEM 1

14
2 CACHE ORANIZATION

32
3 INSTRUCTION SET ARCHITECTURE

44
4 INSTRUCTION PIPELINE

5 INPUT-OUTPUT AND CONTROL UNIT 62

 UNITS AND ABBREVIATIONS

 Units of File size (how big a file is on your computer) is usually measured in
units of "kilobytes", "megabytes", and "gigabytes." In this computing (binary, but
not data transfer) usage, 'K' (uppercase) represents a multiplier of 1,024,
„B’(uppercase) represent bytes and „b‟(lowercase) represent bits. Other
abbreviations use this same base of 1,024:
 1 KB (one KiloByte) = 1,024 Bytes (approximately 1 thousand Bytes)
 1 MB (one MegaByte) = 1,024 KB (approximately 1 million Bytes)
 1 GB (one GigaByte) = 1,024 MB (approximately 1 billion Bytes)
 1 TB (one TeraByte) = 1,024 GB (approximately 1 trillion Bytes)

 Units of Data transfer on the other hand is expressed in bits. In this computing
(data transfer) usage 'k' (lowercase) represents a multiplier of 1,000. In bit rates
the abbreviations are as follows:
 1 kbps = 1,000 bits per second
 1 Mbps = 1,000,000 bits per second.
 1 Gbps = 1,000,000,000 bits per second.

Where:-
kbps (kilobits/sec) means thousands of bits per second (where "thousand"= 103)
mbps or Mbps (megabits/sec) means millions of bits per second (where
"millions"= 106)
gbps or Gbps (gigabits/sec) means billions of bits per second (where "billion"=
109)
tbps (terabits/sec) means trillions of bits per second (where "trillions"= 1012)
pbps (petabits/sec) means quadrillions of bits per second (where "trillions"=
1015)

 Units of Time
 1 second = 103milliseconds (ms)
 1 second = 106microseconds (s)
 1 second = 109nanoseconds (ns)
 1 second = 1012picoseconds (ps)
 1 second = 1015femtoseconds (fs)
 1 milliseconds (ms) = 10-3seconds
 1 microseconds (s) = 10-6seconds
 1 nanoseconds (ns) = 10-9seconds
 1 picoseconds (ps) = 10-12seconds
 1 femtoseconds (fs) = 10-15second
 NUMBER SYSTEM
Q1. The binary representation of the hexadecimal number 3B7F is
(a) 0100 1001 1110 1101 (b) 0011 1011 0111 1111
(c) 0010 0100 0000 1010 (d) 0110 0011 1011 1100
Answers :(b)
Solution
(3B7F)16
(B) 0 0 1 1 1 0 1 10 1 1 11 1 1 1

3 B-(11)10 7 F=(15)10

Q2. The decimal representation of the binary number (10011010010)2 is _________

Answer :(1234)
Solution :
1024+64+128+16+2
= 1234

Q3. The binary representation of the decimal number (54321)10 is

(a) 11000001111000001 (b) 1101 0100 0011 0001
(c) 11000000111000001 (d) 10011100000011001
Answer :(b)
Solution :

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 1

Q4. The binary representation of the decimal number (654321.015625)10 is
(a) 10010001001000010.100100 (b) 00000010010001111.100001
(c) 10010001001000000.000001 (d) 1001 1111 1011 1111 0001. 000001
Answers :(d)

0.015625 *2 =0.03125 =0
0.03125*2 = 0.0625 =0
0.0625*2 = 0.125 =0
0.125*2 = 0.25 =0
0.25*2 = 0.5 = 0
0.5 *2 =1
1001 1111 1011 1111 0001. 000001
Q5. The hexadecimal representation of the decimal number (54321)10 is
(a)1011 (b) D431

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 2

 (c) 3023 (d) 3039
Answers :(d)
Solution: (54321)10 =(1101010000110001)2

(D431)16
Answer is B
Q6. The hexadecimal representation of the decimal number (654321.015625)10 is
(a)1C140.00 (b) 9FBF1.04
(c) 0E240.01 (d) 9FBF1.01

Answers: (b)
Solution:
In previous question no 4 we convert it in to binary.
1001 1111 1011 1111 0001. 000001

Q7. The octal representation of the hexadecimal number (A7C8)16 is

(a) (123456)8 (b) (123614)8
(c) (123710)8 (d) (1010011111001000)2
Answers : (c)
Solution:-

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 3

 (A7C8)16
it can be done in 2 ways :
hexadecimal Binary decimal octal
or. Hexadecimal binary  octal
23=8 3 bits of binary will group
To form an octal digit.
A 7 C 8 1010011111001 000
(A7C8)16 = (1 2 3 7 1 0)8

Q8. The octal representation of the decimal number (668)10 is

(a) (1234)8 (b) (2341)8
(c) (3412)8 (d) (4123)8
Answers :(a)
Solution:-
(668)10 divided by 8 continuously & the remainders

(1234)8
Answers :A
Q9. The octal representation of the decimal number (52345)10 is
(a) 12345 (b) 146 171
(c) 30071 (d) 17003
Answers :(b)
Solution:

Q10. The octal representation of the decimal number (561234.015625)10 is

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 4

 (a) 123456.11 (b) 2 110 122.10
(c) 113600.11 (d) 2 110 122.01
Answers :(d)
Solution:

0.015625 *8 = 0.125 =0
0.125*8=1
Q11. The octal representation of the hexadecimal number (ABCDE)16 is
(a) 2777565 (b) 2777650
(c) 6435210 (d) 2536336
Answers :(d)
(ABCDE)16firstconvert it to binary than make a pair of 3 bit to convert in octal.
10 101 011 110 011 011 110
2536336
Q12. The octal representation of the hexadecimal number (FEDCBA.AB)16 is
(a) 77556272.516 (b) 12345670.116
(c) 23451671.116 (d) 77556272.526
Answers :(d)
111111101101110010111010.101 010 11

Q13. The following numbers are represented in hexadecimal, octal, binary, and decimal,
respectively. Which answer specifies four unique integer numbers?
(a) 0x050, 062, 0z000101000, 50 (b) 0x050, 070, 0z001010000, 62
(c) 0x032, 062, 0z001100010, 62 (d) 0x062, 062, 0z010000010, 62
Answers :(d)
Solution:-
(a) 0x050=000001010000
062 =000110 010
50 =000110010
BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 5
 As 062 is same as (50)10, thus this option is wrong.
(b) 0x050=(000001010000)2=160
070=000111000
160
False because 0X050 =160 in decimal.
(c) 0x032=(00000011 0010)2=(50)10
062=(000 110 010)2=(50)10
False

(d) 062=000001100010=(98)10
062=000110010=(50)10
010000010=(130)10
All are unique correct option

Q14. Which of the following representation(s) is/are equivalent to 0z010101010101?

(a) (555)8 (b) (1365)10
(c) 0x555 (d) (1031)11
Answers :(b),(c)&(d)
Solution:-
(010101010101)2
0 1 01 0 10 1 01 0 1

(2 5 2 5 )8
0 1 0 10 1 0 10 1 0 1
(3 5 5)16
& 2 + 2 + 2 + 2 + 28 + 210
0 2 4 6

(1365)10
d)(1031)11
113*1+112*0+11*3+110*1
=(1365)10
b.c.d are true.
Q15. How many different values can be represented using four digits in the hexadecimal
system? _____
Answers:- (65536)
Solution:-
Each space of the 4 can be filled by 0-15 i.e 16 digits.
16x16x16x16 numbers can be represented using +hexadecimal digits 65536

Q16. The octal representation of the hexadecimal number (ABC.DEF)16 is____________

(Round off to two decimal places)
Answer: (5274.68)
Solution:-

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 (ABC.DEF)16()8
16(2)(8)
hexabinary octal
101 010 111 100.110111101111
23=8 group 3 bits
5274.6757
Round off to =5274.68
Q17. The base–3 representation of the base–81 number (74)(34)(3)(81) is___________________________
Answer: (2202 1021 0010)
Solution:-
(27 9 3 1) code when base is 3
Now represent (74)(34)(3) in base 3 in 4 digit because 81 = 34
74 = 2202 (27*2+9*2+3*0+1*2)
34 = 1021 (27*1+0*9+3*2+1*4)
3 = (0010)
= 2202 1021 0010
OR
( ) 81 ( ) 10 ()3
Base 81  Base 10  Base 3
(74)(34)(3)
812x 74+81x34+1x3
(488271)10

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 7

 2202102000100
Q18. What is decimal equivalent of (5477211)7 ?_____________________________________

Answer:(674787)
Solution:
(5477211)7()10
76x5+75x4+74x7+73x7+72x2+71x1+70x1=674787
Q19. The base–27 representation of the base–3 number (12211022)3 is___________________________
Answer :( 5M8)
Solution :
(12211022)3=( )27
33 =27
012 211 022 = (32 x 0 + 3 1+2 x 3 0)(32x2+3+30x1)(32x0+2x3+2x30)
=(0+3+2)(18+3+1)(0+16+2)
=(5)(22)(8)27
= 5M8
Q20. Find a digit d such that d1116 = 1d467.___________
Answer :( 2)
Solution :
216d+36+6+1=343+49d+28+6

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 216d-49d=343+28+6-36-6-1
167d=334
D=2
Q21. Solve the equation 1xx69 = 1x0105 for the missing digit. Then x=___________
Answer :( 3)
Solution :
729+81x+9x+6=625+125x+5
90x-125x=625+5-729-6
X=3
Q22. If (x876)16 = (114166)8 Then x = ________

Answer: 9
Solution:
(x876)16 = (114166)8
6  160 + 7  161 + 8  162 + x  163 =1  85 + 1  84 + 4  83 + 1  82 + 6  81 + 6 80
6 + 112 + 2048 + 4069x =32768 + 4096 + 2048 + 64 +48 +6
2166 + 4096x = 39030
4096n = 36864
x = 9.
Q23. If (7654)x+ (3210)x = (13064)x , where x > 0, then positive x is
(a) 5 (b) 6
(c) 8 (d) 9
Answer :(c)
Solution:
(7654) x + (3210) x + (3210) x = (13064) x
 x3 7 + x2 6 + x1 5 + x0 4 + x3 3 + 2  x2 + 1  x1 + 0  x0 = x4 1 + x3 3 + 0
 x2 + 6  x 1 + 4  x0
10x3 + 8x2 + 6x + 4 = x4 + 3x3 + 6x + 4
 10x3 – 3x3 – x4 + 8x2 = 0
 -x4 + 7x3+ 8x2 = 0
 x2 (-x2 + 7x + 8) = 0
So roots are 8, -1
Answer is 8.

Q24. If (555)10 = (x)5, then x = _____________

Answer : (4210)
Solution :

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 9

 4210
Q25. If (33332222)4 = (1x8702)9 ,then x = __________
Answer :(0)
Solution:
(3333 2222)4 = (1  8702)9
 3  47 + 3  46 + 3  45 + 3  44 + 2  43 +2  42 + 2  41 + 2  40 =
1  95 + x  94 + 8  93 + 7  92 +0  91 + 2  90
 49125 + 12288 + 3072 + 768 + 128 + 32 + 8 + 2 = 59049 + 6561x + 5832 + 567 + 0 + 2
 65423 = 65450 + 6561x
 -27 = 6561x
x0

Q26. What can be the possible value of x, if (33)x + (11)x = (110)x?______________

Answer: (4)

Solution:
(33)x+(11)x=(110)x
3×X0+3×X1+1×X0+1×X1=1×X2+1×X1 +0×X0
3+3X+1+X=X2+X
4X+4=X2+X
X2-3X-4=0
X2+X-4X-4=0
X(X+1)-4(X+1)=0
(X+1)(X-4)
X=-1
X=4
The possible value of x=4

Q27. If (753)x (in base-x number system) is equal to (384)y (in base-y number system), the
possible values of x and y are
(a) 7, 12 (b) 13, 9
(c) 8, 11 (d) 9, 13
Answer :( D)
Solution:
7x2 + 5x + 3 = 3y2 + 8y + 4
Now try by option
(a) It is not the possible base.

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 10

 (b) x = 13, y = 9
LHS RHS
= 7  132 + 5  13 + 3 3  92 + 8  9 + 4
= 7  132 + 5  13 + 3 3  92 + 8  9 + 4
= 1183 + 65 + 3 319
= 1251  319
( c) x = 8, y = 11
LHS RHS
7  82 + 5  8 + 3 3  112 + 8  11 + 4
448 + 40 + 3 363 + 88 + 4
491  455
(d) x = 9, y = 13
LHS RHS
7  92 + 5  9 + 3 3  132 + 8  13 + 4
567 + 45 + 3 507 + 104 + 4
615 = 615
Answer: x = 9, & y = 13

Q28. Consider the equation (43)x = (y3)8 where x and y are unknown. The number of possible
solutions is__________

Answer : (5)

Solution:

(43) x = (y3)8
4x + 3 = 8y + 3
4x = 8y
Where x > 4 & y < 8
Possible values are
x = 6, & y = 3
x = 8, y = 4
x = 10, y = 5
x = 12, y = 6
x = 14, y = 7
Answer: 5

Q29. Let X = (1100)7 and Y = (453)7 then what is the value of (X-Y)7is?_________
Answer :(314)
Solution:

Perform subtraction in base 7

0767
X = 1100
Y = 453
314

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 11

 Answer: 314

Q30. The roots of the quadratic equation "x2 - 11x + 22 = 0" are given by x = 3 and x = 6. What
is the base of the numbers? ___________
Answer :(8)

Solution:
x2 – 11x + 22 = 0
Given roots are
x = 3, & y = 6
Now sum of roots = -b /a
(11)𝑟
(3)r + (6)r =
1
3+6=r+1
r=8
Also product of roots = c/a
(22)𝑟
(3)r (6)r =
1
3  6 = 2r + 2
18 = 2r + 2
16 = 2r
Again r = 8
So the base is 8
Q31. The roots of the cubic equation x3 – 23x2 + 142x – 120= 0 are given by x = 1, x = 10 and x
=12. What is the minimum base of the numbers? ____________

Answer: 5
Solution
Use same concept of quadratic equation when you solve. It will be independent of
base now if ask for minimum base so answer will be 5 because (it can be greater than
equal to 5) the highest no is 4 in equation ''142x''.

Solution:
 = 1,  = 10,  = 12
Sum of root = -b/a

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 12

 (23)𝑟
(1)r + (10)r + (12)r =
1
1 + 1r + 1r + 2 = 2r + 3
It is independent of Base
(120)𝑟
(1)r . (10)r . (12)r =
1
(1). (1r). (1r + 2) = r2 + 2r + 0
r2 + 2r = r2 + 2r
It is Independent base
Similarly
Now
(1.10)r + (10  12)r + (12. 1)r = (142)r
r + (120)r + (12)r = (142)r
r + r2 + 2r + r + 2 = r2 + 4r + 2
Independent of base
Now when ask for minimum base.
It should be 5 at least because the largest no. is 4 in equation (142)r

Q32. For what value of b the equation is satisfied (1234)b + (5432)b = (6666)b
(a) 6 (b) 7
(c) 10 (d) Any value > 6

Answer : (d)
Solution
(1234)b + (5432)b = (6666)b
As we can see that
1+5 =6 , 2+4 =6, 3+3=6 , 4+2=6
So in any case with base greater than 6 this equation will be satisfied.
Answer: (d)
Q33. Convert the fractional decimal number 194.03125 to binary with a maximum of
six places to the right of the binary point.
(a) 01000010.00001 (b) 01000010.00001
(c) 11000011.10001 (d) 11000010.00001
Answer :( D)
Solution
194.03125

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 13

 11000010.00001 option (D)

Q34. What is the smallest unsigned number that can be represented using a sequence of 23
bits?
(a) 0 (b) –(222  1)
(c) 223  1 (d) 223  1
Answers :( A)
Solution
Range of n bit unsigned integer is
0 to 2n-1
Smallest unsigned integer is 0.

Q35. What is the largest unsigned number that can be represented using a sequence of 32
bits?
(a) -231 (b) 231  1
(c)  (232  1) (d) 232  1

Answers :(d)
Solution:
Range of n bit unsigned integer is
0 to 2n-1
n = 32 so the largest unsigned number is 232  1, all n bits are set to 1.
Q36. What is the smallest signed number (most negative) using a sequence of 32-bits that can
be represented in signed magnitude?
(a) -231 (b) – (231  1)
(c) 232  1 (d) 231  1
Answers :(b)
Solution:
The range of Sign-Magnitude form is from -(2(n-1)-1) to (2(n-1)-1)

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 14

Q37. What is the largest signed number (most positive) using a sequence of 32 bits that can be
represented in signed magnitude?
(a) -231 (b) –(231  1)
(c) 232  1 (d) 231  1
Answers :(d)
Solution:
The range of Sign-Magnitude form is from -(2(n-1)-1) to (2(n-1)-1)
Q38. What is the smallest signed number (most negative) using a sequence of 32 bits that can
be represented in one’s complement?
(a) -231 (b) –(231  1)
(c) 232  1 (d) 231  1
Answers :(b)
Solution:
The range of one’s complement number is from -(2(n-1)-1) to (2(n-1)-1)
Q39. What is the largest signed number (most positive) using a sequence of 32 bits that can be
represented in one’s complement?
(a) -231 (b) –(231  1)
(c) 232  1 (d) 231  1
Answers :(d)
Solution:
The range of one’s complement number is from -(2(n-1)-1) to (2(n-1)-1)
Q40. What is the smallest signed number (most negative) using a sequence of 32 bits that can
be represented in two’s complement?
(a) -231 (b) –(231  1)
(c) 232  1 (d) 231  1
Answers: (a)
Solution:
The range of 2’s complement form is from - (2(n-1)) to (2(n-1)-1).
Only the MSB is 1 rest all 0’s.
Q41. What is the largest signed number (most positive) using a sequence of 32 bits that can be
represented in two’s complement?
(a) -231 (b) –(231  1)
(c) 232  1 (d) 231  1
Answers :(d)
Solution:
The range of 2’s complement form is from -(2(n-1)) to (2(n-1)-1).
Only the MSB is 0 rest all 1’s.
Q42. Which one of the following is the 9-bit two's complement representation of the sign
magnitude number (010010001)sm.
(a) (011101111) 2’s (b) (000010001) 2’s
(c) (011101110) 2’s (d) (010010001)2’s

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 15

 Answer : (d)
Solution:
In the given number MSB is 0 so this is positive number which is represented as it is ,
negative number is represented in 2’s complement form.
Q43. Match the following 6-bit representations of -25 with the names of these
representations:
6-bit representations names of representations
1. 100111 i) one's complement
2. 111001 ii) biased with B=25
3. 110101 iii) signed magnitude
4. 100110 iv) two's complement
5. 000111 v) unknown
(a)1-iv, 2-iii,3-v,4-i,5-ii (b) 1-iv, 2-ii,3-v,4-i,5-iii
(c) 1-v, 2-ii,3-iv,4-i,5-iii (d)None of these
Answer: (a)
Solution
-25 in 1`s complements in 6 bits
100110
-25 in 2`s complement
100111
-25 in signed magnitude
111001
-25 biased with B =25=32
-25 +32 =7
(000111)2 in binary
1-iv, 2-iii,3-v,4-i,5-ii
Option a is correct.

Q44. Which of the following numbers is NOT -1 in the specified representation?

(a) 1111 1110 in 8-bit 1’s complement
(b) 1000 0001 in 8-bit biased representation with a bias of 128
(c) 1 01111111 00000000000000000000000 in 32-bit IEEE floating point format
(d) 1111 1111 in 8-bit 2’s complement
Answer :(b)
Solution
(a) 1111 1110
taking 1`s complement no .magnitude will be
0000 0001
And sign –ve
No=-1
(b) 1000 0001 8 bits biased representation with bias =128
129-128=1

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 16

 (c) 1 01111111 00000000000000000000000
1.00x20
Sign =-ve
(-1) in magnitude
(d) 1111 1111 in 2`s complement bits magnitude =(-1) .

Q45. Which of the following number is the 8-bit two’s complement representation for (-89)10?
(a) (10111101)2s
(b) (10111110)2s
(c) 010000102s
(d) none of the above
Answers :(d)
Solution
(-89)10=(64+16+8+1)

(-89)10=(64+16+8+1)
01011001
1`s comp 10100110
10100111
Q46. What will be the correct result when two 8-bit 2’s complement numbers 11001111 and
10001111 are added?
(a) 0101 1110 carry = 1, overflow = 0
(b) 0101 1110 carry = 0, overflow = 1
(c) 0101 1110 carry = 1, overflow = 1
(d) 0101 1110 carry = 0, overflow = 0
Answers :(c)
Solution

In 2`s complement addition, we drop the carry of msb

Both the numbers are negative
1 1 0 01111
1 0 0 01111
0 1 0 11110
Carry=1
In carry=0 and out carry=1 so it is overflow =1
Answer :(c)
Q47. Which of the following number is the 3-digit 6’s complement representation for (48)10?
(a) 4406s
(b) 4346s
(c) 4356s

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 (d) 4366s
Answers :(a)
Solution
(48)10
48 in base 6
6 48
6 8 -0
1 -2
(48)10=(120)6
6`s complement =5`s complement +1
5`s complement of a base 6 no
555
120
435
435
+ 1
(4 4 0)6 =6`s complement

Q48. What is the value represented by the 8-bit 2’s complement fixed point number
1101.10102s?
(a) 13.22510
(b) -2.312510
(c) -2.37510
(d)-3.312510
Answers :(c)
Solution
A fixed point number just means that there are a fixed number of digits after the
decimal point.
1101.10102s
(11011010)2s x2-4 =- (0 0 1 00 110)x2-4
-38x2-4
-2.375

Q49. Which of the following statements about 8-bit two’s complement is/are correct?
(a) The most significant bit has a weight of −26
(b) The representable range is −128 to +127
(c) The representable range is −127 to +128
(d) To calculate −x from x, we flip all the bits and add 1
Answers :(b&d)
Solution
(a)False ,MSB is used to determine the sign of the number
(b)True ,-128=1000000

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 18

 127=01111111
(c)False, it we have n-bit for 2`s complement representation. the numbers ranges from .
-2n-1 to +(2n-1-1)
(d)True
Answer:- (b& d)

Q50. When do we need to use sign extension?

(a) When we convert an n-bit 2’s complement value to the 1’s complement version.
(b) When we convert an n-bit 1’s complement value to the 2’s complement version.
(c) When we have an n-bit 2’s complement value and we want to use it as the same
value with fewer bits.
(d) When we have an n-bit 2’s complement value and we want to use it as the same
value with more bits.
Answer:- (d)
Solution :
When we have n bit 2`s complement value and we want to use it as same value with
more Bits ,as if we extend Msb with 1 more bit it is used as sign extension
If Msb =1 , number is negative Msb =0 , number is positive.
Q51. Consider the results of adding the following pairs of six-bit (i.e. one sign bit and five
data bits) two’s complement number. Which of the operation is/are cause overflow?

(a)

(b)

(c)
(d) None of the above
Answer: (b)
Solution

Q52. Consider the results of subtracting the following pair of six-bit (i.e. one sign bit and five
data bits) . Which of the operation is/are cause overflow?

(a)

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 (b)

(c)
(d) None of the above
Answer :(C)
Solution :

Ans Answer: (c)

Q53. The following two values
A = 11111111111111111111111010101 and B= 11111111111111001001111010101
are representations of 2's complement integers. Which one of the following is true?
(a) A is larger
(b) B is larger
(c) A and B are equal

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 (d) Can’t say anything, data insufficient
Answer : (a)
Solution
A = 1111111111111111111111111010101
- (00000000000000000000000101011)
=-43
B= 11111111111111001001111010101
000000000000110110000101011
=-27691
A is larger {as both are negative , the numbers with smaller magnitude is larger }

Q54. X is an 8-bit two’s complement number with value 10100010. What is the result of
operation X >> 2?
(a) 11101000 (b) 00101000
(c) 11010110 (d) 10101000
Answer :(a)
Solution :
11101000>>2 (right shift )
11101000

Q55. [MSQ]
Assume that
(i) A, B and C are 8-bit two’s complement numbers,
(ii) A = 11100001,
(iii) B = 01001001, and,
(iv) C = 00010010.
Which one of the following operations cannot causes an overflow?
(a) A >> 2 (b) A + B
(c) B <<1 (d) A + C
Answer: (a)(b)&(d)
Solution :
A= 111 00 0001
(A) A>>2
= 111 1 1 0 0 0 – no over flow
(B) A+B
11100001
01001001
1 0 0 1 0 1 0 1 0 no overflow

(C) B << 1
B=0 1 0 0 1 0 0 1
1 0 0 1 0 0 1 0 it will cause overflow

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 (D) A+C
11100001
0 0 0 10 0 1 0
1 1 1 1 0 0 1 1 no overflow

Q56. For the number -74 which option have the correct 8-bit binary values for all three
representations: 1's complement 2's complement and signed magnitude respectively?
(a) 1011 0110, 1011 0101, 1100 1010 (b) 1011 0101, 1011 0110, 1100 1010
(c) 1011 0101, 1011 0100, 1100 1010 (d) 1100 1010, 1011 0110, 1011 0101
Answer : (b)
Solution :
-74
1`s complement
74 is 01001010
-74 then we will reverse all the bits of 10110101 for 1`s complement ,-74 in 2’s
complement form is 1’s complement +1 i.e 10110110
For sign magnitude 11001010
Answer: (b)
Q57. [MSQ]
Which of the following statements about 8-bit two’s complement are correct?
(a) The largest positive number is 127 = 27 − 1.
(b) The least negative number is −127 = − (27 − 1).
(c) Adding 11111110 and 00000010 produces an overflow.
(d) Adding 01111110 and 00000010 produces an overflow.
Answer: (a)&(d)
S solution
Range of n bit 2`s complement no .is -2n-1 to 2n-1-1
Largest positive no .in 8 bit 2`sComplement =27-1
=127
(a) is correct
(b) least negative is -2n-1
=-27=-128
False
(c) Add 1 1 1 1 1 1 10
00000010
100000000
In carry =1 out carry =1
No over carry =1
No overflow
 false
(d) 0 1 1 1 1 1 1 0

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 00000010
10000000
In carry =1
Out carry=0
Overflow {as in carry  out array}

Q58. In which of the following coding schemes that 0111 represents the smallest value?
(a) The standard 4-bit Gray code (b) The BCD code
(c) The 84-2-1 code (d) The 2421 code
Answer: (c)
Solution
(a) 0 1 1 1 Gray
0 1 0 1  binary (5) 10 in decimal
(b) 0111 BCD
7 in decimal
(c) 0111  8 4 -2 -1
1 in decimal
(d) 0111 2421
Invalid in 2421

Q59. We have number 11001 in gray code then it’s decimal equivalent is:_______
Answer: (17)
Solution
Gray ( 1 1 0 0 1)(BCD)
1st gray to binary
11001
1 0 0 0 1  binary
17 in decimal

Q60. How many of following statement is/are correct?

S1: To convert a decimal integer to base 4 form, repeated multiplication by 4 is
used.
S2: In the Gray code sequence, two consecutive code values differ by one bit.
(a) only s1 (b) only s2
(c) both s1 & s2 (d) none of them
Answer :( b)
Solution :
To convert decimal integer to base 4
S1 : Repeated division by 4 is used not multiplication.
False
S2 : true property of gray code
 only S2 is correct
BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 23
Q61. Which of the following weighted decimal codes is not self-complementing?
(a) 2421 code (b) 3132 code
(c) 5211 code (d) 4421 code
Answer :-D
Solution
A self –complementing code have a property that its weights adds up to g.
2 + 4 + 2 + 1 =9
3+1+3+2=9
5 + 2 + 1 + 1 =9
4 + 4 + 2 +1=11 and 11 ≠ 9 therefore it is not self complementing code.
Q62. Which of the following is/are self-complementary code?
(a) 2421
(b) Excess-3
(c) 5211
(d) 84-21
Answer :(a),(b)&(c)
Solution :

Q63. If we add the following two decimal digits, 7+6, in excess-3 code what will be the sum.
(a) 0001 0000 (b) 0001 0011
(c) 0000 1011 (d) 0100 0110
Answer :(a)
Solution :
As 7+6=13
In excess 3= 1 1 0 1
+ 0011
1000
Option (A) is correct
Q64. Which of the following statements is/are true?
(a) The sign-and-magnitude scheme has two representations for zero.
(b) The BCD is a self-complementing code.
(c) To convert a decimal integer to base 4 forms, repeated multiplication by 4 is used.

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 (d) In the Gray code sequence, two consecutive code values differ by one bit.
Answer :(a, b, d)
Solution :
(i) is true in sign and magnitude scheme has two representation for zero .
(ii) BCD is a self complementary code = true
(iv) is also true.
Answer is (a,b, d)

Q65. Given the space of N bits, if the absolute magnitudes of the largest positive and negative
values that the space can represent are the same, the number system being used can be:
(a) 1's complement only
(b) 2's complement only
(c) sign-and-magnitude only
(d) Both (a) and (c)
Answer : (d)
Solution :
Because both 1’s complement and sign and magnitude has same representation.
Answer is D
Q66. What is the IEEE-754 32-bit floating point format representation of 16?
(a) 0 10000101 10000000000000000000000
(b) 0 00000100 00000000000000000000000
(c) 0 10000011 10000000000000000000000
(d) 0 10000011 00000000000000000000000
Answer : (d)
Solution :
(16)10=(10000)2
10000 = 1.0000x24
Exponent=4
Mantissa = all zeros ,
Exponent stored =4+127 (bias)
= 131
Sign bit =0
0 10 0 0 0 011 00000 00000000000000000 0
Sign bit exponent mantissa
Answer: (d)
Q67. Given the following hexadecimal form in the IEEE 754 single-precision floating-point
number representation: 0xC4EFC000. What decimal value does it represent? ________
(rounded off to three decimal places)
Answer :(-1918)
Solution :
C4EFC000
1 100 0100 1 110 1111 1100 0000 0000 0000
BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 25
 Exponent = 137 – 127
Actual Exponent = 10
So the no. will be
-1.110111111  2+10
-1110111111  2+10 2-9
-959  2
= -1918 is answer.

Q68. Given the following hexadecimal value in the IEEE 754 single-precision floating point
number representation: 0xC4127000. What decimal value does it represent? ________
(Round off to two decimal places)
Answer : (-585.75)
Solution :
C4EFC000
1 10001000 001 0010 0111 0000 0000 0000

Exponent = 136 – 127

Actual Exponent = 9
So the no. will be
-1.00100100111  29
-100100100111  29 2-11
-2343  2-2
= -585.75 is answer.
Q69. Given the following hexadecimal representation in IEEE 754 single-precision floating-
point number system: 0x42CE8000. What decimal value does it represent? _________
(Round off to two decimal places)
Answer :- (103.25)
Solution
0x42CE8000
0 10000101 1001110100000000000 0000
Sign – the exponent =133 -127
=6
Mantissa = 1.10011101
Numbers =1.10011101x26
110011101 x 26 x 2-8
413x2-2
103.25
Answer : (103.25)
Q70. Given the following binary value in the IEEE 754 single-precision floating-point number
representation: 0 10000111 11110100000000000000000. What decimal value does it
represent? _______ (Round off to two decimal places)
Answer :( 500)

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 Solution :
0 10000111 11110100000000000000000
Sign is +
Exponent =135 -127
=8
Mantissa = 1.111101
Numbers =1.111101x28 x2-6
110011101 x 22
125x22
500
Answer :500
Q71. Given the following binary value in the IEEE 754 single-precision floating-point number
representation: 1 10000011 01100010000000000000000. What decimal value does it
represent? __________(Round off to two decimal places)
Answer :( -22.12 to -22.13)
Solution :
1 10000011 01100010000000000000000
Sign is -
Exponent =131 -127
=4
Mantissa = 1.0110001 x24
Numbers =1. 0110001x24 x
- 110011101 x 2-3 x2-7
- 177 x2-3
- 22.125
-22.12 to -22.13
Answer
Q72. What is the hexadecimal representation of a decimal number -3.5 in IEEE-754 single-
precision floating-point system?
(a) 0xC0E00000
(b) 0xC0700000
(c) 0xC0600000
(d) 0xC0F00000
Answer : (c)
Solution
(-3.5)10 = -(11.1)2
11.1x20
1.11x21
Exponent =1
Mantissa=1100….0
Stored exponent =128
Sign bit =1

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 1 10000000 110 00000000000000000000
0xC0600000
Answer : (c)
Q73. What is the hexadecimal representation of a decimal number -75.35 in IEEE-754 single-
precision floating-point system?
(a) 0xC20F0000 (b) 0xC20E0000
(c) 0xC296B333 (d) 0xC10E0000
Answer : (c)
Solution :
Decimal no = -75.35
Binary representation= 1001011.01011001100110011

Stored exponent = 6+127 =133

Exponent in binary = 10000101

1.00101101011001100110011 * x26

1 10000101 001 0110 1011 0011 0011 0011

C296B333
Q74. What is the hexadecimal representation of a decimal number 52.21875 in IEEE-754
single-precision floating-point system?
(a) 0x40200000 (b) 0x41200000
(c) 0x42E87000 (d) 0x4250E000
Answer : (d)
Solution :
(52.21875)10 = (110100.00111)2
1.1010000111x25
Exponent =5+127 =132
Mantissa=1010000111
Stored exponent =
Sign bit =1
010000 100 101 0000 1110000000000000
0x4250E000
Answer : (d)
Q75. Assuming IEEE single-precision floating point numbers (with an 8-bit exponent), Which
of the following has the greatest value?
(a) 0x00000000 (b) 0x00000001
(c) 0x50000000 (d) 0xC0000000
Answer : (c)
Solution :
(a) 0x00000000

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 =0
(d) 0xC0000000
As its sign bit is 1 , no is –ve therefore its not largest .
It represent-2.0
(b) 0x00000001
000000000 00000000000000000000001
All exponent bits are 0 and mantissa bit not all 0  it is denormalized no .
(-1)0x0.0000000- - - - -001x2-126

(c) 0x50000000
01010000 0000 0000 0000000000000000
1.0x233
It is the largest numbers
Option C is correct
Answer: C
Q76. Given the following hexadecimal representation in IEEE 754 single-precision floating-
point number system: 0x4305C000. What decimal value does it represent?
(a) 5.75 (b) 66.875
(c) 133.75 (d) 267.5
Answer:- (c)
Solution
0x4305C0000
01000011000001011100
Exponent =10000110
=134
1.000010111x2134-127
1.000010111x27
10000101.11
133.75
As sign bit =0
No is +ve
No is 133.75

Q77. Computer A uses the following 32-bit floating-point representation of real numbers:

Computer B uses the following floating point representation scheme:

Which of the following statements is true with regard to Computer B’s method of
representing floating-point numbers over Computer A’s method?
(a) both the range and precision are increased

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 (b) the range is increased but the precision is decreased
(c) the range is decreased but the precision is increased
(d) both the range and precision are decreased
Answer :( b)
Solution :
A uses 7 bits for exponent
B uses 8 bits for exponent
A uses 24 bits for mantissa
B uses 23 bits for mantissa
Increasing the size of exponent increases the range of numbers that can be represented.
Also decreasing the size of mantissa decreases the precession of a number that can be
represented.
Answer: (b)
Q78. For a 7-bit normalized floating-point format: (-1)S×(1.FFFF)×(2EE) where FFFF is unsigned
and EE is two’s complement, what is the smallest positive value you can represent just after
0?
(a) 0.5 (b) 0.25
(c) 0.125 (d) 0.28125
Answer : (b)
Solution :
EE means exponent is in 2 bit .In 2 bit 2`s complement range is -22-1 to (22-1-1)
i.e -2 to 1
smallest positive value will have
0 10 0 0 0 0
1.0 x2-2=1/4=0.25
0.25
Answer: (0.25)
For next three questions consider a floating-point representation with a sign bit in the
leftmost position, followed by a three-bit base 4 exponent and represented as 1’s complement,
followed by a normalized six-bit fraction. Zero is represented by the bit pattern 0 000 000000
Q79. What decimal number is represented by the bit pattern: 1 110 010000? _________
Answer : (-0.3125)
Solution :
1 110 010000
Exponent = 110 in 1 ‘s complement form it represent -1
1.01 x4-1
101 x4-1 x 2-2
5/16 = - 0.3125
Q80. What is the bit pattern (in decimal) for the smallest non-zero positive representable
number? ______
Answer : (0.015625)

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 Solution :
Sign bit =0
Exponent smallest value represented in 1`s complement = 100=-3
In 3 bit 1`s complement =100-3
In 3-bit 1`s complement range is –(23-1-1) to +(23-1 -1)
-3 to 3
And mantissa will all zeros 1.000000x4-3
1x2-6
1/64=0.015625
Q81. What is the bit pattern for the largest positive representable number? ________
Answer :0 011 111111
Solution :
The largest positive representable number will be
0 011 111111
1.111111* 43
1111111* 26*2-5
63*2 = 126
Q82. Consider a hypothetical 10-bit similar to IEEE floating point representation including all
special cases. There is a sign bit in the most significant bit. The next five bits are the
two’s complement exponent. The last 4 bits is the normalized fraction. What is the
floating-point representation for 0.125?
(a) 0x130 (b) 0x230
(c)0x1D0 (d)0x103
Answer : (c)
Solution :
(0.125)10=(.001)2
=1.0x2-3
Exponent =(-3)2=-(00011)2
=1.0x2-3
Exponent =(-3)2=-( 00011)2
=(11101)2`s
0 11101 0000
1 D 0
0x1D0
Q83. Express the floating-point number 1.63 in binary notation using 1-bit sign, 3-bit
exponent in excess-4 notation (100 stands for 0), and 4-bit un normalized mantissa in the
same order.
(a) 0x5D (b) 0x6B
(c) 0x55 (d) 0x2A
Answer : (a)
Solution :
(1.63)10

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 0.63x2=1.26
0.26x2=.52
0.52x2=1.04
0.4x2=0.8
The numbers in binary :-1.1010
The number is unnormalized representation
0.1101x21
Exponent is in excess -4
Stored exponent :- 1+4
(5)10= (101)2
0 101 1101

5 D
0X5D
Answer :(a)

For next four question, suppose a designer create a variant similar to an IEEE floating point
number that uses 1 bit for sign, 7 bits for biased exponent and 8 bits for mantissa. It has all the
properties of IEEE 754 (e.g., 0, , NAN, Denormalized number) just with different ranges,
precision & representations
Q84. What is the biasing value in this representation? ___________________________
Answer : (63 )
Solution :
Bias will be 26-1=63
Q85. What is the largest number smaller than +∞ (in decimal)? ___ _______________
Answer :7EFF
Solution :
0111 1110 1111 1111
1.111 111 1 1 x2 126-63
111111111x2-8 x2 126-63
(29-1)x255
The largest no is hex =7EFF
Q86. What is the smallest positive normalized number (closest to 0 in HEX)?___________
Answer : (0100)
Solution :
0000 00010000 0000
1.0 0 0 0 0 0 0 0 X21-63
2-62
In hex : 0 1 0 0

Q87. [MSQ]
Which of the following is not the floating point representation of decimal number

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 -0.1325 using the design above in hexadecimal is?
(a) BC80 (b) CC40
(c) BB31 (d) None of these
Answer : (a, b, c)
Solution :
(-0.1325)10=(.001000011110)
Mantissa=1.00001111x2-3
Exponent =-3+63=60
=0111100
1 0 111100 0000 1111 BC0F
Answer: (a, b, c)

For the next five questions, Consider the following 16-bit floating point representation
similar to IEEE floating point format. There is a sign bit in the most significant bit to represent
sign of the number. The next five bits are the exponent. The exponent stored in Excess – 15
notations. The last ten bits are the mantissa. The mantissa stored in sign-magnitude
representation. The rules are like those in the IEEE standard (normalized, denormalized,
representation of 0, infinity, and NAN)
Q88. What is the smallest positive normal number greater than zero in decimal?
0 1023
(a) 2−14 × (1 + ) (b) 2−14 × (0 + )
1024 1024
1 1023
(c) 2−14 × (0 + ) (d) 215 × (1 + )
1024 1024
Answer : (a)
Solution:
For smallest positive no sign bit= 0 next 5 bit exponent should be minimum = 00001
and mantissa should be all o's i.e 0000000000 so the smallest positive value greater
than 0 will be 2^(stored-biasing) *1.0 =2^(1-15)*1 = 2^-14*1 which is equal to option
a.

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 33

Q89. What is the largest positive normal number greater than zero in decimal?
0 1023
(a) 2−14 × (1 + ) (b) 2−14 × (0 + )
1024 1024
1 1023
(c) 2−14 × (0 + ) (d) 215 × (1 + )
1024 1024

Answer: (d)
Solution:
0 11110 1111111111
Actual exponent = stored – biasing
= 30-15
= 15
1.1111111111 *2 15

11111111111 * 215 * 2-10

Which is equal to option (d)

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 34

Q90. What is the smallest positive subnormal number greater than zero in decimal?
0 1023
(a) 2−14 × (1 + ) (b) 2−14 × (0 + )
1024 1024
1 1023
(c) 2−14 × (0 + ) (d) 215 × (1 + )
1024 1024
Answer: (c)
Solution
Subnormal mean denormalized number represented as 0.f × 2^(−b+1) .Here we have
biasing value of b=15. 0 | 00000| 0000000001 this is the smallest denormalized
number. 0.000000001 * 2^(-15+1) = 2^(−14)× (0+ 1 / 1024) Answer C

Q91. What is the largest positive subnormal number greater than zero in decimal?

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 35

 0 1023
(a) 2−14 × (1 + ) (b) 2−14 × (0 + )
1024 1024
1 1023
(c) 2−14 × (0 + ) (d) 215 × (1 + )
1024 1024
Answer: (b)
Solution:

Q92. What is the largest positive normal number less than one in above floating-point
representation?
(a) 0x3BFF (b) 0x3C00
(c) 0x3C01 (d) 0x3555

Answer: (a)
Solution:
0 01110 1111111111
214-15 = 2-1
1.1111111111 *2-1
11111111111 *2-1*2-10
(211 -1)/211
= 0.99951 This is largest number less than one.

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 36

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 37
 CACHE ORANIZATION

For next two questions consider a direct mapped cache having 8 cache lines. Each
cache line consists of 2 words, and each word is one byte. The address bus consists
of 7 bits.
Q1. Which one of the following statements is correct?
(a) The index field consists of 2 bits.
(b) The index field consists of 1 bit.
(c) The tag field of the cache consists of 3 bits.
(d) The tag field of the cache consists of 2 bits.

Answer: (c)
Solution:
8 cache lines =23 cache lines
 3 bits for index
As 1 line =2 words =2 bytes
 1 bit for offset
Address size =7 bits
7
Tag Index Offset
Tag bits =7 – 3 – 1=3 bits

Q2. Which one of the following statements is correct?

(a) The total number of bytes for storing data in the cache is 16 bytes.
(b) The total number of bytes for storing data in the cache is 32 bytes.
(c) The total number of bytes for storing data in the cache is 8 bytes.
(d) The total number of bytes for storing data in the cache is 8K bytes

Answer: (a)
Solution:
Cache address is divided into two parts offset +index (line) in case of direct
mapped
1+3=4 bits
Cache size = 24=16 bytes

Q3. Assume a 2-way set-associative word addressable cache is being used in a

system with a 24-bit address using an 8-word block size. How many sets are
there if the cache has 1024 lines, i.e., 8K words? ______

Answer: (512)
Solution:
If the cache has 1024 lines and the chance is 2-ways set associative, then each
set have line. Total numbers of sets =1024/2=512
For the next three questions, consider 32-bit byte addressable physical memory

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and 2 MB cache with blocks of size 8KB each:
Q4. How many bits in the tag, index and offset fields of the cache address
respectively if the cache is direct mapped?
(a) 19, 6, 13 (b) 19, 0, 13
(c) 11, 8, 13 (d) 11,8,12

Answer: (c)
Solution:
𝑐𝑎𝑐 𝑕𝑒 𝑠𝑖𝑧𝑒
Number of line in cache =
𝑏𝑙𝑜𝑐𝑘 𝑠𝑖𝑧𝑒
2∗220
=
8∗ 210
221
= = 28
213
So 8 bit are required for index
Block size = 23* 210 = 213
13 bit are required for offset
tag=PA- (index +offset)
tag =32 -8-13=11
Answer is C
Q5. How many bits in the tag, index and offset fields of the cache address
respectively if the cache is 4 -way set-associative?
(a) 13, 6, 13 (b) 19, 0, 13
(c) 11, 8, 13 (d) 11,8,12

Answer: (a)
Solution:
𝑐𝑎𝑐 𝑕𝑒 𝑠𝑖𝑧𝑒
Number of line in cache=
𝑏𝑙𝑜𝑐𝑘 𝑠𝑖𝑧𝑒
2∗220
= = 28
8∗ 210
28
Number of set-incache =
way of associtvity
28
= = 26
22
So 6 bit are required for index
Block size = 213, means 13 bit are required for offset
tag =32-6-13 =13
Answer is A
Q6. How many bits in the tag, index and offset fields of the cache address
respectively if the cache is full associative?
(a) 13, 6, 13 (b) 19, 0, 13
(c) 11, 8, 13 (d) 11,8,12

Answer: (b)
Solution:
In fully associative cache no bit for index

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 39

 Block size = 213, 13 bit for offset
tag = 32- 13 =19 bit
Answer is B
For next two questions, consider a 2-way set-associative cache with following
specification:
 word size: 32 bits
 cache block size: 2048 bits
 physical address size: 32 bits
 Number of blocks in cache: 2048
 memory is word addressable
Q7. How many bits are used for tag, index and offset if memory is word addressable?
(a) 13, 11, 8 (b) 14, 10, 6
(c) 16, 10 and 6 (d) 10, 11, 11

Answer: (c)
Solution:
Word size = 32 bits = 4 bytes
Number of block in cache =2048= 211
211
Number of set = = 210
2
So 10 bit is required for set
Memory is word addressable, so PA is 32 bit means 232 words stored in it
Cache block size = 2048 bit = 256 byte
256
Cache block size (In word) = = 64 word
4
So 6 bit is require for offset
tag = 32 -10-6=32-16 =16
Answer is C
Q8. How many bits are used for tag, index and offset if memory is byte addressable?
(a) 13, 11, 8 (b) 14, 10, 8
(c) 16, 10 and 6 (d) 10, 11, 11

Answer: (b)
Solution:
Number of block
Number of set =
set associativity
2048
= = 1024 =210
2
10 bit are required for index
2048
Cache block size = = 256 byte
8
Means 8 bit are required for offset.
Tag =32-10-8 =14
Answer is B
For next two questions consider two different cache configurations for an 8-bit
processor. Both caches have two 16-byte blocks (for a total capacity of 32 bytes), but

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 40

one is direct-mapped and the other is two-way set associative.
Q9. For the direct-mapped cache, how many bits are in the tag, index, and offset
respectively?
(a) 5,1,1 (b) 3,1,4
(c) 2,2,4 (d) 4,1,2

Answer: (b)
Solution:
2 lines = 1 bits for index {direct mapped}
1 line =16 bytes =24 bytes
 4bits for offset
Address size =8 bits
Tag size =8-(4+1)=3
Bits for tag index offset are 3, 1, 4 respectively

Q10. For the two-way set associative cache, how many bits are in the tag, index, and
offset?
(a) 3,1,4 (b) 4,0,4
(c) 5,0,3 (d) 2,2,4

Answer: (b)
Solution:
As 2 way set associative and there are 2 lines
 Set index bit =0
Offset =4 bits {24bytes =line size}
Tag =8- (0+4) =4 bits
=4 bits
As address size 8 bits.
For next two questions consider a direct-mapped cache design with a 32-bit
address and byte-addressable memory, the following bits of the address are used to
access the cache (Assume word size is 32 bit)
Tag Index Offset
31-10 9-5 4-0
Q11. What is the size of cache line in words? _______

Answer: (8)
Solution:
Offset bits are from 0 to 4.
5 bits are there
32 bytes line size
1 word =4 bytes {as word size 32 bits}
 No of word =32/4 =8 words
Size of 1 line is 8 words.

Q12. How many lines does the cache have? ______

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 Answer: (32)
Solution:
As index bits are form 5-9
Means 5 bits for index
 25 lines will be there
32 lines in cache.

For next two questions, consider the 16 Kbyte cache with following specification:
 Each block will hold 32 bytes of data (not including tag, valid bit, etc.)
 The cache would be 2-way set associative
 Physical addresses are 32 bits
 Data is addressed to the word and words are 32 bits long
Q13.How many blocks would be in this cache? __________

Answer: (512)
Solution:
Cache size = 214 bytes
Block size =25 bytes
Word size =32/8 bits =22 bytes
No. of words in a cache line =23 words
 3 bits for offset
No. of lines = cache size /block size = 214/25=29 =512

Q14.How many bits of tag are stored with each block entry? _____

Answer: (21)
Solution:
Refer to solution of question 13
Offset =3 bits
As 29 lines in cache and cache is 2 ways set associative
28 sets = 8 bits for index
Tag bits = PA-(index +offset)
=32-(8+3)
=21 bits

Q15.Consider a byte-addressable 4-way set associative cache with a full data

capacity of 8192 bytes. Each cache block consists of 4 words, and each word is
4 bytes long. The number of bits in the set-index field and the number of bits in
the offset field of the memory address is
(a) Set-index = 4 bits; Offset = 2 bits
(b)Set-index = 6 bits; Offset = 2 bits
(c)Set-index = 6 bits; Offset = 4 bits
(d)Set-index = 7 bits; Offset = 4 bits

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 Answer: (d)
Solution:
As 1 line = 4 words, each word =4 bytes
Line size =16 bytes
4 bits for offset
Cache size =8192 bytes
=213 bytes
No.of lines = cache size /block size = 213/24= 29 liens
As cache is 4 ways set associative
No.of sets = 29/22=27 sets
7 bits for set index.

Q16. Consider a cache with a size of 256 bytes and a block size of 16 bytes. In which
cache index (in decimal) the memory address 28E716 is mapped if cache is direct
mapped cache and if cache is a 2-way set-associative cache respectively?
(a) 7 and 15 (b) 15 and 7
(c) 14 and 6 (d) 14 and 7

Answer: (c)
Solution:
256 28
Number of lines in cache = = =24
16 24
4 bit is required for index
and block size = 16 byte = 24, 4 bit is required for offset
PA= 16 bit
tag = 16-4-4=8
PA= 0010 1000 1110 0111
So, it maps on line 14
In set associative cache
24
Number of sets = = 23 = 3 bit is required
2
So, tag PA- set- 4
= 16 -3-4=9

Answer is C
Q17. Assume a 2-way set-associative word addressable cache with 1024 lines is being
used in a system with a 24-bit address using an 8-word block size. If a block
containing the address (7BE453)16 is stored in the cache, what would the tag be?
(a) 0x7BE (b) 0x3DF
(c) 0x7BE4 (d) data insufficient

Answer: (a)
Solution:
Numbers of sets =512 which can be represented in 9 bits
BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 43
 block size is 8 words, therefore offset =3 bits
(7BE453)16= 0 1 1 1 1 0 1 1 1 1 1 0 | 0 1 0 0 0 1 0 1 0 | 0 1 1
Tag Set index Offset
Q18.Given a 16-KB two-way associative cache with 32-byte cache lines and a 64-bit
address space there will be x bits used for the index. If that same cache were
fully-associative you‟d need y bits to be used for the index. Then x* y =__________

Answer: (0)
Solution:
As index bits in fully associative =0=y
Cache size =214 bytes
Line size = 25 bytes
Lines = 214/25 =29 lines
2 way set associative cache.
= 28 sets
8 bits for index =x
x*y=8 * 0=0

Q19.Consider the processors have a 256kB 16-way set associative L2 cache with a
64-byte cache line size. How many cache lines will be there?
(a) 2048 (b) 512
(c) 256 (d) 4096

Answer: (d)
Solution:
Cache size =256x210 bytes
Cache line size -2 6 bytes
No of lines =(256*210)/26=212=4096 lines

Q20.Consider system:
 A processor has a direct mapped cache
 Data words are 8 bits long (i.e., 1 byte)
 Data addresses are to the word
 A physical address is 20 bits long
 The tag is 11 bits
 Each block holds 16 bytes of data
How many blocks are in this cache? ___________

Answer: (0)
Solution:
Block size =16 bytes
then offset =4 bits
index = physical address –tag –offset
20-11-4 =5 bits

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 Total numbers of block will be 32 .(25)
Q21. Assume you have a 2-way set associative cache.
 Words are 4 bytes
 Addresses are to the byte
 Each block holds 512 bytes
 There are 1024 blocks in the cache
If you reference a 32-bit physical address – and the cache is initially empty –how
many data words are brought into the cache with this reference?__________

Answer: (128)
Solution:
1 line = 29 bytes
1 word =22bytes
No.of words = 29/22 = 27 words
With 1 cache reference 1-line can be brought .and in 1 line, 27 words will
bethere
Q22. Consider a cache with 32-bit addresses, 768 blocks, and a block size of 128
bytes. Tags are 17 bits. How many sets are there, and what is the associatively
of the cache?
(a) 128 sets, 6-way set associatively. (b) 256 sets, 3-way set associatively.
(c) 128 sets, 8-way set associatively. (d) Data inadequate

Answer: (b)
Solution:
Tag =17 bits
Block size=27 bytes
7 bits for offset
Index bits =32-(17+7)=8
28 sets =256 sets
Total 768 block 768/256 =3 way set associative.

Q23. An 8-way set-associative cache memory allows a maximum of 256 different MM

blocks to map to the same cache set. A block is 8-byte long. The MM is 16 MB.
What are the sizes (in bits) of the tag, set and byte fields, respectively?
(a) 9, 13, and 2. (b) 17, 3, and 3.
(c) 18, 3, and 3 (d) 8, 13, and 3

Answer: (d)
Solution:
Block size =8 byte =23B
3 bits for offset
As 256 mm block mapped to 1 same cache set means tag bits =8
P.A =24 bits index =24-(8+3)=13 bits
Q24. Which of the following accurately computes the set index for a cache with 8-byte
blocks and 32 sets?(Assume I being physical address)

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 (a) INDEX = (I /8) % 32;
(b)INDEX = (I » 3) & 31;
(c) INDEX = (I & 0XF8) /8;
(d) All of the above

Answer: (d)
Solution:
(a) (I /8) % 32 from divide by 8 bits shift toward right by 3 bits and mod 32 gives
set index.
(b) I » 3, I right shift 3, shift 3 bits to right and do ANDing with 31, as set index
bits are of 5bitswill give you index bits.
(c) ANDing with 0xF8 give last 8 bits and divide by 8, shift those 3 bits forward
right, remaining is set index bits.Let say our PA = 0000 0000 1000 0000
0001 1000 and ANDing with 0x0000F8 give last 8-bits which is 0001 1000
and divide by 8, that is shift those 3 bits forward right, remaining is set index
bits which is 00011.
For the next seven questions, consider the direct mapped cache organization of a
computer shown below. Computer uses 32-bit data words and 32-bit word
addresses.

Q25.What are the maximum number words of data from main memory that can be
stored in the cache at any one time?
(a) 4 (b)8 (c) 16 (d)32

Answer:(none)
Solution:
Maximum number words of data from main memory that can be stored in the
cache at any one time = 16 * 4 words = 64
Q26. How many bits of the address are used to select which line of the cache
isaccessed?
(a) 4 (b)8 (c)16 (d)32
BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 46
 Answer: (a)
Solution:
As there are 16 lines {Row -0 to Row 15)
4 bits are required to select line of cache that is accessed.
Q27. How many bits wide is the tag field?
(a) 24 (b) 28 (c) 26 (d) 25

Answer: (c)
Solution:
As line size = 4 words,as memory is word addressable
2 bits required for offset
4 bits for index
Tag = PA-(index +offset)
= 32-(4+ 2)
= 26 bits
Q28. Assume that memory location 0x0002045C was present in the cache. Using the
row and column labels from the figure, in what cache line could we find the
data from that memory location?
(a) 4 (b) 5 (c) 6 (d) 7

Answer:(d)
Solution:
Tag Index Offset
26 4 2

0x0002045C
00 000000000000100000010001 | 0111 |00
Line No: 7
Q29.What would the value of the tag field have to be for the cache row in which the
above data appears?
(a) 0x000204 (b) 0x00020 (c) 0x0002045 (d) 0x00204

Answer: (None)
Solution:
Tag = 0x0000811
Refer solution of question 28
Q30. When an access causes a cache miss, how many bytes need to be fetched from
memory to fill the appropriate cache location(s) and satisfy the request?
(a) 4 (b)8 (c) 16 (d)32

Answer: (c)
Solution:
When a cache misses a line brought form main memory or we can say that a

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 47

 lineis fetched from main memory.
As 1 line =16 bytes
 16 bytes will be fetched
For next four questions consider a 64 KB, 2-way set-associative cache with 32-
Bytes blocks in a 32-bit byte addressable system, in which a byte address is of the
form b31, b30, …, b1, b0
Q31. What is the total number of cache blocks in the cache?
(a) 2 K blocks (b) 4 K blocks (c) 512 blocks (d) 1 K blocks

Answer: (a)
Solution:
as there are 5 bits for offset
cache size =2^16
#lines=2^16/2^5
=2^11
=2K blocks
Answer is A
Q32. Identify the address bits that are used for indexing a block in the cache
(a) b15, b14, … , b6, b5 (11 bits)
(b) b13, b12, … , b5, b4 (10 bits)
(c) b14, b13, … , b5, b4 (11 bits)
(d) b14, b13, … , b6, b5 (10 bits)

Answer: (d)
Solution:
0 to 4 bits are for offset
now for index
there are 2K lines
and cache is 2 way set associative
thus 10 bits are used for index.
from b5 to b14 bits are used for index
Answer is D
Q33. Identify the address bits that are used as a tag for a block in the cache
(a) b31, b30, … , b17, b16 (16 bits)
(b) b31, b30, … , b15, b14 (18 bits)
(c) b31, b30, … , b16, b15 (17 bits)
(d) b30, b29, … , b16, b15 (16 bits)

Answer: (c)
Solution:
As 5 bits for offset (b0,--------b4)
10 bits for index (b5-------- b14)
17 bits for tag (b15-------- b31)

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Q34. What is the total number of bits used as tags for all the blocks in the cache?
(a)136 K bits (b) 68 K bits
(c) 17 K bits (d) 34 K bits

Answer: (d)
Solution:
from the above questions solution, we know that
index bits=10
offset bits=5
tag bits =32-10-5
=17 bits.
there are 2K lines
thus, per line
2K x 17 bits are used for tag
=34K bits
Q35. How many possible locations are there for storing the address 0x45E4 in a 64KB
4 -way set-associative write back cache with 32-byte cache lines?
(a) 1 (b) 4
(c) 16 (d) 2048

Answer:B
Solution
In a 4-way set associative cache each memory block can be mapped to 4
lines,that use in the same set
Q36. Consider a 256-byte, direct mapped cache that uses 13 bits for tag and 2 bits for
block offset. Given that memory is byte addressable, what is the maximum
number of megabytes that memory can hold? ____________

Answer: (2)
Solution:
Cache size =28 B
13 bits =tag
2 bits =offset
P.A size =13+8=21 bits =2 MB.

Q37. Suppose you have a word-addressed memory hierarchy system with the
following parameters:
 Block size = 16 words
 Main memory size = 64 blocks
 Cache size = 8 blocks
Suppose your cache is set-associative with 4 sets (i.e., 2 cache blocks per set).
The tag values in the cache are:

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 49

 Accessing which of the following memory addresses: (1) 0x37A and (2)0x22C
results in cache hit?
(a) Only (1) will result in cache hit
(b) Only (2) will result in cache hit
(c) Both will result in cache hit
(d) Both will result in cache miss

Answer: (c)
Solution:
(1) 0x37A
Offset =4 bits (24 words)
Set index =2 bits (4 sets)
0 0 1 1 0 1 1 11 0 1 0

Set offset
We will mater tag of set 3 with 00 1101 to find weather it is a hit or a miss it
matches with line 2 of set 3,
It is a hit.
(2) (22C)16 = 0 0 1 0 0 0 1 0 1 1 0 0

Set
tag matches with set 2 line 2 therefore it is a hit .
Q38. A byte‐addressable machine with 32‐bit memory addresses has a cache with the

following properties:
 16byte cache blocks
 8KB of data in the cache
 Direct mapped
 Write through
 1 valid bit/block
How many bits of metadata are required for each cache entry? ___

Answer: (20)
Solution:
Metadata includes: (tag +1 valid bit )per block
Q39. Consider a direct mapped cache with a 32-bit address divided as follows:

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 50

 bits 0 - 3 = offset
bits 4 - 14 = index
bits 15 - 31 = tag
How much space is required to store the tags for the cache?(in KB)_______

Answer: (4.25)
Solution:
bits 0 - 3 = offset
bits 4 - 14 = index
bits 15 - 31 = tag
Tag bits =17 bits
No. of lines = 211=2048
No of space for tag is =2048x17 /8x1024=4.25 KB
Q40. Consider a 4-way set associative write-back cache of size 64KB. Each cache
block holds 8 words of 4 bytes each. Physical addresses are 32 bits long.
Assuming that the 64KB of cache refers purely to “usable cache” – i.e. cache
that is used only to store data or instructions, and not overheads like tag bits,
what is the actual overall cache size including the overheads? _______KB

Answer:(68.5)
Solution:
𝑐𝑎𝑐 𝑕𝑒 𝑆𝑖𝑧𝑒
Number of lines in cache =
𝐵𝑙𝑜𝑐𝑘 𝑠𝑖𝑧𝑒
64∗210
=
32
26 ∗210
=
25
216
=
25
=211
211
Number of sets = = 29
22
9 bit is required for index
Number of bits for offset is 5 bits
tag = 32 – 9 – 5=18
Cache line size = (18 +32*8)
= 18+256 =274 bit
Cache size = cache line size * number of lines in cache
=274*211
=548 k bits
= 68.5 Kbytes
Answer is 68.5
The following next four questions ask you to evaluate alternative cache designs
using patterns of memory references taken from running programs. Each of the
caches under consideration has a total capacity of 8 (4-byte) words, with one
word stored in each cache line. The cache designs under consideration are:
DM: a direct-mapped cache.

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S2: a 2-way set-associative cache with a least-recently-used replacement policy.
FA: a fully-associative cache with a least-recently-used replacement policy.
The questions below present a sequence of addresses for memory reads. You should
assume the sequences repeat from the start whenever you see "...". Keep in mind
that byte addressing is used; addresses of consecutive words in memory differ by 4.
Each question asks which cache(s) give the best hit rate for the sequence. Answer by
considering the steady-state hit rate, i.e., the percentage of memory references that
hit in the cache after the sequence has been repeated many times.
Q41.Which cache(s) have the best hit rate for the sequence 0, 16, 4, 36, ...
(a) DM (b) S2
(c) FA (d) Both B and C

Answer:(d)
Solution:
Cache size =8 words =8 time
1 word =4 bytes
Line size =4 bytes =1 word
 2 bits for offset
3 bits for index in direct mapped
2 bits of offset
2 bits for index in 2-way set associative cache
Direct Mapped
MA TAG INDEX OFFSET Line No. 1st Iteration 2nd Iteration
0 000 000 00 0 M H
16 000 100 00 4 M H
4 000 001 00 1 M M
36 001 001 00 1 M M
So, form the 2 iteration per iteration there will be 2 misses on 4 and 36
nd

2-way SA:
MA TAG INDEX OFFSET Set No. 1st Iteration 2nd Iteration
0 0000 00 00 0 M H
16 0001 00 00 0 M H
4 0000 01 00 1 M H
36 0010 01 00 1 M H
So, form the 2nd iteration per iteration there will be no misses.

FA:
MA TAG OFFSET 1st Iteration 2nd Iteration
0 000000 00 M H
16 000100 00 M H
4 000001 00 M H
36 0010 01 00 M H
So, form the 2 iteration per iteration there will be no misses.
nd

So, S2 and FA gives same cache hit rate

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Q42.Which cache(s) have the best hit rate for the sequence
0, 4, 8, 12, 16, 20, 24, 28, 32...
(a)DM (b) S2
(c) FA (d) All give same

Answer:(a)
Solution:
Converted the memory address (MA) into block address (BA)
MA 0 4 8 12 16 20 24 28 32
BA
0 1 2 3 4 5 6 7 8
= MA/Block size

(a) DM
MA 0 4 8 12 16 20 24 28 32
BA = MA/Block size 0 1 2 3 4 5 6 7 8
Line No.
0 1 2 3 4 5 6 7 0
= (BA) MOD (8)
1st iteration M M M M M M M M M
2 iteration
nd M H H H H H H H M
… … … … … … … … … …
So, form the 2 iteration, per iteration
nd there will be 2 misses on 0 and 32

(b) S2
MA 0 4 8 12 16 20 24 28 32
BA = MA/Block size 0 1 2 3 4 5 6 7 8
Set No.
0 1 2 3 0 5 6 7 0
= BA MOD (4)
1st iteration M M M M M M M M M
2nd iteration M H H H M H H H M
… … … … … … … … … …
So, form the 2 iteration, per iteration
nd there will be 3 misses on 0, 16 and 32

(c) FA
MA 0 4 8 12 16 20 24 28 32
BA = MA/Block size 0 1 2 3 4 5 6 7 8
1st iteration M M M M M M M M M
2 iteration
nd M M M M M M M M M
… … … … … … … … … …
So, form the 2 iteration per iteration there will be no hit.
nd

Q43.Which cache(s) have the best hit rate for the sequence 0, 4, 8, 12, 16, 20, 24, 28,
32, 28, 24, 20, 16, 12, 8, 4, ...
(a) DM (b) S2
(c) FA (d) All have same performance

Answer:(a)
Solution:
BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 53
 Converted the memory address (MA) into block address (BA)
MA 0 4 8 12 16 20 24 28 32 28 24 20 16 12 8 4
BA
= MA/Block 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
size

(a) DM
MA 0 4 8 12 16 20 24 28 32 28 24 20 16 12 8 4
BA
= MA/Block 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
size
Line No.
= (BA) MOD 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1
(8)
1 iteration M M M
st M M M M M M H H H H H H H
2nd
M H H H H H H H M H H H H H H H
iteration
… … … … … … … … … … … … … … … … …
So, form the 2 iteration,
nd per iteration there will be 2 misses on 0 and 32

(b)S2
MA 0 4 8 12 16 20 24 28 32 28 24 20 16 12 8 4
BA =
MA/Block 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
size
Set No.
= BA MOD 0 1 2 3 0 5 6 7 0 7 6 5 0 3 2 1
(4)
1st
M M M M M M M M M H H H M H H H
iteration
2nd
M H H H M H H H M H H H M H H H
iteration
… … … … … … … … … … … … … … … … …
So, form the 2nd iteration, per iteration there will be 4 misses on 0, 16 and 32

(c) FA
MA 0 4 8 12 16 20 24 28 32 28 24 20 16 12 8 4
BA =
MA/Block 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
size
1st
M M M M M M M M M M M M M M M M
iteration
2nd
M M M M M M M M M M M M M M M M
iteration
… … … … … … … … … … … … … … … … …
So, form the 2 iteration per iteration there will be
nd no hit.

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Q44.Which cache(s) have the best hit rate for the sequence
0, 4, 8, 12, 32, 36, 40, 44, 16 ...
(a) DM (b) S2
(c) FA (d) All have same performance

Answer: (b)
Solution:
Converted the memory address (MA) into block address (BA)
MA 0 4 8 12 32 36 40 44 16
BA
0 1 2 3 8 9 10 11 4
= MA/Block size

(a) DM
MA 0 4 8 12 32 36 40 44 16
BA
0 1 2 3 8 9 10 11 4
= MA/Block size
Line No.
0 1 2 3 0 1 2 3 4
= (BA) MOD (8)
1st iteration M M M M M M M M M
2 iteration
nd M M M M M M M M H
… … … … … … … … …
So, form the 2 iteration, per iteration
nd there will be 2 misses on 0 and 32

(b) S2
MA 0 4 8 12 32 36 40 44 16
BA
0 1 2 3 8 9 10 11 4
= MA/Block size
Line No.
0 1 2 3 0 1 2 3 0
= (BA) MOD (4)
1st iteration M M M M M M M M M
2 iteration
nd M H H H M H H H M
… … … … … … … … …
So, form the 2nd iteration, per iteration there will be 3 misses on 0, 16 and 32

(c) FA
MA 0 4 8 12 32 36 40 44 16
BA
0 1 2 3 8 9 10 11 4
= MA/Block size
1st iteration M M M M M M M M M
2nd iteration M M M M M M M M M
… … … … … … … … …
So, form the 2 iteration per iteration there will be no hit.
nd

For the next three questions, consider the following sequence of memory references
given as word addresses: 22, 10, 27, 21, 23, 30, 4, 22, 7, 35, 5, 31, 10, 27, and 21.
Assume the cache is initially empty.
Q45. How many of the above references a cache hit is if 64 bytes direct mapped cache

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 55

 with block size of 8 bytes and a word size of 4 bytes is used? ________

Answer:(4)
Solution:
64
Cache size = =16 words
4
8
Block size = = 2 words, therefore number of bits for offset 1 bit
4
16
Number of lines = = 8 words = 23, therefore number of bits for index 3 bits
2
(22)10 =(010110)
(10)10 =(001010)
(27)10 = (011011)
(21)10 = (010101)
(23)10=(01 011 1)
(30)10 = (01 111 0)
(4)10=(000100)
(7)10 = (00 011 1)
(35)10 = (100011)
(5)10 = (00 010 1)
(31)10 = (01 111 1)

Word address:
WA 22 10 27 21 23 30 4 22 17 35 5 31 10 27 21
Hit/Miss M M M M H M M H M M H H M M M
So,Number of hits =4
Answer is 4
Q46. How many of the above references a cache hit is if a 64 bytes 2-way set
associative cache, with block size of 8 bytes, a word size of 4 bytes, and LRU
replacement policy is used? ______

Answer: (5)
Solution:
8
Block size = = 2 words
4
16
Number of sets = = 4= 22
2∗2
16
Cache size = =16
4
(22)10 =(010110)
(10)10 =(001010)

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 56

 (27)10 = (011011)
(21)10 = (010101)
(23)10=(01011 1)
(30)10 = (01111 0)
(4)10=(000100)
(7)10 = (00011 1)
(35)10 = (100011)
(5)10 = (00010 1)
(31)10 = (01111 1)

Word address:
WA 22 10 27 21 23 30 4 22 17 35 5 31 10 27 21
Hit/Miss M M M M H M M H M M H H M M H
So, Number of hits = 5
Q47.How many of the above references a cache hit is if a 64 byte Fully associative
cache, with block size of 8 bytes, a word size of 4 bytes, and LRU replacement
policy is used?________

Answer:(7)
Solution:
8
Block size = = 2 words
4
MA 22 10 27 21 23 30 4 22 17 35 5 31 10 27 21
BA
= MA/Block 11 5 13 10 11 15 2 11 8 17 2 15 5 13 10
size
Hit/Miss M M M M H M M H M M H H H H H
Number of hits=7
Answer is 7
Q48. Consider a direct mapped cache memory with total 16 cache blocks (0-15) and a
main memory with 256 blocks (0-255). Assuming that initially the cache did not
have any memory block. Consider the following sequence of memory block
references: 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, and 253. Which
memory blocks will be present in the cache after the above sequence of memory
block references?

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 57

 (a) 2, 3, 180, 181, 88, 186, 43, 44, 253, 14, 191
(b) 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253
(c) 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186
(d) 3, 180, 43, 2, 191, 190, 88, 14, 181, 44, 186.

Answer:(a)
Solution:
Number of blocks = Memory address block mod no of block
8 mod 16=3
180mod 16=4
43mod16=4
4 mod 16=2
191mod 16 = 15
88mod 16=8
190 mod 16=14
14mod 16=14
181mod16= 5
44mod 16=12
186mod 16=10
253mod 16=13

So, block present in cache after execution of sequence of job.

2,3,180,181,88,186,43,44,253,14,191
Answer is A
Q49. Consider a 2-way set associative cache memory with 8 sets (0-7) and total 16
cache blocks (0-15) and a main memory with 256 blocks (0-255). Assuming that
initially the cache did not have any memory block. Consider the following
sequence of memory block references: 3, 180, 43, 2, 191, 88, 190, 14, 181, 44,
186, 253. Which memory blocks will be present in the cache after the following
sequence of memory block references if LRU policy is used for cache block

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 replacement?
(a) 3,180,43,2,191,14,181
(b) 2, 191, 88, 190, 14, 181
(c) 14, 181, 44, 186, 253
(d) 88,2,186,3,43,180,44,181,253,190,14,191

Answer:(d)
Solution:
Number of sets = Memory block address mod number of set
3mod 8=3
180mod8=4
43mod8=3
2mod8=2
191mod8=7
88mod8=0
190 mod 8=5
14 mod 8=6
181mod 8= 5
44 mod 8 =4
186mod 8 =2
253 mod 8=5

So, at last memory block will be present in the cache after the following
sequence.88,2,186,3,43,180,44,181,253,190,14,191
Answer is D
Q50. A designer makes a mistake and builds a cache that has a MRU (most recently
used) replacement policy instead of an LRU replacement policy. What is left in a
4-entry, fully associative, MRU cache with 1-byte lines after the following
address accesses: 1, 2, 3, 4, 5,3, 5, 1, 5, 2
(a) 1,2,3,5 (b)2, 5, 1, 3
(c) 4,2, 5, 3 (d)both a and b

Answer:(d)
Solution:

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 1
2
3
4 5
1 miss

2miss

3miss

4miss

5miss
replaces
3hit

5hit

1hit

2 hit

At last 1,2,3&5 remains as it is a fully associative memory , initially it is not

necessary that it will replace the first access to first line of cache .it may part it
anywhere ,so any combination is possible .

Q51.Considera 64-byte cache with 8 byte blocks, an associativity of 2 and LRU block
replacement. Virtual addresses are 16 bits. The cache is physically tagged. The
processor has 16KB of physical memory. What is the total number of tag bits in
cache?_____________

Answer: (72)
Solution:
Offset =3 bits (8 bytes block)
No .of lines =64/8=8
No of sets =8/2=4
Set index =2 bits
Size of physical memory =214 bytes
mm address bits =14 bits
tag bits =14-2-3=9 bits
no of lines =8, tag bits will be stored per lines.
total no of tag bits =8x9=72

Q52. What data will be in a 4-entry, fully-associative, LRU cache with one word per
line after the following memory accesses word address: 0, 1, 2, 3, 4, 5, 3, 2, 1?

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 60

 (a) 1, 2, 3, 4 (b) 1, 2, 3, 5
(c) 1, 3, 4, 5 (d) 1, 2, 4, 5

Answer:(b)
Solution:
0 4
1
1 5
2
3
MRU 0 miss
1 miss
2 miss
3 miss
MRU 4 miss replaces 0
5 miss replaces 1
3hit
2 hit
1 miss replaces
Q53. Assume you have a fully associative cache with 4 entries. For the following
memory block address sequence, which entry becomes at the end? Assume that
LRU police is used for replacement.
8 9 5 2 6 5 9 10 3
(a) 3, 9, 5, 10 (b) 9,5,2,10
(c) 8,9,5,10 (d) 9,5,2,3

Answer:(a)
Solution:
8 6 3
9
5
2 10
It is fully associative cache, so the data will be shored one by one.
1 1
8 9 5 2 6 5 9 10 3
M M M M m M M M M
 
Replaces 8Replaces 2 Replaces6
Q54.Assume you have a 2-way set-associative LRU cache with 4 entries and a cache
line size of 1 byte. What will the hit (H) miss (M) pattern be for the following
access pattern: 0 1 2 3 7 0 3 8 1?

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 (a) M MMMMM H M M (b)MMMMMH M M H
(c) M MMMM H H M M (d) M MMMM H H M H

Answer:
Solution:
0 1 2 3 7 0 3 8 1
M M M M M H H M M
0
2 8
1 7
1
3

to finds in which set they will map, we will find line no modulus2.
For next two questions consider the access pattern A, B, C, B, A where each letter
corresponds to a unique cache block. You are to assume there were no accesses to
any block before this, and that all conflict is random.
Q55. The probability of the second access to “A” being a hit on a direct-mapped cache
with 4 lines is closest to: _________

Answer: 100
Solution:
A,B,C all them of them correspond to unique cache block If they come in
different cache block & we have 4 blocks in the cache.
A
B The probability of hit on a second assess =1
C
Q56. For a fully-associative cache with 2 lines the probability of a hit is closest to____

Answer: (0 or 100)
Solution:
If replacement policy is LRU
For fully associative
A C hit of a on second access=0
B
If replacement policy is MRU
A
B C hit of a on second access=1
For next four questions Assume the cache with 8 blocks. If following memory block
address access in the given sequence
0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4
What is cache hit(in %) rate in following four cases?
Q57. Cache is direct mapped____________

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 Answer:31.82
Solution:
0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4

Q58.Cache is 2-way set associative assume LRU Replacement__________

Answer:31.82
Solution:
0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4

m h m h m h m mmmmmmmmmmm h hhh
Hit rate=7/22=31.82
Q59.Cache is 4-way set associative assume LRU replacement__________

Answer:31.87
Solution:
0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 63

 m h m h m h m mmmmmmmmmmm h hhh
bit rate =7/22=31.87

Q60.Cache is fully associative assume LRU replacement_____

Answer: (50)
Solution:
0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4
0 1 2 3 4 5 6 7
0 8 16 24 32 40 44 1
2 3 4
m h m h m h mm m m h hhh m mmm h hhh
cache hit =11/22=50
Q61. Consider a fully associative cache with 8 cache blocks (numbered 0-7) and the
following sequence of memory block requests: 4, 3, 25, 8, 19, 6, 25, 8, 16, 35,
45, 22, 8, 3, 16, 25, 7 If LRU replacement policy is used, which cache block will
have memory block 7?_

Answer:(5)
Solution:
0 4 45
1 3 22
2 25
3 8
4 19 3
5 6 7
6 16
7 35
7 will be in block no 5.

Q62. If you have a 32-bit address space (addresses are 32 bits) and you have a 4-way
associative cache that uses 5 bits as the set index and 4 bits as the byte offset,
how large is the data portion of the cache (in bytes)?_______

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 Answer :( 2048)
Solution :
5 bit set index
4 way set associative
that means 2^7 lines
and 4 bits for offset thus line size is 2^4 bytes
total cache size=#linesxline size
=2^4 x 2^7
=2^11
=2048 bytes
For the next three questions, Consider a direct mapped of 8 words, with block 2
word per block. The following sequence of accesses to memory block 0, 5, 2, 7, 4, 0
and 4 is repeated 10 times.
Q63.The number of compulsory misses_________
Answer : (5)
Solution :
Memory block = 0,5,2,7,4,0,4, is repeated 10 times

0mod4=0
5mod4=1
2mod4=2
7mod4=3
4mod4=0
So number of compulsory miss=5
for 0,5,2,7,4.
and next m=0 and 4 count in conflict miss
Answer is 5

Q64.The number of conflict misses_______

Answer: (0)
Solution:
As after 1st iteration
0527404

Q65. The number of capacity misses___________

Answer :38
Solution :
Number of capacity miss in 1st iteration = 1 on access of 0.
Number of capacity miss in each iteration after 1st = 2 on access of 4 and 0.
0 Compulsory

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 5 Compulsory
2 Compulsory
7 Compulsory
4 Compulsory
0 Capacity
4 Capacity
0 Capacity
5 Hit
2 Hit
7 Hit
4 Capacity
0 Capacity
4 Capacity
Therefore total capacity miss = 2 + 9 x 4 = 38
Q66. Consider a 2-way set associative cache with 256 blocks and uses LRU
replacement, initially the cache is empty. Conflict misses are those misses
which occur due the contention of multiple blocks for the same cache set.
Compulsory misses occur due to first time access to the block. The following
sequence of accesses to memory blocks
(0,128,256,128,0,128,256,128,1,129,257,129,1,129,257,129) is repeated 10
times. The number of conflict misses experienced by the cache is ___________.
Answer :( 76)
Solution :
256
Number of sets =
2
=128

0,128,256,128,0,128,256,128,1,129,257,129,1,129,257,129

0mod128=0
128 mod128=0
256 mod128=0
1 mod 128 =1

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 129 mod 128=1
257 mod 128=1
So in first iteration =4 conflict miss
for 2nd iteration = 0,256,0,256,1, 257, 1 , 257
8 misses
4+ 9*8
72+4=76
Answer is 76
Q67. Which one of the following statements is/are correct?
(a) Compulsory misses cannot be reduced by increasing the size of the cache.
(b) Increasing the associativity of the cache can increase conflict misses.
(c) Capacity misses can be reduced by increasing the associativity of the cache.
(d) Compulsory misses can be reduced by increasing the associativity of the
cache.
Answer :(c)
Solution :
(A) compulsory missed can be reduced by increasing line size , hence increasing
the size of cache, but increasing the associativity will not affect compulsory
misses at all  (A) &(d) are false
(B) False increasing the associativity decreases conflict misses.
(C) True.

Q68. Which one of the following statements is/are correct?

(a) Accessing a set-associative cache is faster than accessing a direct mapped
cache.
(b) Compulsory misses cannot be totally avoided.
(c) A capacity miss occurs when a replaced cache line needs to be accessed
again.
(d) Compared with a direct mapped cache, a fully associative cache has a larger
tag field.
Answer :( b)
Solution :
(A)False the more number of lines is a set the more no.of comparators used for
comparing tag in a cache with is set associative.
(B)True
(C)False, a conflict misses accurs when a replaced cache line needs to be
accessed again.
(D) False depends on the configuration.

Q69. Match the column for each of the following suggested changes in set associative
cache with a reason why the change might make things worse, assuming that
the total size of the cache (i.e., the total amount of data it can store) must
remain the same

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 (a) 1-ii, 2-iii, 3-i, 4-iv
(b)1-iii,2-i,3-iv,4-ii
(c) 1-iv, 2-i, 3-ii, 4-iii
(d)1-ii,2-i,3-iv,4-iii
Answer : (d)
Solution :
Explanation:
1. Increases the block size – ii. Decrease cache ability to capture temporal
locality because cache store fewer total block.
2. Decrease the block size – i. Decreases cache‟s ability to capture spatial
locality
3. Decrease set associativity – iv. Increase potential for conflict miss.
4. Increase set associative – iii. Slow cache hit time, because no. of line per set
increase, so tag comparator also increase so it slows cache hit time.
Correct answer is (d)
Q70. Which of the following statement(s) is/are true?
(a) It is possible for Conflict Misses in Set-Associative Cache Mapping.
(b) Cache block search time in Direct Mapped Caches is larger than that of other
Cache Organization.
(c) Increasing Cache Line size helps decreasing the Cache Miss Ratio for
programshaving Spatial Locality.
(d) Decreasing Cache Line sizes could decrease Conflict Misses.
Answer :(a), (c) and (d)
Solution :
(a) True,yes it is possible
Ex .cache have 4 lines 2 sets block sequence no is 0480---
Conflict miss is there all are mapped to set 0 .
(b) False, cache search time is more where more comparator are used like in
fully associative and n way set associative, not in direct mapped.
(c) True,
(d) True again it depends upon sequence accessed.
Q71.Which one of the following statements is/are correct?
(a) Temporal locality means a recently accessed data item is likely to be accessed

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 68

 again in the near future.
(b) Spatial locality means variables should be stored close to each other.
(c) Temporal locality means a temporary variable is more frequently used than a
global variable.
(d) Spatial locality means a branch instruction should not branch to an
instruction that is too far away.
Answer :(a)
Solution :
Temporal locality is when we use a for loop and in that loop incrementing a
variable at each iteration, the variable location is accesses after some time again
&again . Spatial locality is when the data which are accessing is stored close in
mm, for example accessing an array element by element.

Q72. Which is the fastest cache mapping function?

(a) Direct mapping
(b) Set associative mapping
(c) Fully associative mapping
(d) Cannot say anything
Answer : (a)
Solution :
only 1 tag comparator is used in direct mapped cache thus it is fastest cache
mapping function
Q73. Which is the slowest cache mapping function?
(a) Direct mapping
(b) Set associative mapping
(c) Fully associative mapping
(d) Cannot say anything
Answer : (c)
Solution :
Slowest cache mapping function is fully associative cache because it uses LRU
to replace the block , which needs to be searched in all the lines

Q74. Which cache mapping function is most likely to thrash, i.e., two blocks
contending with each other to be stored in the same line?
(a) Direct mapping
(b) Set associative mapping
(c) Fully associative mapping
(d) Cannot say anything
Answer : (a)
Solution :
In other words conflict miss is most likely to occur in direct mapped cache
Q75. The problem with a cache that uses a write through policy is/are that:
(a) It runs the risk of leaving main memory invalid for a long period of time.
(b) It cannot be used with multiple CPUs even if the CPUs are watching main

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 memory for an update.
(c) It slows down the write process.
(d) It requires additional overhead in the cache to keep track of which blocks
have been modified.
Answer :(c)
Solution :
Write through policy, writes data cache and main memory simultaneously
Whenever a write request comes.
(A)& (D) both are reasons why write –back cache is not used .
(C) is true, it directly writes to main memory whenever write request comes we
will access main memory, this will increase the average access time (B) is false it
can be used.
Q76.Which of the following statements is/are not true about caches?
(a)Caches do not have to be as big as the data the program needs to access
(b) It takes longer to access a cache if it is full
(c) Cache memories are faster than memories used for DRAM
(d) Caches only help if the application reuses its data
Answer : (B)
Solution :
It takes the same amount of time to access cache irrespective to the amount of
data
it have, all other are true

Q77. Which one of the following is/are correct statement?

(a) In a set associative cache, blocks in memory that map to the same set are
stored contiguously in memory.
(b) All other things equal, direct mapped caches have a lower tag overhead than
fully associative caches.
(c) Bigger cache blocks always lead to a higher hit rate.
(d) On every store instruction, a write back cache will write to main memory
Answer :(b)
Solution :
Solution :-
(A) False ,if two block are contiguous in main memory ,they will be mapped to
contiguous sets.
(B) True , direct mapped caches divides the virtual address in 3 parts ,tag line
no and offset .where as fully associative cache divides the virtual address
into 2 parts tag & offset if offset is same then tag in fully associative will be
greater.
(C) false in cash of temporal locality it will cause greater miss
(D)False, write back cache updates main memory when there is swapping of the
memory contents. The write through cache is the one which on every store
will write to main memory

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Q78. A cache has a 95% hit ratio, an access time of 100ns on a cache hit, and an
access time of 800ns on a cache miss. What is the effective access time?_
______ns
Answer: (135)
Solution:
Effective access time:
cache hit x cache time access +cache miss(cache access +mm access )
0.95x100+0.5x800
95+40=135 ns
Q79. Assume a memory access to main memory on a cache "miss" takes 40 ns and a
memory access to the cache on a cache "hit" takes 10 ns. If 75% of the
processor's memory requests result in a cache "hit", what is the average memory
access time?
(a) 17.5 ns (b) 32.5 ns
(c) 40.0 ns (d) 7.5 ns
Answer : (17.5)
Solution :
On cache miss time required =40 ns
On cache hit time required =10 ns
Cache hit =75%
AMAT=(1-ht)x miss time +ht x hit time
= 0.25x40+0.75x10
=17.5 ns

Consider a cache with following specification

Q80.
 Hit rate: 92%
 Hit latency: 2 cycle
 Memory access time: 124 cycles
What is the average memory access latency? (in cycle)________
Answer : (11.92)
Solution :
EAT=0.92*2+0.08*(2+124)
=1.84+0.08*126
1.84+10.08
=11.92
Answer is 11.92

Q81. Your machine has a write-back cache. The cache read and writes times are both
2 nanoseconds. The memory read and writes times are both 50 nanoseconds.
The proportion of writes is 15%, and the hit ratio is 90%. What is the average
effective memory access time?
(a) 6.1 nanoseconds (b) 7 nanoseconds
(c) 13.45 nanoseconds (d) 3.4 nanoseconds
Answer : (b)

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 Solution :
0.85(0.9x2+0.1x52)+0.15/(0.9x2+0.1x52)=7ns
Hit rate 90%
Write proportion =15 %
Q82. Consider a memory system with a single L1 cache that has an average access
time of 100ns without L1, and 30ns with L1. L1 has an access time of 10ns.
What is the hit ratio of L1 required to have an average access time of 30ns?
(a) 90% (b) 70%
(c) 80% (d) 81.8%

Answer : (c)
Solution :
30 ns =hx10 +(1-h)(100+10)}EAT
30 =10h+(1-h)110
30 = 10 h +110 -110 h
100h=80
H = 80%
H=hit rate
With cache L1 means EAT
Without cache L1 means  main memory time

Q83. A direct mapped cache consists of eight blocks. Byte-addressable main memory
contains 4K block of eight bytes each. Access time for cache is 22 ns and the
time required to fill a cache slot from main memory is 300ns. (This time allows
us to determine the block is missing and bring it into cache.) Assume a request
is always started in parallel to both cache and to main memory. If a block is
missing from cache, the entire block is brought into cache and the access is
restarted. Initially, the cache is empty and cache hit rate is 80%. What is the
effective access time for this program in nanoseconds? _________
Answer: (82)
Solution:
Cache hit rate =80%
Time to access cache =22 ns (tc)
Time to access main memory =300 ns (tm)
Eat=ht * tc+(1-ht)(tc + tm)
= 0.8x22+0.2(22+300)
=82

Q84.Consider the following memory system:

• Level 1 cache: 91% hit rate, 1‐cycle access time.
• Level 2 cache: 98% hit rate, 15‐cycle access time.
• Memory: 140‐cycle access time.
What is the average memory access time in cycles for the above memory
system?____ (Round off to two decimal places)

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 72

 Answer :( 2.602)
Solution :
AMAT = 0.91 * 1 + 0.09 * (0.98*(1+15) + 0.02*(1+15+140) = 2.602 cycles
Q85. Assume that the local hit rate for our L1 cache is 40% and the local hit rate for
our L2 cache is also 40%. The hit time for the L1 cache is 5 cycles, the hit time
for the L2 cache is 25 cycles, and access time for main memory is 100 cycles.
The average memory access time in cycles is________
Answer :(56)
Solution :

Q86. Your machine has a write-through cache. The cache read and writes times are
both 2 nanoseconds. The memory read and writes times are both 50
nanoseconds. The proportion of writes is 15%, and the hit ratio is 90%. What is
the average effective memory access time?
(a) 6.1 nanoseconds (b) 5.9 nanoseconds
(c) 7 nanoseconds (d) 13.45nanoseconds
Answer : (d)
Solution :
0.85*(0.90*2+0.1*(2+50))+ 0.15*50
as the cache is write through therefore it access main memory simultaneously

therefore it result in
(0.15*50 )
= 13.45 nenoseconds
Answer is D

Q87. Consider the following cache system:

 L1 has a hit time of 2 cycles, and hits 90% of the time.
 L2 has a hit time of 15 cycles, and hits 95% of the time.
 L3 has a hit time of 25 cycles, and hits 99% of the time.
 Main Memory has an access time of 100 cycles.
The Average Memory Access Time (in terms of cycles) of cache is _________
(Rounded off to two decimal places)
Answer : 3.63
Solution :
All are block Hit rates
.9x2+.1[.95x17+0.5x[.99x42+.01x142]}=3.63

For next three questions, consider a system with CPI of 1.2 cycles assuming
memory access always results in cache hit. Processor run at 2 GHz. Consider a

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program running on this system has 30% Load and store instructions. The processor
has an I-cache with miss rate of 2% and a D-cache with miss rate of 5%. The hit time
is 1 clock cycle. The miss penalty for both the cache is 50 ns.
Q88.What is the average memory access time for instruction access in clock cycles?
_________
Answer : (3)
Solution :
1
Cycle time = = 0.5nsec
2∗10 9
50
Number of clock cycle= = 100 cycle
0.5
1+0.02*100= 3cycles
Answer is 3 cycle

Q89.What is the average memory access time for data access in clock cycles?
__________
Answer :( 6)
Solution :
1+0.05*100=6 cycles

Q90.What is the overall CPI including both instruction and data access?__________
Answer : (4.7)
Solution :
1.2+0.02*100+0.3*0.05*100
=4.7 cycles
Answer is 4.7

Q91. A machine has a base CPI of 2 clock cycles. Assume that instruction miss rate is
12% and the data miss rate is 6%, and on average, 30% of all instructions
contain one data reference. The miss penalty for the instruction and data cache
is 10 cycles. What is the average CPI?________
Answer : ( 3.38)
Solution :
Bass CPI =2 clock cycles
= 2+.12x10+.3x.06x10=3.38

Q92. Compute the average memory access time for a 4-way set-associative, unified L2
cache with 64B blocks and a 95% hit rate. The access time for this 1MB cache is
8 cycles, and it take 80 cycles to move a 64B block from memory to the cache.
_______Cycles
Answer : (12)
Solution :
amat=hit rate x(cache access time)+miss rate(cache accestime+main memory
access time)

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 =.95x8+.05x88
=12 cycles
Q93. Suppose we have a cache that has an access time of 5ns, and a main memory
with an access time of 80ns. If 10,000 accesses take a total of 70 microseconds.
What is the miss rate of your cache?____
Answer :( 0.025)
Solution :
EAT=
10,000= 70 micro second
70
1 access= *1000ns
10,000
= 7ns
EAT= ht* cache access time+(1-ht) ((At+MAT)
7= ht*5+(1-ht)(5+80)
7=5ht +85 – 85 ht
-78 =-80 ht
ht= 78/80
ht= 0.975
Miss rate =(1-ht) = (1-0.975)
Answer is 0.025
Q94. Suppose that in 1000 memory reference there are 40 misses in the first level
cache and 20 misses in the second level cache. Assume miss penalty from the
L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.
The hit time of the L1 cache is 1 clock cycle. If there are 1.5 memory references
per instruction. What is the average stall cycle per instruction?
(a) 3.4 cycles
(b) 3.5 cycles
(c) 3.2 cycles
(d) 3.6 cycles
Answer : (d)
Solution :
Overall 1000 memory access L1
Miss Rate=
1000---- 40
40
L1 = 0.04
1000
20
L2 = 0.5
40
0.04*10+0.04*0.05*100 = 2.4
So Average per instruction
= 2.4x1.5=3.6

Q95. Consider a two-level cache hierarchy with L1 and L2 caches. An application

incurs 2.8 memory accesses per instruction on average. For this application, the
miss rate of L1 cache is 10%; the L2 cache experiences, on average, 10 misses
per 1000 instructions. The miss rate of L2 expressed correct to two decimal

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 places is _______.
Answer : (0.04)
Solution :

=1000*2.8
=2800Memory reference
Therefore miss rate = 0.1
280 memory reference with in L1
10
= 0.035 ≅ 0.04
280
Answer is 0.04
For the next two questions, consider three machines with different cache
configurations:
 Cache 1: Direct-mapped with one-word blocks
 Cache 2: Direct-mapped with four-word blocks
 Cache 3: Two-way set associative with four-word blocks
The following miss rate measurements have been made:
 Cache 1: Instruction miss rate is 4%; data miss rate is 8%.
 Cache 2: Instruction miss rate is 2%; data miss rate is 5%.
 Cache 3: Instruction miss rate is 2%; data miss rate is 4%.
For these machines, one-half of the instructions contain a data reference. Assume
that
the cache miss penalty is 6 + Block size in words. The ideal CPI for this workload is
2.0.
Q96. Which cache spends the most cycles on cache misses?
(a) Cache 1 (b) Cache 2 (c) Cache 3 (d) Both a and b
Answer : (a)
Solution :
Cache 1
2+0.04*7+0.08*0.5*7
Cache2:
2+0.02*10+0.05*0.5*10
Cache 3: 2+ 0.02*10+0.04*0.5*10
=2.3
Cache spends the most cycles o code misses
Answer is A
Q97. Which cache has the best performance?
(a) Cache 1 (b) Cache 2 (c) Cache 3 (d) Both b and c
Answer : (c)

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 Solution:
Cache 3 has best performance because memory cycle is 2.03
Answer is C

INSTRUCTION SET ARCHITECTURE

Q 1.
Match the following instruction to its appropriate addressing mode:
Instructions Addressing Mode
1. MOV AL, 35H i. Direct Mode
2. MOV AX,CX ii. Base addressing
3. MOV AX, [BX] iii. Register mode
iv. Register Indirect
4. ADD AL,[0301]
mode
5. MOV
v. Immediate mode
AL,[BX+05]
6. MOVL
vi. Displacement mode
12(R5),R3
(a) 1-v, 2-iii,3-iv,4-i,5-ii, 6-vi (b) 1-iii, 2-v,3-iv,4-i,5-ii, 6-vi
(c) 1-v, 2-iii,3-iv,4-i,5-vi, 6-ii (d) 1-v, 2-iii,3-i,4-iv,5-ii, 6-vi
Answer :- A
Solution:
1. MOV AL, 35H i. Immediate mode
2. MOV AX,CX ii. Register mode
3. MOV AX, [BX] iii. Register Indirect mode
4. ADD AL,[0301] iv.Direct Mode
5. MOV AL,[BX+05] v. Base addressing
6. MOVL 12(R5),R3 vi. Displacement mode
Answer is A
Q 2.
Match List I with List II and select the correct answer. Assume that A and B are
memory addresses.
List I List II
A. Immediate 1. LD A
addressing 2. MOV R1,
B. Implied addressing R2
C. Register addressing 3. SUB A,
D. Direct addressing #20
4. PUSH
(a) A – 3, B – 4, C – 2, D – 1 (b) A – 2, B – 1, C – 3, D – 4
(c) A – 3, B – 4, C – 1, D – 2 (d) A – 2, B – 4, C – 3, D – 1
Answer :(a)
Solution :
List I List II
A. Immediate 3. SUB A,
addressing #20

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 B. Implied addressing 4. PUSH
C. Register addressing 2. MOV R1,
D. Direct addressing R2
1. LD A

(a) A – 3, B – 4, C – 2, D – 1
Q 3.
Match List-I with the List-II and select the correct answer.
List I List II
S1: ADD R1, R2, I. Displacement
100(R3)[R3] addressing
S2: Add R4,100(R1) II. Scaled addressing
S3:Add R3,(R1+R2) III. Index/base addressing
S4:Add R1,(R2)+ IV. Auto increment
addressing
(a) S1 – I, S2 – II, S3 – III, S4 – IV
(b) S1 – II, S2 – I, S3 – III, S4 – IV
(c) S1 – II, S2 – II, S3 – IV, S4 – III
(d) S1 – I, S2 – III, S3 – II, S4 – IV
Answer :(b)
Solution :
List I List II
S1: ADD R1, R2, II . Scaled addressing
100(R3)[R3] I. Displacement addressing
S2: Add R4,100(R1) III. Index/base addressing
S3:Add R3,(R1+R2) IV. Auto increment
S4:Add R1,(R2)+ addressing
(b) S1 – II, S2 – I, S3 – III, S4 – IV
For the next four questions, suppose we have the instruction Load 1000. Given
memory and register R1 contain the values below:

Assuming R1 is implied in the indexed addressing mode; determine the actual value
loaded into the accumulator using the following addressing modes:
Q 4.
In Immediate addressing the actual value loaded into the accumulator is_______
Answer :1000
Solution :

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 Load 1000
and in immediate direct value is available
Answer is 1000
Q 5.
In Direct addressing the actual value loaded into the accumulator is _________
Answer :1400
Solution :
Load(1000), so go to 1000 memory location , and read value of memory
location
1000 value of memory location 1000 is 1400.Answer is 1400
Q 6.
In Indirect addressing the actual value loaded into the accumulator is________
Answer :1300
Solution :
Load ([1000])

Answer is 1300
Q 7.
In Indexed addressing the actual value loaded into the accumulator _____
Answer :1000
Solution :
Indexed
Load 200(1000)
Load (200+1000)

Answer is 1000

Q 8.
What is the SOURCE ADDRESSING MODE for the instruction:
ADD AX,[1000] //AXMEM[1000]
(a) Register Direct
(b) Immediate
(c) Memory Direct
(d) Register Indirect
Answer :(c)
Solution :

Answer is C

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Q 9.
What is the DESTINATION ADDRESSING MODE for the instruction?
ADD AX, [1000] //AXMEM[1000]
(a) Register Direct
(b) Immediate
(c) Memory Direct
(d) Register Indirect
Answer :(A)
Solution :

Answer is A

For next two questions,refer to a processor with an accumulator and two registers,
R1 and R2. At some point in the execution of a program, R1 contains 40, R2 contains
50, Memory location 40 contains 50, location 50 contains 60, and location 60
contains 70.
Q 10.
What will be the value in the accumulator A after the processor executes the
following instruction?
Load A, m(R1) // A ⃪ Mem[R1]
(a) 40 (b) 50
(c) 60 (d) can‟t be determined
Answer :(b)
Solution :

R1=40 R2 =50
m(40 )=50
m(50)= 60
m(60) =70
A= m(R1)
A =m(40)
A= 50
Answer is B

Q 11.
What will be the value in the accumulator A after the processor executes the
following instruction?
Load A, m[R1] // A ⃪Mem[R2]
(a) 40 (b) 50
(c) 60 (d) can‟t be determined

Q 12.
What will be the value in the accumulator A after the processor executes the
following instruction?
Loadi A, #40 // A ⃪ 40
(a) 40 (b) 50

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 (c) 60 (d) can‟t be
determined
Answer :(a)
Solution :
Load A # 40
A= 40 Immediate
Answer is A

Q 13.
Consider an 8-bit register that has the initial data 10010101. If we apply the
following operations sequentially on given register:
1. Arithmetic Shift-right by one bit
2. Logical Shift-left by one bit
3. Logical Shift-right by one bit
4. Circular Shift-left by one bit
5. Circular Shift-right by one bit
6. Arithmetic Shift-left by one bit
The content of 8-bit register at the end of the six operations (in binary) is____
Answer : 10010100
Solution
initial data 10010101
1. Arithmetic Shift-right by one bit
1 0 0 1 0 1 0 1

After applying this operation we get

1 1 0 0 1 0 1 0

2. Logical Shift-left by one bit

1 1 0 0 1 0 1 0

We get
1 0 0 1 0 1 0 0

3. Logical Shift-right by one bit

1 0 0 1 0 1 0 0

We get
0 1 0 0 1 0 1 0

4. Circular Shift-left by one bit

0 1 0 0 1 0 1 0

We get
1 0 0 1 0 1 0 0

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 5. Circular Shift-right by one bit

1 0 0 1 0 1 0 0

We get
0 1 0 0 1 0 1 0

We get
1 0 0 1 0 1 0 0
So the content of 8 bit register at the end of the six operations (in binary ) is
10010100
Answer :-10010100
Q 14.
What is the content of AL (in binary) after executing the following code? Assume
that all register can store 8-bit data and the 2‟s complement number
representation is used for the negative data.(Consider initial value of AL is
01010101 )
MOV BL, AL // BL  AL
MOV CL, 3 // CL  3
SHL AL, CL // left shift the contain of AL register
MOV CL, 2 // CL  2
SHL BL, CL // left shift the contain of BL register
ADD AL, BL // AL AL + BL
(a)11111100 (b)00000100
(c) 11111000 (d) 10101010
Answer :- (a)
Solution: BL = (01010101)
CL=3
AL = left shift the content of AL register by 3 bit
= 10101000
AL =10101000
CL=2
BL = left shift the content of BL register by 2 bit
BL = 01010101, 2
=01010100
BL = 01010100

So answer is 1111 1100

Answer is A

Q 15.
A certain processor executes the following set of machine instructions

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 sequentially.
MOV R0, # 0 // R0⃪ 0
MOV R1, 100(R0) // R1⃪Mem[R0 + 100]
ADD R1, 200(R0) // R1⃪R1+Mem[R0 + 200]
MOV 100(R0), R1 // [100+R0]R1
Assuming that memory location 100 contains the value 35 (Hex), and the memory
location 200 contains the value A4 (Hex), what could be said about the final
result?
(a) Memory location 100 contains value A4
(b) Memory location 100 contains value DA
(c) Memory location 100 contains value D9
(d) Given data is insufficient to decide
Answer :- c
Solution

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Q 16.
A stack-based processor executes the following set of machine instructions
sequentially.
1. PUSH A
2. PUSH B
3. SUB
4. PUSH C
5. ADD
6. PUSH D
7. PUSH E
8. ADD
9. DIV
10. POP Y
Initially A, B, C, D and E contain the values 20, 6, -4, 6 and 4 respectively, what is
the result in Y after execution the given program? _______
Answer :(1)
Solution:

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 A=20
B=6
C=-4
Sub =20-6 =14

Add= - 4+14=10
Add=6+4=10

Div= 10/10 = 1
POP =1
Answer is 1

Q 17.
A stack-based processor executes the following set of machine instructions
sequentially.
1. PUSH 100
2. PUSH 200

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 3. ADD
4. POP 300
Assuming that
(I) Memory location 100 contains the value 53 (Hex) and memory location 200
contains the value 4C (Hex).
(II) The stack is byte organized and the stack pointer is at 00FF, and that
(III) All PUSH and POP instructions have a memory operand.
Which of the following could the final result be?
(a) Memory location 300 contains the value 9F
(b) Memory location 00FD contains the value 9F
(c) Memory location 00FF contains a value 100
(d) Memory location 00FE contains a value 200
Answer :(a)
Solution

then Add
0101 0011
0100 1100
1001 1111
9F

POP 300
POP 300 means (300) contain 9F
Answer is A
For next four questions, consider the following code fragment:
1. loop: SUBI R3, R1, #3 // R3 = R1 - 3
2. BEQZ R3, label1 // if R3 equals to zero jump to label1
3. ADDI R4, R4, #2 // R4 = R4 + 2
4. label1: ADDI R1, R1, #1 // R1 = R1 + 1
5. BNE R1, R2, loop // if R1 is not equals to R2 then jump to loop
Assume that the initial values of R1, R2 and R4 are 3, 6 and 10 respectively. After
completion of the above code fragments...
Q 18.
What is the final contents of register R1?____
Answer :-
Solution

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BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 87
BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 88
Q 19.
How many times instruction I3 is executed ?_____
Answer :
Solution :

Q 20.
How many times instruction I5 is executed ?______
Answer :
Solution :

Q 21.
What is the final contents of register R4?_______

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Q 22.
Given the 32-bits register values in two's complement representation
s1 = 0X00000005
s2 = 0X00000003
s3 = 0XFFFFFFFC
What will be the value of registers s1 through s4 after executing the following
independentinstructions?
1. SLT s1, s1, s2 // Set on less than (signed)if s1 < s2 then s1 = 1,otherwise s1=0
2. SLT s2, s1, s3 //Set on less than (signed)if s1 < s3 then s2 = 1,otherwise
s2=0
3. SLTU s3, s1, s2 // Set on less than unsigned if s1 < s2 then s3 = 1
otherwise s3=0
4. SLTU s4, s1, s3
(a) s1=0, s2=0, s3=0 and s4=1
(b)s1=0, s2=0, s3=0 and s4=0
(c) s1=0, s2=0, s3=1 and s4=0
(d) s1=0, s2=1, s3=1 and s4=1

Answer :(a)
Solution:
s1=5
s2=3
s3= -4
s1< s2 than s1=1
5<3 (condition false)
So s1 =0
s1< s3
5< -4 (condition is false)
So s2 = 0
s1 < Ss2
5<3
Condition false So s3 =0
s1<s3 (unsigned) here no means of negative value
5< 232-4
So this condition is true
s4 =1
Answer is A

Q 23.
Consider the following MIPS assembly code:
1. SLT t0, t1, t2 // set t0 if t1< t2, otherwise set t0=0

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 2. BEQ t0, 0, X // if t0 is equal to zero then jump to label
3. BNE t3, 0, X // if t3 is not equal to zero then jump to label
4. ADDI t4, 0, 1 // t4 = 0 + 1
5. X: HALT // Stop execution
Assume that the variables a, b, c, d, 1 and x are assigned to registers t1, t2, t3, t4,
s0 and s1 respectively. Which high-level language code fragment does the above
assembly code closely correspond?
(a) if ((a<b) && (c==0)) d = 1;
(b) if ((a<b) || (c==0)) d = 1;
(c) if (a<b) d = 1;
(d) none of the above
Answer :(a)
Solution:
$t1=a, $t2=b $t3 =c $t4=d
$s0=I $s1=X
If(a<b) means $t1<$ t2 , than set $ t0 =1
BEQ += = 0(false)
C= = 0 (If c does not equal to 0)
then go to level X, otherwise
$ d=0+1 =1

So If ((a<b) $$(c= =0)) than d= 1

If any one condition false than it go level X, so if both condition
it is true than it
add $ t4= 0+1
d=1
Answer is A

Q 24.
When a particular high-level language code fragment is compiled, it produces the
following set of machine instructions.
1. MOV R1, #j // R1⃪ j
2. BEQZ R1, label // if R1 is equal to zero then jump to label
3. MOV R2, #0 // R2⃪ 0
4. JMP exit // unconditional jump to exit
5. label :MOV R2, R3 // R2⃪ R3
6. exit: HALT // Stop
Assuming that values p and q are stored in registers R2 and R3 respectively, to
which high-level language code fragment does the above machine code closely
correspond?
(a) if (j  0) p = q; else p = 0;
(b) if (j ==0) q = p; else q = 0;
(c) if (j ==0) p = q; else p = 0;
(d) if (j == 0) p = 0; else p = q;
Answer : (c)

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 Solution

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For the next four questions, consider the following program segment. Here R1, R2
and R3 are the general purpose registers.
1. MOV R1, (1000) // R1 ←M[1000]
2. MOV R2, (R3) // R2 ←M[R3]
3. LOOP: ADD R2, R1 // R2 ← R1 + R2
4. MOV (R3), R2 // M[R3] ← R2
5. INC R3 // R3 ← R3 +1
6. DEC R1 // R1 ← R1 - 1
7. BNZ LOOP // Branch on not zero
8. HALT // Stop
Assume that memory location 1000 contains 100 and the base address of array is
store in register R3 and the base address of array is 500. All the number is in
decimal.
Memory
500 501 502 503 … 599 600
Location
Contain 100 100 100 100 … 100 100
Q 25.
After the completion of this program, the content of memory location 599 is: _____
Answer :(5150)
Solution:
R1=100
R2 =100
R2 =100+100=200
Move(R3),R2 =200
R3 = R3 +1(point to the next location)
R1 = 99
their process is done until R1 become 0
100+(100+99+98+………)
100∗101
100+
2
100+5050
5150
Answer is 5150

Q 26.
The content of memory location 600 is: ______________________________
Answer :(100)
Solution:
This loop execute frame memory location 500 to 599 R1=0
So (600) memory location value is 100.
Answer is 100

Q 27.
How many times the instruction of program is executed:_________

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 Answer : 503
Solution:
Number of time instruction of program is executed is 2 + 5 x 100 + 1 = 503
Answer is 503

Q 28.
The number of memory references for accessing the data in executing the program
completely is:__________
Answer :(102)
Solution:
Two memory reference for first two instructions and 100 memory reference for
3rd instruction.
2+100*1
=100+2=102
Answer is 102

Q 29.
Consider the following assembly code.
1. Loop: STLI t0, s0, 10 //Set on less than immediate if s0 < 10 then t0 = 1;
2. BEQ t0, zero, exit // if t0 is equal to zero then jump to exit
3. SLL t1, s0, 2 // shift logically left s0 by 2 and store in t1
4. ADD t1, t1, s2 // t1 = t1+ s2
5. ADD t2, s1, s0 // t2 = s1 + s0
6. SW t2, 0(t1) // Mem[t1+ 0] = t2
7. ADDI s0, s0, 1 // s0 = s0 + 1
8. JMP Loop // jump to loop
9. exit: // stop
Assume that the variables a and b are assigned to registers s0 and s1 respectively
and the base address of the array D is in register s2. The initial value of variable a
and b is 0 and 10 respectively. what is the value of s0 register after the execution
of given code? _____
Answer :- 10
Solution:
$s0= a, $ s1=b
$S2=d
a=0
b=10
$ s0=0 $s1=10
0<10
$ t0=1
BEQ t0 =0
1=0(Condition false)
$90 = Shift by 2 bit
$t1=0
t1= $t1+ $t2= (Contain base address of D)
$ t2 = 10

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 D=10
$ s0= 0+1=1
JMP loop , and loop execute until value of $s0 =10
S0 at the end $ s0 =10
Answer is 10
For the next two questions, consider the following program segment. Here R1, R2
and R3 are the general purpose registers.
Instructions Meaning
1. LOAD R1, (R0) R1M[[r0]]
2. ADD R1, R2 R1 R1+R2
3. AND R3, R2 R3R3&& R2
4. ADD R3, R4 R3R3+R4
5. LOAD (R0), R3 M[[R0]] R3
6. SUB R1, R3 R1R1-R3
7. HALT HALT
8. OR R2, R1 R2R2|| R1
9. ADD R2, R1 R2R2+R1
Suppose this processor has 32-bits Load/Store instruction, 16-bits ALU, BRANCH
and HALT instructions. Program has been loaded in the memory with a starting
address of 1000 (in decimal). Assuming the memory is word addressable and word
size is 16 - bits.

Q 30.
If an interrupt occurs during the execution of the instruction “HALT”, what return
address will be pushed on to the stack? __________________
Answer :( 1009)
Solution: Memory with a starting address =1000
Load and store operation = 32/8= 4byte
=2 word.
And ALU = 16 bit =2 byte =1 word
halt instruction = 16 bit =2byte =1 word.
Instruction Words
Instruction Meaning
No.
I1 LOAD R1, (R0) R1M[[r0]] 2
I2 ADD R1, R2 R1 R1+R2 1
R3R3&& 1
I3 AND R3, R2
R2
I4 ADD R3, R4 R3R3+R4 1
LOAD (R0), 2
I5 M[[R0]] R3
R3
I6 SUB R1, R3 R1R1-R3 1
I7 HALT HALT 1
I8 OR R2, R1 R2R2|| R1 1

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 I9 ADD R2, R1 R2R2+R1 2

Interrupt occurred at the time of HALT instruction so HALT instruction is

executed and return the address of next instruction
1000+(2+1+1+1+2+1+1)
1000+9
1009
Answer is 1009

Q 31.
Let the clock cycles required for various operations be as follows:
Clock
Instruction Type
Cycles
Register to/from memory transfer 3
ADD/SUB with both operands in
2
register
AND/OR with both operands in
1
register
If the instruction fetch and decode takes 2 clock cycles per word, what will be the
total number of clock cycles required to execute the program___

Answer: 31

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 Solution:
Word Cycles = Number of words x clock
INo. Instruction Meaning s cycles per word + number of cycles to
perform operations
I1 LOAD R1, (R0) R1M[[r0]] 2 2*2+ 3 = 7
I2 ADD R1, R2 R1 R1+R2 1 2*1+2=4
I3 AND R3, R2 R3R3&& R2 1 2 * 1 +1=3
I4 ADD R3, R4 R3R3+R4 1 2 * 1 +2=4
I5 LOAD (R0), R3 M[[R0]] R3 2 2*2+3=7
I6 SUB R1, R3 R1R1-R3 1 2 * 1 +2=4
I7 HALT HALT 1 2 * 1=2
Total 9 31

Because halt instruction need cycle only for fetch and decode instruction and after
HALT instruction execution of program terminated therefore I8 and I9 will not
execute.
Answer is 31
For the next two questions, Consider the following program segment. Here R1, R2
and R3 are the general-purpose registers.
Instruction size (no. of
Instruction Operation
words)
MOV R1,
R1 ← m[3000] 2
(3000)
LOOP: MOV R2, (R3) R2 ← M[R3] 1
ADD R2, R1 R2 ← R1 + R2 1
MOV (R3), R2 M[R3] ← R2 1
INC R3 R3 ← R3 +1 1
DEC R1 R1 ← R1 - 1 1
Branch on not
BNZ LOOP 2
zero
HALT Stop 1
Assume that the content of memory location 3000 is 10 and the content of the

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 97

register R3 is 2000. The content of each of the memory locations from 2000 to 2010
is 100. The program is loaded from the memory location 1000. All the numbers are
in decimal. Assume that the memory is word addressable.
Q 32.
The number of memory references for accessing the data in executing the program
completely is_________
Answer : (21)
Solution:
1st memory reference R1←m[3000] and then in the loop which runs for 10
times,
because the content of memory location 3000 is 10 given in question and loop
will
run 10 times.. There are two memory reference R2 ← M[R3], M[R3] ← R2 every
iteration (each MOV is loading 1 word, so 1 memory reference for each MOV
inside the loop), therefore 10*2=20 memory accesses inside the loop, one
memory
access is outside the loop for the first instruction. So total=20+1=21.

Q 33.
Assume that the memory is word addressable. After the execution of above
program, the content of memory location 2010 is__________
Answer : 100
Solution :

Q 34.
A processor has 40 distinct instruction and 24 general purpose registers. A 32-bit
instruction word has an opcode, two registers operands and an immediate
operand. The number of bits available for the immediate operand field is (if fixed
size instruction format is used) _____.
Answer :( 16)
Solution:

24 general purpose register need 5 bit

40 distinct operation require = 6 bit for opcode
number of bit for immediate operand =
32-(6+5+5)=32-16=16
Answer is 16
Q 35.
There are 50 registers and total 55 instructions available in a general-purpose
computer. The computer allows only 2-address instructions, where one operand is
a register and another is a memory location. The memory is byte addressable with
64KB in size. The minimum number of bits to encode the instruction will be _____.
Answer :( 28)
Solution:
Total registers = 50; hence number of bits required to represent one register
will be 6 as 50 < 26. Total instructions = 55; hence again 6 bits will be
required to represent an instruction. Total memory = 64KB = 216 B; hence

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 16 bits will be required to represent a memory location. An instruction has
two parts, Opcode and Operand. In this problem there are only 2-address
instructions, out of which one is register operand and other is memory
operand. Hence total bits will be: 6 (opcode) + 6 (register operand) + 16
(Memory operand) = 28 bits

For next three questions consider the system that has a memory unit with 16 bits
per word. The instruction set consists of 200 different operations. All instructions
have an operation code part (opcode) and an address part (allowing for only one
address). Each instruction is stored in one word of memory.
Q 36.
How many bits are needed for the opcode? _________
Answer :(8)
Solution
200 different operations so 8 bits required for opcode .
All instructions have an operation code an address part.
Each instruction size is one word & one word is 16 bit long
Opcode address part
8 bit 8 bit
16 bit

Q 37.
How many bits are left for the address part of the instruction? ___________
Answer :( 8)
Number of bits left for the address part
= total – opcode bit
=16-8
=8 bits
Answer :8

Q If
38.the memory is byte addressable then the maximum allowable size for memory (in
bytes) is _____
Answer : (256)
Solution
Address part is 8 bit long so maximum allowable size for memory =28 bytes =256
For next two questions, suppose a 32-bit instruction uses register addressing mode
with the following format:
OPCODE DEST SRC1 SRC2
Assume that there are 242 opcodes in the instructions set and 64 registers in register
set

Q 39.
The minimum number of bits required to represent the opcodes is_______
Answer : (8)
Number of operation =242
So 8 bit required for opcode
Number of register =64

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 So 6 bit required for register
8 bits 6 bits 6 bits 6 bits
OPCODE DEST SRC1 SRC2

Answer :- 8
Q 40.
Let the minimum number of bits required to represent the SRC1, SRC2 and
DEST registers are x, y and z respectively, then the value of x+y+z is _______
Answer : (18)
Solution
X=6
Y=6
Z=6
x+y+z= 6+6+6= 18
Q 41.
Consider a processor with 64 registers and an instruction set of size twelve. Each
instruction has five distinct fields, namely, opcode, two source register identifiers,
one destination register identifier, and twelve-bit immediate value. Each
instruction must be stored in memory in a byte-aligned fashion. If a program has
100 instructions, the amount of memory (in bytes) consumed by the program text
is ________.
Answer :-500
Solution:
4 6 6 6 12
Opcode SR1 SR2 DR1 immediate

64 register = 6 bit is required

for instruction set of size 100
Number of bit required =7
instruction size (in bit) = (12+6+6+6+4)
=33 bit =40 bit
5 byte
and for single instruction , instruction size is 5 byte
so for 100 instruction = 5*100 =500 byte
Answer is 500 byte
Q 42.
A computer uses extensible opcode technique. It has 16-bit instructions which
have 6-bits address field. It supports one address, two address instructions only.
If there are eight two address instructions, then the maximum numbers of one
address instructions are_______
Answer :( 512)
Solution:

16- (6+6)=16-12=4
Type 2

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 Type1
Total instruction= 24=16
16-8=8
So maximum number of one address instruction
8*26 = 64* 8 =512
Answer is 512
For the next four questions, in a computer instruction format, the instruction
length is 11 bits and the size of an address field is 4 bits. The computer support:
 2-address instructions
 1-address instructions
 0-address instructions
All three type of instruction must be exist in the computer (i.e. there is at least one
instruction from each type)
Q 43.
What is the maximum number of instruction with 0-address?________________
Answer : (1776)
Solution:

Total number of instruction = 23 = 8

Maximum number of instruction with 0 address , 0 address means both of the

address is free.
000 Type 2
001 Type1
In type 1 one address is free remaining 15 instruction we use as a zero address
instruction
15*24+6*24 *24
=1776
Answer is 1776

Q 44.
What is the maximum number of instruction with 1-address?________________
Answer : (111)
Solution:
Maximum number of instruction with one address
000 for Type 2 , remaining 7 for Type1.

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 6* (24) +1*15

one address 1111 to used as a 0 address.

So maximum number of Type 1 address
6*16+15
=111
Answer is 111

Q 45.
What is the maximum number of instruction with 2-address?________________
Answer : (7)
Solution:
Maximum number of introduction with 2 address 7, one instruction is used for
Type1 and one from type 1 used as a type 0.
So maximum number of 2 address introduction =7
Answer is 7

Q 46.
How many maximum number of instruction supported by this computer?_______
Answer :- 1778
Solution:
Maximum number of instruction
1+1+15*16+6*28
Remaining instruction is 7.
1 used as a Type 1 (and remaining 15 used as a Type 0)
and 6 as a type 0
=1778
Answer is 1778

Q 47.
Consider a machine with x bits long instruction and 8 registers. We need to use 3
bits to specify a unique register. Suppose machine encode the following class of
instructions:
Class A: 4 instructions with 2 registers
Class B: 255 instructions with 1 register
Class C: 16 instructions with 0 registers

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 The minimum value of x in the extensible opcode technique to encode the above
class of instruction is______
Answer : 12
Solution

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For next two questions,consider the machine in which instructions are 12 bits in
length and addresses are 4 bits in length. There are 3 classes of instructions:
Class A: 2 addresses
Class B: 1 address
Class C: 0 addresses
All three type of instruction must be exist in the computer (i.e. there is at least one
instruction from each type)
Q 48.
What is the maximum total number of instruction possible in machine?_________
Answer :-( 3826)
Solution

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Q 49.
What is the minimum total number of instruction possible in machine?__________
Answer :46
Solution
Minimum number of instruction possible in machine when two address
instructions
Minimum ,
Opcode Address1 Address 2
4 bit 4bit 4 bit
0-14 r1 R2
15 0-14 r1

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 15 15 0-15

Minimum = 1 5 + 15+ 1 6

Two address one address zero address

=46
Ans:46

Q 50.
Consider a machine where each instruction is 4 bytes long. Conditional and
unconditional branch instructions use PC-relative addressing mode with Offset
specified in bytes to the target location of the branch instruction. Also, the Offset
is always with respect to the address of the next instruction in the program
sequence. Consider the following instruction sequence:
Instruction i: DD R2,R3,R4
Instruction i+1: SUB R5,R6,R7
Instruction i+2: SEQ R1,R9,R10
Instruction i+3: ADD R1, R2, R3
Instruction i+4: BEQZ R1, Offset
If the target of the branch instruction is i, the decimal value of Offset will be______
Answer : (-20)
Solution
Assume that instruction “i” starts from memory address X.
Address of instruction i+1 = X + 4
Address of instruction i+2 = X + 8
Address of instruction i+3 = X + 12
Address of instruction i+4 = X + 16
Address of instruction i+5 = X + 20
So, Offset = X – (X + 20) = -20

INSTRUCTION PIPELINE

For next six questions, suppose we have the following functional units with the
given
latencies in a processor:
IF 2 ns
ID 2 ns
EX 3 ns
MEM 6 ns
2 nsWB
Q 1. If we use these units to build a single-cycle implementation (non-pipeline),
what is the cycle time (in ns) of pipeline processor?_________
Answer :-15
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 Single –cycle implementation means, every phase will execute in one cycle
only (non-pipeline )
1 instruction takes : 2+2+3+6+1=15ns

Q 2. How long (in ns) does it take to execute a single instruction in non-pipeline
processor?_________

Q 3. If we use these units to build our usual 5-stage pipeline processor, what is the
cycle time of pipeline processor?_________
Answer :-6
Shortest possible cycle time should be the largest phase time so the
other phases can adjust with its time . 6ns
Q 4. How long (in ns) does it take to execute a single instruction in pipeline
processor?________

Q 5. How long does it take to execute N instructions using this pipeline, where N is
some arbitrary large number?
(a) (6N) ns (b) (6 × 5+(N – 1) × 6) ns
(c)6 × (4+N) ns (d)Both(b)&(c)
Answer :- (D)
5* 6+(n-1)*6

No of stages * phase time +(no .of instructions -1)*phase time
5*6+6*n-6
6*n+4*6
6(n+4)

Q 6. What is the speedup of this pipelined processor over the non-pipeline

processor?_
Answer :2.5
non −pipeline time 𝟏𝟓
= =2.5
pipeline time 𝟔

For next three questions, consider a 5-stage processor with the following

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latencies:
Fetch Decode Execute Memory Write back
300ps 400ps 350ps 550ps 100ps
Assume that when pipelining, each pipeline stage costs 20ps extra for the registers
between pipeline stages.
Q 7. What is the cycle time for non-pipelined processor and what is the latency of an
instruction?
(a) 550ps, 2750ps (b) 570ps, 2850ps
(c) 1700ps, 1700ps (d) 1800ps, 1800p
Answer :- c
Solution:
Buffer delay = 20 ps.
Cycle time in non pipeline = sum of cycle time of all phase.
= 300+400+350+550+100
=1700ps.
Phase time = 550+20
=570
Latency in non pipeline:-
Latency means i/p to O/P time = Sum of cycle
=1700ps.
Answer is C

Q 8. What is the cycle time for pipelined processor and what is the latency of an
instruction?
(a) 550ps, 2750ps (b) 570ps, 2850ps
(c) 550ps, 2850ps (d) 1800ps, 1800ps
Answer :- B
Solution: In pipeline, phase time= 550+20 = 570 ps.
In pipeline phase time = Cycle time
Latency in pipeline = 570*5= 2850ps.
Answer is B

Q 9. What is the throughput (in MIPS) of the non-pipelined and pipelined

respectively?
(a) 588.24, 1754.39 (b) 555.56, 1754.39
(c) 555.56, 1818.18 (d) 588.24, 1818.18
Answer :- a
1700 ps 1
1
11700 *1012
10 6
MIPS
1700
= 588.235≅ 588.24 MIPs
In Pipeline:-
570ps
570*1012 1

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 10 12
1 570 =1754.385MIPS
≅ 1754.39
Answer is A

Q 10. Comparing the time T1 taken for a single instruction on a pipelined CPU with
time T2 taken on a non-pipelined but identical CPU, we can say that
(a) T1 ≥ T2
(b) T1 ≤ T2
(c) T1 < T2
(d) T1 is T2 plus the time taken for one instruction fetch cycle

Q 11. A non pipelined single cycle processor operating at 100 MHz is converted into
a synchronous pipelined processor with five stages requiring 1nsec, 1.5nsec,
4nsec, 3nsec, and 0.5nsec, respectively. The speedup of the pipeline processor
for a large number of instructions is____________
Answer :- 2.5
Non –pipeline cycle time =10ns
Pipeline cycle time =largest phase time =4 ns
Assuming CPI=1 for pipeline
Speedup =10/4= 2.5
Q 12. A non pipelined single cycle processor operating at 100 MHz is converted into
a synchro-nous pipelined processor with five stages requiring 2.5nsec, 1.5nsec,
2nsec, 1.5nsec and 2.5nsec, respectively. The delay of the latches is 0.5nsec.
The speedup of the pipeline processor for a large number of instructions is
(a) 4.5 (b) 4.0
(c) 3.33 (d) 3.0

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Q 13. Consider a 5-stage single cycle machine (non-pipeline), and a 5-stage pipeline
machine. The cycle time of the non-pipeline is five times that of pipeline.
Assume that there are no stalls in the pipeline. What is the speedup achieved
over non-pipeline if pipeline phase time is 2 ns? _______
Answer :- 5
For non-pipeline cycle is five times more than that of pipeline cycle time.
Cycle time for pipeline is 2 ns
cycle time for non-pipeline =10 ns
Speedups=10/2=5 ns

Q 14. A pipeline P operating at 1 GHz has a speedup factor of 5 and operating at 60%
efficiency. How many stages are there in the pipeline?_______
Answer :- 8
Solution:
𝑆𝑝𝑒𝑒𝑑 𝑢𝑝
=𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑠𝑡𝑎𝑔𝑒𝑠
60 5
=100 = 𝑘
.25
k= = 8.33
3
=8 stages.
Answer is 8 stages

Q 15. Consider two different machines; the first has a single cycle data path i.e., a
single non pipelined machine with a cycle time of 4 ns. The second is a
pipelined machine with four pipeline stages and a cycle time of 1 ns. What is
the speedup of the pipeline machine versus the single cycle machine for the
very large number of instructions?__________
Answer ;-4
4 𝑛𝑠
The speedup is =4
1 𝑛𝑠

Q 16. In a 5-stage pipelined system, assume that stages 1 and 4 take 2ns each,
stages 2 and 5 take 3ns each, and stage 3 takes 1ns. What is the speed-up
attained for the pipelined system as compared to the non-pipelined system, if
BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 110
 50 instructions are executed?
(a)2.500
(b)3.333
(c)3.395
(d)3.667
Answer :-C

S1 S2 S3 S4 S5
2ns 3ns 1ns 2ns 3ns
Non –pipeline : 11x50=550
Pipeline =3x5+3x49=162
550
Speedup = =3.395
162

Q 17. Suppose the four stages in a 4-stage pipeline take the following timing: 2ns,
3ns, 4ns, and 2ns. Given 1000 instructions, what is the speedup of the
pipelined processor compared to the non-pipelined single-cycle
processor?__________
Answer :- 2.741
Non –Pipeline processor will take
(2ns+3ns+4ns+2n)*1000 time to execute 1000 instruction, i.e
11000 ns
Pipeline processor, will select its cycle times as the largest phase time i.e 4
ns
Each instruction of this processor will take 4 ns,
We have 1000 instruction
Total time =4x4+999*4=4000 ns
11000
Speedup = =2.741
4012

Q 18. The five stages of a certain pipeline take 2 ns, 3 ns, 4 ns, 5 ns, and 2 ns. If
there are 20 instructions, what is the maximum speed up in the execution time
of a pipeline implementation compared to a single-cycle implementation?
(a) 2.50 (b) 2.67
(c) 5.00 (d)3.20
Answer :- B
Cycle time of single –cycle processor
2+3+4+5+2=16ns
Cycle time of pipeline=largest phase time
=5ns
Now to execute 20 instructions:
Non pipeline=20x16
= 320 ns

Pipeline time=1stinst all stages +other instruction only 1 cycle

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 111
 5*5+19*5
120 ns
320
Speedup 2.67
120

Q 19. Consider the 5 stages of the processor have the following latencies:
Fetch Decode Execute Memory Write back
300ps 400ps 350ps 500ps 100ps
Assume that when pipelining, each pipeline stage costs 20ps extra for the
registers between pipeline stages. If you could split one of the pipeline stages
into 2 equal halves, which one would you choose?
(a) Write back (b) Fetch
(c) Decode (d) Memory
Answer :- d
we would chose memory phase because then the new cycle time will be
reduced to
400 ps.
Q 20. The stage delays in a 5-stage pipeline process are 800nsec, 400nsec, 900nsec,
400nsec and 300nsec, respectively. The third stage is replaced with a
functionality equivalent design involving three stages with respective
delays 550nsec, 350nsec and 350nsec. What will be change in the throughput
of the pipeline processor?
(a) It is increases by 12.5%
(b) It is decreases by 12.5%
(c) It is increases by 12.25%
(d) It is decreases by 12.25%
Answer: (a)
Solution:
Throughput = 1/(CPI x Cycle Time) = 1/(CPI x (1/Frequency) = Frequency/CPI
= 1/(CPI x Largest Phase Time)
Throughput of old processor = 1/(CPI x 900 ns) = 1/(900 x 10^-9) = 10^9/900
and Throughput of new processor = 1/(CPI x 800 ns) = 1/(800 x 10^-9) =
10^9/800
% Increase in throughput
1 1
∗10 9 − ∗10 9
= 800
1
900
∗10 9
900
900−800 1
= 109 ( )* *109
7200 900
100∗900 900
= = =12.5*100
7200 72
= 12.5% increase
Answer is A
Q 21. The stage delays in a 4 stage pipeline are 800, 500, 400 and 300 picoseconds.
The first stage is replaced with a functionally equivalent design involving two
stages with respective delays 600 and 350 picoseconds. The throughput
increase of the pipeline is _____%.

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For the next two questions,Consider a system in which it takes 8 cycles to complete
execution of instruction and clock period is 0.5 ns.
Q 22. What is the Clock frequency of the machine? ____________GHz
Answer :- 2
1
Frequency = 𝐶𝑙𝑜𝑐𝑘 𝑡𝑖𝑚𝑒
1
= 0.5∗10 −9
1
= ∗ 109 GHz
0.5
= 2 GHz
Answer is 2

Q 23. What is the total number of instructions per second executed by system (in
million)? ____
Answer:- 250
Solution: It take 8 cycle to complete the execution of program
=8* cycle time
=8*0.5ns
=4ns
4ns  1
4*10-91
10 9
1sec 4
10 6
= ∗ 103
4

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 =250 MIPS
Answer is 250

Q 24. If a non-pipelined processor had a maximum clock rate of 500 MHz and was
converted to a perfectly balanced 10-stage pipeline, what would the pipelined
processor‟s maximum clock rate be?
(a) 0.5 GHz (b) 500 GHz (c) 5 GHz (d)
50 GHz
Answer :- c
1
Cycle time of Non Pipeline = =2ns
500
2
Cycle time of P = =0.2ns
10
1
Clock frequency/clock rate = GHZ
.2
5 GHZ.

Q 25. A single-cycle processor design with a 1 GHz clock is converted to a ten-stage,

perfectly balanced, pipelined design. What will be the clock period of the new
design?
(a) 0.1 GHz (b) 10 GHz (c) 1000 GHz (d) 100 GHz
Answer : b
10GHz
Cycle time of single-cycle processor
1
sec or 1ns
1 ∗ 10 9
When its converted to 10 stage pipeline its cycle time become
1𝑛𝑠
=0.1ns
10
The clock period of new design will
1
HZ
0.1  10 −9
10 GHz

Q 26. Consider a non-pipelined processor with a clock rate of 2.5 GHz and average
cycles per instruction of 5. The same processor is upgraded to a pipelined
processor with five stages but due to the internal pipeline delay, the clock
speed is reduced to 2 GHz. Assume there are no stalls in the pipeline. The
speed up achieved in this pipelined processor is______

BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 114

Q 27. A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode
(ID), Instruction Execution (IE), Memory Access (MA) and Write Back (WB)
stages. All stages take 1 clock cycle each for any instruction. Consider the
following code fragment:
Instruction Meaning of instruction
Load R1, [1000] // R1 = M[1000]
Load R3, 5(R2) // R3 = M[R2 + 5]
MUL R4, R1, R6 // R4 = R1 x R6
DIV R5, R1, R6 // R5 = R1 / R6
SUB R6, R2, R7 // R6 = R2 – R7
What is the number of clock cycles needed to execute the above sequence of
instructions on 5-stage pipeline processer? ______

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Q 28. A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode
(ID), Instruction Execution (IE), Memory Access (MA) and Write Back (WB)
stages. All stages take 1 clock cycle each for any instruction. Consider the
following code fragment:
Instruction Meaning of instruction
Load R1, [1000] // R1 = MEM[1000]
Load R3, 5(R2) // R3 = MEM[R2 + 5]
MUL R4, R1, R3 // R4 = R1 x R3
DIV R5, R1, R4 // R5 = R1 / R4
SUB R6, R4, R5 // R6 = R4 – R5
What is the number of clock cycles needed to execute the above sequence of
instructions on 5-stage pipeline processer? _____

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Q 29. A 5-stage classical pipelined processor has Instruction Fetch (IF), Instruction
Decode (ID), Instruction Execution (IE), Memory Access (MA) and Write Back
(WB) stages. All stages take 1 clock cycle each for any instruction. Consider the
following code fragment:
Instruction Meaning of instruction
MOV R3, R7 // R3←R7
LD R8, (R3) // R8 = MEM[R3]
ADD R3, R3, 4 // R3 = R3 + 4
LOAD R9, (R3) // R9 = MEM[R3]
What is the number of clock cycles needed to execute the above sequence of
instructions on 5-stage pipeline processer? _____

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Q 30. A 5-stage classical pipelined processor has Instruction Fetch (IF), Instruction
Decode (ID), and Instruction Execute (EX), Memory Access (MA) and Write Back
(WB) stages. The IF, ID, MA and WB stages take 1 clock cycle each for any
instruction. The EX stage takes 1 clock cycle for ADD and SUB instructions, 3
clock cycles for MUL instruction, and 6 clock cycles for DIV instruction
respectively. Consider the following sequence of instructions:
Instruction Meaning of instruction
I0:MUL R2 ,R0 ,R1 R2 ← R0 *R1
I1:DIV R5 ,R3 ,R4 R5 ← R3/R4
I2: ADD R2 ,R5 ,R2 R2 ← R5 + R2
I3:SUB R5 ,R2 ,R6 R5 ← R2 - R6
What is the number of clock cycles needed to execute the above sequence of
instructions? ______

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Q 31. Consider a pipelined processor with the following four stages: Instruction Fetch
(IF), Instruction Decode and Operand Fetch (ID), Instruction Execute (EX), and
Write Back (WB). The IF, ID and WB stages take one clock cycle each to
complete the operation. The number of clock cycles for the EX stage depends
on the instruction. The ADD and SUB instructions need 1 clock cycle, the MUL
instruction needs 3 clock cycles and the DIV instruction needs 5 clock cycles in
the EX stage respectively. Consider the following sequence of instructions:

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 Instruction Meaning of instruction
I0: MUL R2 ,R0 ,R1 R2 ← R0 * R1
I1: DIV R5 ,R3 ,R4 R5 ← R3 / R4
I2: ADD R2 ,R5 ,R2 R2 ← R5 + R2
I3: SUB R5 ,R2 ,R6 R5 ← R2 - R6
What is the number of clock cycles taken to complete the following sequence of
instructions?_________

Q 32. The instruction pipeline of a RISC processor has the following stages:
Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform
Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock
cycle each for every instruction. Consider a sequence of 100 instructions. In
the PO stage, 30 instructions take 3 clock cycles each, 30 instructions take 2
clock cycles each, and the remaining 40 instructions take 1 clock cycle each.
Assume that there are no stalls in the pipeline. The number of clock cycles

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 required for completion of execution of the sequence of instructions is ______.

Q 33. A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode
(ID), Instruction Execution (IE), Memory Access (MA) and Write Back (WB)
stages. All stages take 1 clock cycle each for any instruction. Consider the
following code fragment:
Instruction Meaning of instruction
I1: LOAD R2, 0(R1) // R2 = MEM[R1+0]
I2: LOAD R1, 40(R3) // R1 = MEM[R3 + 40]
I3: SUB R3, R1, R2 // R3 = R1 - R2
I4: ADD R3, R2, R2 // R3 = R2 + R2
I5: OR R4, R3, 0 // R4 = R3 || 0
I6: STORE R3, 50(R1) // MEM[R1+50] = R3
What is the number of clock cycles needed to execute the above sequence of
instructions on 5-stage

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Q 34. A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode
(ID), Instruction Execution (IE), Memory Access (MA) and Write Back (WB)
stages. All stages take 1 clock cycle each for any instruction. Consider the
following code fragment:
Instruction Meaning of instruction
I1: LOAD R2, 0(R1) // R2 = MEM[R1+0]
I2: LOAD R1, 40(R3) // R1 = MEM[R3 + 40]
I3: SUB R3, R1, R2 // R3 = R1 - R2
I4: ADD R3, R2, R2 // R3 = R2 + R2
I5: OR R4, R3, 0 // R4 = R3 || 0
I6: STORE R3, 50(R1) // MEM[R1+50] = R3
What is the number of clock cycles needed to execute the above sequence of
instructions on 5-stage pipeline processer without operand forwarding but
theregister file can be read and written in the same cycle. The write takes place
duringthe first half of the cycle and the read takes place during the second half
of thecycle? ______
Answer :- 14

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Q 35. A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode
(ID), Operand Fetch (OF), Perform Operation(PO)and Write Operand(WO)stages.
The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The
PO stage takes 2 clock cycles for ADD and SUB instructions, 5 clock cycles for
MUL instruction, and 6 clock cycles for DIV instruction respectively. Assume
no operand forwarding but a split-cycle register file (i.e. the register file can be
read and written in the same cycle.) is in used.
Instruction Meaning of instruction
I0: MUL R2, R0, R1 //R2 ← R0 *R1
I1: DIV R5, R3, R4 //R5 ← R3/R4
I2: ADD R2, R5, R2 //R2 ← R5+R2
I3: SUB R5, R2, R6 //R5 ←R2-R6
What is the number of clock cycles needed to execute the following sequence of
instructions?_______
Answer :-21
Solution: Dependency between I0 and I1
I2&I3

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 =21
Answer is 21

I ID OF PO WO
I0
I1 I0
I2 I1 I0
I3 I2 I1 I0
I3 I2 I1 I0
I3 I2 I1 I0
I3 I2 I1 I0
I3 I2 I1 I0
I3 I2 I2 I1 I0
I3 I2 I1
I3 I2 I1
I3 I2 I1
I3 I2 I1
I3 I2 I1
I2 I1
I3 I2
I3 I2
I3 I2
I3
I3
I3
Q 36. Consider a 2GHz pipelined processor with the following four stages: Instruction
Fetch (IF), Instruction Decode and Operand Fetch (ID), Execute (EX) and Write
Back (WB). The IF, ID and WB stages take one clock cycle each to complete the
operation. The number of clock cycles for the EX stage depends on the
instruction. The ADD and SUB instructions need 2 clock cycle and the MUL

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 instruction needs 5 clock cycles in the EX stage.
Instruction Meaning of instruction
ADD R2, R1, R0; //R2+Rl→R0
MUL R0, R3, R4; //R0*R3→R4
SUB R4, R5, R6; // R4 – R5 → R6
Operand forwarding is not used in the pipelined processor. What is the time (in
ns) to complete the above instruction? ______

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Q 37. Consider the ideal five stage in-order pipelining processor and the following
sequence of instructions is executed on the processor:
Instruction Meaning of instruction
ADD R1, R2, R3 // R1 ← R2 + R3
SUB R4, R5, R6 // R4 ← R5 – R6
SUB R7, R8, R9 // R7 ← R8 + R9
ADD R10, R11, R12 // R10 ← R11 + R12
ADD R13, R14, R15 // R13 ← R14 + R15
During the fifth cycle of execution, which registers (in the register file) are being
read and which register will be written?
(a) Written: R1; Read: R12, R11
(b) Written: R1, R12; Read: R11
(c) Written: R11; Read: R12
(d) Written: None; Read: R12, R11

Q 38. Consider the ideal five stage in-order pipelining and the following sequence of
instructions is executed on the processor:
Instruction Meaning of instruction
LW R1, 0(R0); // R1 = MEM[0 + R0]
LW R2, 4(R0; // R2 = MEM[4 + R0]
ADD R3, R1, R2; // R3= R1 + R2
SW R3, 8(R0); // MEM[8+R0] = R3
LW R4, 12(R0); // R4 = MEM[12 + R0]
ADD R5, R3, R4; // R5 = R3 + R4
SW R5, 16(R0); // MEM[16+R0] = R5
The number of RAW, WAR and WAW data dependencies exist in this code
respectively is
(a) 5, 1, 2
(b) 6, 0, 2

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 (c) 4, 1, 1
(d) 6, 0, 0

Q 39. Consider the ideal five stage in-order pipelining processor and the following
sequence of instructions is executed on the processor:
Instruction Meaning of instruction
ADD R1, R2, R3 // R1 ← R2 + R3
ADD R4, R2, R1 // R4 ← R2 + R1
LW R5, 0(R4) // R5 ← MEM[200 + R4]
ADD R4, R5, R4 // R4 ← R5 + R2
If the operand forwarding is not used then how many data dependencies can
create
hazards? _________

Q 40. Consider the ideal five stage in-order pipelining processor and the following
sequence of instructions is executed on the processor:
Instruction Meaning of instruction
LW R1, 40(R2) // R1 ← MEM[40 + R2]
ADD R2, R3, R0 // R2 ← R3 + R0

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 ADD R1, R1, R2 // R1 ← R1 + R2
SW R1, 20(R2) // MEM[20 + R2] = R1
How many ANTI, TRUE and OUTPUT dependencies respectively are there in the
above code?
(a) 1, 3, 1 (b) 1, 4, 1
(c) 1, 3, 2 (d) 1, 4, 2

Answer: (b)
1. LW R1, 40(R2) // R1 ← MEM[40 + R2]
2. ADD R2, R3, R0 // R2 ← R3 + R0
3. ADD R1, R1, R2 // R1 ← R1 + R2
4. SW R1, 20(R2) // MEM[20 + R2] = R1
A Flow dependency, also known as a data dependency or true dependency or
read-after-write (RAW), occurs when an instruction depends on the result of a
previous instruction. An anti dependency, also known as write-after-read
(WAR), occurs when an instruction requires a value that is later updated.An
output dependency, also known as write-after-write (WAW), occurs when the
ordering of instructions will affect the final output value of a variable.
ANTI: (1 and 2)
TRUE: (1 and 3), (2 and 3), (2 and 4) and (3 and 4)
OUTPUT: (1 and 3)
Q 41. Consider the ideal five stage in-order pipelining and the following sequence of
instructions is executed on the processor:
Instruction Meaning of instruction
ADD R4, R2, R3 // R4 ← R2 + R3
SW R2, 100(R6) // MEM[100 + R6] = R2
LW R5, 200(R4) // R5 ← MEM[200 + R4]
SUB R5, R8, R6 // R5 ← R8 – R6
The number of RAW, WAR and WAW data dependencies exist in this code
respectively is
(a) 2,1,1 (b) 1,0,1
(c) 1,1,1 (d) 1,1,0
Answer :- b
RAWI1I3 (R4) 1
WARno dependency 0
WAW I3I4 (R5) 1

Q 42. Consider the ideal five stage in-order pipelining processor and the following
sequence of instructions is executed on the processor:
Instruction Meaning of instruction
ADDi R7, R7, 1 // R7 ← R7 + 1
SLL R8, R7, 2 // Shift R7 logical left by 2 bit
ADD R8, R8, R14 // R8 ← R8 + R14

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 LW R8, 0(R8) // R8 ← MEM[0 + R8]
LW R8, 0(R8) // R8 ← MEM[0 + R8]
BNE R7, R22, TARGET // if R7 ≠ R22 then jump to target
Let the number of RAW, WAR and WAW dependencies exists in the code is x, y
and z respectively, then the value of x + y + z is________

Q 43. Consider a machine that has ideal five stage in-order pipelining processor. The
machine uses delay slots to handle control dependences. The Jump targets,
branch targets and destinations are resolved in the execute stage. What is the
number of delay slots needed to ensure correct operation of pipeline
processor?________

Q 44. Consider a machine that has ideal five stage in-order pipelining processor.
BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 129
 Instruction Meaning of instruction
I1. ADD R5, R4, R3 // R5 ← R4 + R3
I2. OR R3, R1, R2 // R3 ← R1 || R2
I3. SUB R7, R5, R6 // R7 ← R5 – R6
I4. Jump X // Jump to lable X
I5. LW R10, (R7) // R10 ←MEM[R7]
I6. ADD R6, R1, R2 // R6 ← R1 + R2
I7. X: HALT
Which instruction(s) in the assembly sequences above would you place in the
delay
slot(s)? Assume that the number of available delay slots is 2.
(a)1st and 2nd instruction
(b) 2nd and 3rd instruction
(c) 2ndinstruction
(c)Delay slot cannot be filled.
Answer :- b
ADD R5← R4, R3
Jump X
OR R3 ← R1, R2
SUB R7 ← R5, R6
LW R10 ← (R7)
Add R6← R1,R2
X:
OR R3 ← R1, R2

Q 45. Consider a machine that has ideal five stage in-order pipelining processor.
Instruction Meaning of instruction
I1. ADD R5, R4, R3 // R5 ← R4 + R3
I2. OR R3, R1, R2 // R3 ← R1 || R2
I3. SUB R7, R5, R6 // R7 ← R5 – R6
I4. BEQ R5, R7, X // if R5 == R7 then jump to x
I5. LW R10, (R7) // R10 ←MEM[R7]
I6. ADD R6, R1, R2 // R6 ← R1 + R2
I7. X: HALT
Which instruction(s) in the assembly sequences above would you place in the
delay slot(s)? Assume that the number of available delay slots is 2.
(a)1st and 2nd instruction
(b) 2nd and 3rd instruction
(c) 2nd only
(d) Delay slot cannot be filled.
Answer :- c
ADD R5← R4, R3
SUB R7 ← R5, R6
BEQ R5 ← R7,X

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 OR R3 ← R1, R2
NOP
LW R10 ← (R7)
Add R6 ← R1,R2
X:
Q 46. Consider a machine that has ideal five stage in-order pipelining processor.
Instruction Meaning of instruction
I1. ADD R2, R4, R3 // R2 ← R4 + R3
I2. OR R5, R1, R2 // R5 ← R1 || R2
I3. SUB R7, R5, R6 // R7 ← R5 – R6
I4. BEQ R5, R7, X // if R5 == R7 then jump to x
I5. LW R10, (R7) // R10 ←MEM[R7]
I6. ADD R6, R1, R2 // R6 ← R1 + R2
I7. X: HALT
Which instruction(s) in the assembly sequences above would you place in the
delay slot(s)? Assume that the number of available delay slots is 2.
(a)1st and 2nd instruction
(b) 2nd and 3rd instruction
(c) 1st Only
(d) Delay slot cannot be filled.
Answer :- d
ADD R2← R4, R3
OR R5 ← R1, R2
SUB R7 ← R5, R6
BEQ R5 ← R7,X
NOP
NOP
LW R10 ← (R7)
Add R6 ← R1,R2
X:

Q 47. Consider a machine that has ideal five stage in-order pipelining processor.
Instruction Meaning of instruction
I1. L1: LOAD R1, 8(R2) // R1 ←MEM[8 + R2]
I2. ADD R3, R1, R8 // R3 ← R1 + R8
I3. SUB R2, R1, R4 // R2 ← R1 – R4
I4. STORE R7, 12(R2) // MEM[12 + R2] = R7
I5. ADD R6, R2, R5 // R6 ← R2 + R5
I6. BEQ R6, R7, L1 // if R6 == R7 then jump to L1
Which instruction(s) in the assembly sequences above would you place in the
delay slot(s)? Assume that the number of available delay slots is 2.
(a) I2 and I4 instruction
(b) I3 and I4instruction
(c) I2 and I3instruction

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 (d)Delay slot cannot be filled.
Answer :- a
Choosing I2 R3 is not used below, R1 &R8 is not manipulated below both
are
reading registers ,it can be filled in the delay slot.
Choosing I4 both R7 &R2 are not manipulated below both are reading
registers ,it can be filled in the delay slot
Q 48. Register renaming solves the problem of:
(a) Name Dependence
(b) Output Dependence
(c) Anti-Dependence
(d) All of the above
Answer :- d
Q 49. [MSQ]
Which of the following statements about pipelining is/are incorrect?
(a) Pipelining reduces the latency of a single instruction.
(b) Pipelining is invisible to the programmer.
(c) Stalling the pipeline is the only method to handle structural hazards.
(d)In pipeline memory reference may cause data hazards.
(e)Bypassing and forwarding eliminates all data hazards.

Q 50. Consider a classical 5 stage pipelined processor executes a program that

consists of 50,000 instructions. Because of hazards 10% of instructions are
stalled by one cycle, 15% by 2 cycles and 10% by 3 cycles. How many cycles
take execution of this program? ______
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Q 51. Consider a 8-stage instruction pipeline, where all stages are perfectly balanced.
Assume that there is no cycle-time overhead of pipelining. When an application
is executing on this 8-stage pipeline, the speedup achieved with respect to non-
pipelined execution if 30% of the instructions incur 2 pipeline stall cycles
is____________

Q 52. Consider a processor with following specifications

Clock Rate 0.5 GHz

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 CPI for ALU instructions 1
CPI for Control instructions 2
CPI for Memory instructions 2.7
The average instruction execution time (in ns) for a program with 70% ALU
instructions, 1% control instructions and 29% memory instructions
is__________ (Rounded off to three decimal places)

Q 53. A program‟s execution time is 100 seconds. Suppose FP instructions account

for 30% of the execution time of the program and multiply instructions account
for 10% of the execution time. How much faster would the program execute if
we speed up FP instructions by a factor of 3 and multiply instructions by a
factor of 5? _________ (Rounded off to three decimal places)
Answer :- 1.389
program execution time=100 sec
FP instructions account for30 %(30sec)
multiply instructions account for 10% (10sec)
Remaining instructions are 60%(60sec)
fpinstructions y a factor of 3 =10 sec
Multiply instructions by a factor of 5 =2 sec
after the factor of FP & multiply take gives 72 sec for program execution.
100/72=1.389

Q 54. Adding a faster floating-point unit to a machine will give a speedup of 5 on FP

instructions. The FP instructions make up 10% of the dynamic instruction
count on the original machine and the average CPI for FP instructions on the
original machine is 9 cycles and the average CPI for all other instructions on
the original machine is 1 cycle. What is the overall speedup of the machine due

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 to this modification?__________ (Rounded off to three decimal places)

For next three questions, consider a program has 109 instructions and 50% of these
instructions are memory instructions. This program is executed on a processor that
runs on a 2-GHz clock, executes the memory instructions in an average 4.0 CPI, and
executes the other instructions in an average 1.0 CPI.
Q 55. What is the overall average CPI of program? ________
Answer :- 2.5
50% of instructions are memory instruction and average CPI for memory
instruction 4.
While remaining instruction in an average 1.0 CPI
Overall average CPI=05x4+.5x1=2.5

Q 56. What is the time needed to execute this program? _______nsec

Answer :- 1.25
Clock Rate =2GHz
Cycle time =1/2 =0.5
Time needed to execute this program = CPI*cycle time * no .of inst.
= 2.5*.5*109
=1.25 seconds

Q 57. What is the speedup when the memory instructions are improved by a factor of
4? ____

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 Answer :-2.5
Now the memory instuction are improved by a factor 4 and the average CPI
for
memory instruction is 4.
Now the CPI of memory instuction =1
Speedup=2.5/1 (form question no 55)=2.5

Q 58. Consider a non-pipelined processor with a clock rate of 5 gigahertz and average
cycles per instruction of four. The same processor is upgraded to a pipelined
processor with five stages; but due to the internal pipeline delay, the clock
speed is reduced to 2.5 gigahertz. Assume that there are no stalls in the
pipeline. The speed up achieved in this pipelined processor is __________.

Q 59. Consider a program running on a 5-stage pipeline processor; assume that 25%
instructions of program cause a single-cycle stall. If forwarding can eliminate
60% of the stalls, but increases the clock cycle by 20%, what is the speedup
obtained by using forwarding? __________
Answer :-0.95
Solution: 1+0.25*1= 1.25cycle
If cycle time= p
So instruction execution time= 1.25*p
=1.25p
If for warding can eliminate 60% of stall , so 40 % has stall
1+0.25*0.4*1
=1.1
and if reduce stall than increasing cycle time by 20%
𝑝∗20
p+ 100
𝑝 6𝑝
p+5 = 5
Average instruction execution time
6𝑝
= 1.1* 5

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 1.25∗𝑝
Speed up= 6𝑝
1.1∗
5
1.25∗5
= 1.1∗6 ≅0.9456 ≅0.95
Answer is 0.95

Q 60. What is the average CPI of a processor with base CPI as 1, if it has 2 branch
delay slots, 20% of the instructions are branches, and the branch delay slots
can be filled only 50% of the time?________
Answer :- 1.2
Assuming base CPI=1
20% of the time we will have to have 2 branch delay slots but 50% of that
time
we can use then that means we u see a CPI increase .2*.5*2=0.2 & then
total
CPL will be 1.2
Q 61. Consider the following code consisting of 100 load instructions in which each
instruction is dependent on the instruction immediately preceding
LW R2, 0(R1)
LW R3, 0(R2)
LW R4, 0(R3)
...
What would the average CPI be for this code in the 5-stage pipelined processor
without forwarding? _______

Q 62. Consider the following code consisting of 100 load instructions in which each
instruction is dependent on the instruction immediately preceding
LW R2, 0(R1)
LW R3, 0(R2)
LW R4, 0(R3)
...
What would the average CPI be for this code in the 5-stage pipelined processor
with forwarding? ________

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Q 63. Assume a processor with instruction frequencies and costs
 Integer ALU: 50%, 1 cycle
 Load: 20%, 5 cycles
 Store: 10%, 1 cycles
 Branch: 20%, 2 cycles
Which change would improve performance more of the processor?
i. Branch prediction to reduce branch cost to 1 cycle.
ii. Faster data memory to reduce load cost to 3 cycles.
(a) (i) will improve performance
(b) (ii) will improve more performance
(c) Both improve same performance
(d) Nothing improved performance

Q 64. Consider two machines M1 and M2. For both machines, all instructions except

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 for mispredicted branches take one cycle. Mispredicted branches take one cycle
plus an additional misprediction penalty.
 Machine A has a clock rate of 1.0 GHz and a misprediction penalty of 5
cycles.
 Machine B has a clock rate of 2.0 GHz and a misprediction penalty of 20
cycles.
Branches are 25% of all instructions and 80% of branches are predicted
correctly. Which of the following statement is correct?
(a) Machine A is faster than Machine B
(b) Machine B is faster than Machine A
(c) Both are same
(d) None of these
Answer :- B
Solution:
Machine A:
1+0.25*2.0*(1+5)
1+0.25*0.20*6
=1.3 x 1 ns
Machine B:1+0.25*0.20*(1+20)
1+1.05=2.05 x 0.5 ns = 1.025
So machine B is faster than machine A
Answer is B

Q 65. Consider a 5-stage pipeline processor with operand forwarding, where branches
are resolved in the 4th stage. A given program consists of 30% loads, 5% stores,
15% branches and 50% ALU operations. If 30% of the branches are not-taken
and only 40% of load instructions are dependent on the instruction in front of
them, what is the expected CPI of the processor on this program?______(round
off to 3 decimal places)

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Q 66. Consider a program with branch frequencies (as percentage of all instructions)
as follows: Conditional branches 15% out of which 60% are taken, Jumps and
calls 1%. This program is executed on a 5-stage pipelined processor where
unconditional branches are resolves at second phase and conditional branches
at the third phase of the pipeline. Assuming that only the branch instructions
results in stall how much faster would the machine be without any branch
hazards? ________
Answer :- 1.19
Solution: 1+0.15*0.6*2+0.01
=1.19
Answer is 1.19

Q 67. Consider that we have a machine with 7-stage pipeline: IF, ID1, ID2, EX, M1,
M2, and WB. The branch is resolved at the end of the third cycle for
unconditional branches and at the end of the forth cycle for conditional
branches. Suppose that 20% of all instructions are conditional branches out of
which 60% are taken and 5% are unconditional branches or procedure calls.
Assume that only the branch instructions results in stall. What is the CPI for
this machine?________
Answer :- 1.46
Solution: 1+0.2*0.6*3+0.05*2
=1+0.36+0.1
=1.46
Answer is 1.46

Q 68. Consider that we have a machine with 7-stage pipeline: IF, ID1, ID2, EX, M1,
M2 and WB. Branch target addresses are calculated in ID2 and branch
conditions are evaluated in EX. Assume a base CPI of 1 without any stall.
Assume 30% conditional branch frequency and 80% of these are taken. How
much faster is the machine with predicted-taken branch prediction than with
predicted-not-taken scheme?_________
Answer :- 1.04
Solution:
Predicted taken CPI
In 80% instruction branches taken its target, and address evaluated in ID2  2
stall
In 20% instruction branches not taken, so our predictionwas incorrect 3 stall
= 1+0.3*0.8*2 + 0.3*0.2*3
=1.66
Also it is also acceptable answer:
1+ 0.3*0.8*2 + 0.3*0.2*1 = 1.54
See advanced booklet question 138 for detail explanation that why second
expression is also acceptable.

Predicted not taken CPI

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 Out of 25% conditional instruction 80% of branch instruction mis-predicted
therefore 3 stall, 20% of branch instruction predicted correctly because our
prediction was not taken.
= 1+0.3*0.8*3+0.3*0.2*0
=1.72
1.72
Faster = = 1.036 = 1.04
1.66
Answer is 1.04
Q 69. Consider a 5-stage non-pipelined processor with 2 GHz clock. To improve the
performance the processor is converted into 5-stage pipeline. Assume that due
to pipeline registers, pipelining the processor lengthens the clock cycle period
by 10%. The processor uses a unified cache for data and instruction accesses,
resulting in a structural hazard between IF and MEM stages. Suppose that
data references represent 30% of the instructions executed and that the CPI of
the pipelined processor, ignoring the structural hazard is 1. How much
speedup can we gain from pipelining?____ ____(round off to 1 decimal place)
Answer ;-3.5

Q 70. An instruction pipeline has five stages, namely, instruction fetch (IF),
instruction decode (ID), instruction execution (EX), memory access (MEM), and
write back (WB) with stage latencies 1 ns, 3 ns, 2 ns, 1 ns, and 0.75 ns,
respectively. To gain in terms of frequency, the designers have decided to split
the ID stage into three stages (ID1, ID2, ID3) each of latency 1 ns. Also, the EX
stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design
has a total of eight pipeline stages. A program has 20% branch instructions
which execute in the EX stage and produce the next instruction pointer at the

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 end of the EX stage in the old design and at the end of the EX2 stage in the
new design. The IF stage stalls after fetching a branch instruction until the
next instruction pointer is computed. All instructions other than the branch
instruction have an average CPI of one in both the designs. The execution times
of this program on the old and the new design are P and Q nanoseconds,
respectively. The value of P/Q is __________.

For the next two questions, consider state diagram of the 1- bit and 2-bit dynamic
branch predictor as show in figure:

Q 71. Assume that 1 indicates a taken branch and 0 indicate not taken branch.
Assume also that this predictor starts in the “Not taken” state. What is the
accuracy (in percent) of a 1-bit predictor if the last 24 instance of this branch
pattern is 1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1 and 1? Assume that the
most recent branch is represented in the least significant bit._____________

Q 72. Assume that 1 indicates a taken branch and 0 indicate not taken branch.
Assume also that this predictor starts in the „”strongly not taken” state. What is
the accuracy (in percent) of a 2-bit predictor if the last 24 instance of this
branch pattern is 1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1 and 1? Assume

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 that the most recent branch is represented in the least significant
bit._____________

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BASIC COMPUTER ORGANIZATION ARCHITECTURE Page 144
 INPUT-OUTPUT AND CONTROL UNIT
Q1. If a magnetic disc has 1024 cylinders, each containing 512 tracks of 256
sectors each, and each sector can contain 128 bytes, what is the maximum
capacity (in GB) of the disk in bytes?_____
Answer : (16)
Solution :

Q2. According to the specifications of a particular hard disk a seek takes 3 msecs
(thousandths of a second) between adjacent tracks. If the disk has 100
cylinders how long will it take for the head to move from the innermost cylinder
to the outermost cylinder?
(a) 30 microseconds (b) 300 msecs (c) 297 msecs (d) 3 microseconds
Answer : (c)
Solution :

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Q3. Consider a disk pack with a seek time of 3 milliseconds and rotational speed of
10,000 rotations per minute (RPM). It has 600 sectors per track and each
sector can store 8K (213) bytes of data. How long (in milliseconds) does it take to
read a random single sector on average? ______
Answer :( 6.01)
Solution :
Rotational speed :-
10000 rotation60 sec
60
1 rotation 
10000
 6 msec
1
Average latency time = * one rotation time
2
1
= *6 = 3 msec
2
Average seek time = 3ms
Average access time = avg seek time +avg latency time+ data transfer time
Data transaction time for 1 sector
Track capacity = 600*8*103
60
than need to read 1 sector 
10,000∗600
1
= *10-3
100
=0.01msec
than Avg transaction time = 3+3+0.01
= 6.01ms
Answer: 6.01ms

Q4. A hard disk system has the following parameters:

 Number of tracks = 500
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  Number of sectors/track =100
 Number of bytes/sector =500
 Average seek time: 250 ms
 Rotation speed =6000 rpm.
What is the average time (in ms) taken for transferring a sector from the disk?
Answer : (255.1)
Solution :

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Q5. A hard disk system has the following parameters:
 Number of tracks = 3000
 Number of sectors/track = 600
 Time taken by the head to move from one track to adjacent track =1 ms
 Rotation speed = 7200 rpm.
What is the average time (in ms) taken for reading a random sector from the
disk_______ (round up two decimal place)

Answer:1000.18
Solution:
If the position of Head is not given then
Average seek time = Avg seek distance / seek rate
Avg seek distance = N/3, where N is number of tracks. See below link for the
formula
(https://pages.cs.wisc.edu/~remzi/OSFEP/file-disks.pdf page No 9)
If the seek time for the from position 0 to track N takes 't' seconds then seek
rate = N/t
Therefore, Average seek time = (3000/3)/(1/1ms) = 3000/3 = 1000 ms
Average Latency = ½ x 8.3333 = 4.16665
So time to read random sector = Avg Seek + Avg Latency + Data Transfer
= 1000 + 4.16665 + 0.0139 = 1004.18055

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 So time to read random sector = Avg Seek + Avg Latency + Data Transfer
= 1000 + 4.16665 + 0.0139 = 1004.18055
For the next two questions, consider a disk with average seek time of 4 ms, rotation
speed of 15,000 rpm, and 512-byte sectors with 500 sectors per track. Suppose that
we wish to read a file consisting of 2500 sectors for a total of 1.28 Mbytes.
Q6. What is the minimum total time (in ms) for the transfer the file if the sequential
organization is used i.e. the file occupies all of the sectors on 5 adjacent tracks
(5 tracks  500 sectors/track = 2500 sectors)? _______
Answer : (26)
Solution :

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Q7. Consider the same hard disk given in the previous question. What is the

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 minimum total time (in sec) for the transfer the file if the random organization is
used rather than sequential organization, that is, accesses to the sectors are
distributed randomly over the disk? ________
Answer : (15.02)
Solution :

Q8. A hard disk has 63 sectors per track, 10 platters each with 2 recording

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 surfaces and 1000 cylinders. The address of a sector is given as a triple ⟨C, H,
S⟩, where C is the cylinder number, H is the head/surface number and S is the
sector number. Thus, the 1st sector is addresses as ⟨0, 0, 1⟩, the 2nd sector
as ⟨0, 0, 2⟩, and so on. The address ⟨400, 16, 29⟩ corresponds to sector
number: ________
Answer : (505037)
Solution :

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Q9. Consider a hard disk with 16 recording surfaces (0-15) having 16384 cylinders
(0-16383) and each track contains 64 sectors (0-63). Data storage capacity in
each sector is 512 bytes. Data are organized cylinder-wise and the addressing
format is ⟨Cylinder #, Surface #, Sector #⟩. A file of size 42797 KB is stored in
the disk and the starting disk location of the file is ⟨1200, 9, 40⟩. What is the
cylinder number of the last sector of the file, if it is stored in a contiguous
manner? _________
Answer : (1284)
Solution :

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Q10. When the processor constantly checks the status of an I/O device, this is
called:
(a) Memory mapped I/O
(b) Asynchronous communication
(c) Interrupt-Driven I/O
(d) Polling
Answer : (d)
Solution :
When processor constantly check the status of an I/O device this is called
polling.
Answer: D
Q11. What advantage(s) does Interrupt-Driven I/O have over polling?
(a) Interrupt-Driven I/O is synchronous while polling is asynchronous
(b) Interrupt-Driven I/O does not require any additional hardware
(c) Interrupt-Driven I/O allows the computer to process other tasks while
waiting for I/O
(d) Interrupt-Driven I/O can be memory-mapped while polling cannot
Answer : (c)
Solution :
In interrupt driven I/O allow the computer to process other tasks while
waiting
for I/O.
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 Answer: C

Q12. [MSQ]
Which of the following statements below is/are true?
(a) In polling, I/O devices set flags that must be periodically checked by the
CPU
(b) When using interrupts, the CPU interrupts I/O devices when an I/O event
happens
(c) The overhead of polling depends on the polling frequency
(d) Polling is often a viable option for slow and asynchronous devices
Answer :( a)&(c)
Solution :
(a) True, In polling I/O device set flag that must be periodically check by
CPU true.
(b) False because CPU does not generate interrupt. Interrupt are generated
by I/O device.
(c) True
(d) False
Answer: (a)&(c)

Q13. When the processor treats I/O devices as locations in memory and uses the
same instructions to access them, this is called:
(a) Memory mapped I/O
(b) Asynchronous communication
(c) Synchronous communication
(d) Interrupt-Driven I/O
Answer : (a)
Solution :
Memory mapped I/O uses the same address space to address both memory
and
I/O.Answer: A

Q14. [MSQ]
Which of the following is /are advantages of cycle stealing in DMA.
(a) It increases the maximum I/O transfer rate.
(b) It reduces the interference by the DMA controller in the CPU's memory
access.
(c) It is beneficially employed for I/O device with shorter bursts of data transfer.
(d) None of the above
Answer : (a)(b)&(c)
Solution :
All are the advantages of cycle stealing mode .
Q15. The main reason for implementing DMA in a computer system is
(a) To free off the CPU from cache coherency problems.

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 (b) To simplify the writing of interrupt service routines
(c) To remove the need for a buffer on the device interface
(d) To speed up the transfer of data between an interface and the main memory
Answer : (d)
Solution :
CPU sole purpose is to execute instruction, not data transfer. Thus CPU
transfer
data solely dma was introduce to reduce this time .

Q16. In a non-vectored interrupt, the address of interrupt service routine is

(a) Obtained from interrupt address table.
(b) Supplied by the interrupting I/O device.
(c) Obtained through Vector address generator device.
(d) Assigned to a fixed memory location.
Answer : (d)
Solution :

Q17. Which of the following I/O methods requires the CPU to initialize the I/O
device?
i. Programmed I/O
ii. Interrupt driven I/O
iii. Direct memory access
(a) ii and iii only (b) iii only
(c) i and ii only (d) All of the above
Answer : (D)
Solution :

Q18. Which of the following I/O methods requires the CPU be able to use interrupts?
i. Programmed I/O
ii. Interrupt driven I/O
iii. Direct memory access
(a) ii and iii only (b) iii only
(c) i and ii only (d) All of the above
Answer : (a)
Solution :

Q19. Which of the following I/O methods requires the CPU to act as a bridge for
moving data between the I/O device and main memory?

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 i. Programmed I/O
ii. Interrupt driven I/O
iii. Direct memory access
(a) ii and iii only (b) iii only
(c) i and ii only (d) All of the above
Answer : (c)
Solution :

Q20. A vectored interrupt is one which

(a) Does not require all device interfaces to be polled
(b) Does not require the cpu to check the interrupt line at the end of each“
Fetch and Execute” cycle
(c) Reduces the number of control lines needed on the bus
(d) Removes the need to enable interrupts on the interface
Answer : (a)
Solution :

Q21. In order to execute a program, instructions must be transferred from memory

along a bus to the CPU. If the bus has 8 data lines, at most one 8 bit byte can
be transferred at a time. How many memory accesses would be needed in this
case to transfer a 32 bit instruction from memory to the CPU?
(a) 1 (b) 2 (c) 3 (d) 4
Ans :-d since we have &data lines in data bus at a time or in a cycle &
bit data can be transferred so if we want to a accurs 32 bits
32/8 =4 cycles will be necessary or 4 memory accurs .
Q22. Consider a printer which can print 20 pages per minute where a page consists
of 4000 characters (1 character = 1 byte). it takes 50 microseconds by CPU to
handle a interrupt. How much CPU time per minute is consumed in handling
the interrupt if output is sent to the printer one character at a
time?_____________%
Answer : (6.67)
Solution :
20 pages and consist of 4000 character per page, and print 20 pages in one
minute.

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 4000*2080,000 character print in one minute.
and interrupt are generated per single character and so total interrupt
generate
= 80,000.
and for handing single interrupt = 50microseconds are required.
for handling 80,000 interrupt number of time= 80,000*50 =40,00000 used
4sec
4
 Minute, consumed by CPU to handle interrupt = 0.06666 = 6.67%
60
Answer: 6.67

Q23. Assume the number of clock cycles for a polling operation, including
transferring to the polling routine, accessing the device, and restarting the user
program, is 400 cycles, with a 500 MHz clock. The mouse must be polled 30
times a second to ensure that no user movement is missed. Fraction of CPU
time (in %) consumed for polling is________
Answer : (0.002)
Solution :

Q24. Suppose we want to read 5000 bytes in programmed I/O mode of transfer,
where the bus width is 16 bits. Each time an interrupt occurs, it takes 10
microseconds to service it (i.e. transfer 16 bits). The CPU time required to read
5000 bytes is _____milliseconds.
Answer :( 25)
Solution :
25 milliseconds.
2 byte transfer requires a minimum of 10 microseconds.
So, 5000 bytes transfer will require: 10 / 2 * 5000 = 25,000 microseconds =
25
milliseconds.

Q25. Consider a system employing interrupt-driven I/O for a particular device that
transfers data at an average of 10000 bytes per second on a continuous basis.
If interrupt processing takes 50 µs, what fraction(in percent) of CPU time is
consumed by this I/O device if it interrupts for every byte?__________
Answer : ( 50)
Solution :

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Q26. The size of the data count register of a DMA controller is 16 bits. The processor
needs to transfer a file of 32 Mbytes from disk to main memory. The memory is
byte addressable. The minimum number of times the DMA controller needs to
get the control of the system bus from the processor to transfer the file from the
disk to main memory is _______
Answer : (512)
Solution :
Maximum number that can be stored in 16 bits is 216 – 1 = 65535 = 64K
(approx.)
So, up to 64K bytes of data can be transferred by the DMA controller at a
time.
Number of times DMA controller needs to be invoked = 215 K / 64 K= 512

Q27. A hard disk with a transfer rate of 1 Mbytes/ second is constantly transferring
data to memory using DMA. The processor runs at 500 MHz, and takes 500
and 1000 clock cycles to initiate and complete DMA transfer respectively. If the
size of the transfer is 1 Kbytes, what is the percentage of processor time
consumed for the transfer operation?________(Rounded off to three decimal

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 places)
Answer : (0.292)
Solution :

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Q28. A DMA controller transfers 4 byte words from an input device to memory in one
clock cycle using cycle stealing. The input device transmits data at a rate of
9600 bytes per second. The CPU is fetching and executing instructions at an
average rate of 1,000,000 instructions per second. Assume that size of each
instruction is4bytes. The CPU will be slowed down because of the DMA transfer
by _________ percent.
Answer : (0.24)
Solution :
In 1 second, the input device transfers 9600 bytes of data.
This is equivalent to 9600 / 4 = 2400 DMA cycles, as 4 bytes are
transferred every cycle.
Earlier, in 1 second, 1,000,000 instructions were executed.
But now, in 1 second, (1,000,000 – 2400) = 997600 instructions are
executed.
So, slowdown = 2400/1000000 = 0.24 %

Q29. A hard drive with a maximum transfer rate of 1MB/sec is connected to a 32-
bit, 10 MIPS CPU operating at a clock frequency of 100 MHz. Assume that the
I/O interface is DMA based and it takes 500 clock cycles for the CPU to set-up
the DMA controller. Also assume that the interrupt handling process at the end
of the DMA transfer takes an additional 300 CPU clock cycles. If the data
transfer is done using 2000Bytes blocks, what is the percentage of the CPU
time consumed in handling the hard drive?________
Solution
Since the hard drive transfers at 1MB/sec, and each block size is 2KB,
there are
1000/2= 500 blocks transferred/sec
Every DMA transfer uses 500+300=800 CPU cycles. This gives us
800x500 = 400,000 = 400x103 cycles/sec For the 100 MHz CPU, this

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 corresponds to (400x103 ) / (100x106 )= 4x10-3 = 0.4%
This would be the case when the hard drive is transferring data all the time.
In
actual situation, the drive will not be active all the time, and this number
will
be much smaller than 0.4%.

For the next two questions, consider a system in which bus cycle takes 500 ns.
Transfer of bus control in either direction, from processor to device or vice-versa,
takes 250 ns. One of the I/O device has data transfer rate of 75 KB/sec and employs
DMA. Data are transferred one byte at a time.
Q30. Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus
master ship prior to the start of block transfer and maintains control of the bus
until the whole block is transferred. For how long (in nanoseconds) would the
device tie up with the bus when transferring a block of 256
bytes?_________(Rounding to 2 decimal places)

Q31. Now suppose we employ DMA in a cycle stealing mode. That is, the DMA
interface gains bus master ship prior to the start of each byte of data to be
transferred and then return control to the CPU after each byte of data
transferred. For how long (in nanoseconds) would the device tie up with the
bus when transferring a block of 256 bytes?______________ (Rounding to 2
decimal places)

Q32. Consider the following sequence of microinstructions

t1: MAR ← (PC)
t2: MBR ← (memory), PC ← (PC) + 1
t3: IR ← (MBR)
t4: MAR ← (PC)
t5: MBR ← (memory), PC ← (PC) + 1
t6: R1 ← R1 + (MBR)
What operations do the following instructions perform?
(a) Add the number NUM to register R1.
(b) Add contents of memory location NUM to register R1.
(c) Add contents of the memory location whose address is at memory location
NUM to register R1
(d) None of the above

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 Ans :- B
T1: MAR (PC)
T2: MBR (memory), pc(pc)+1}fetch cycle
T3: IR (MBR)
T4: MAR (PC)
T5: MBR(memory ).pc(pc)+1
R6:R1R1+(MBR)

Q33. Consider the following sequence of micro-operations

t1: MAR(PC)
t2: MBR(memory);
PCPC+1
t3: IR(MBR)
Which of the following cycle is performed by this sequence in the
instruction cycle?
(a) Fetch cycle (b) Execute cycle
(c) Indirect cycle (d) Interrupt cycle

Q34. Consider the following sequence of micro-operations

t1: MAR(IR address)
t2: MBR(memory)
t3: R1R1+(MBR)
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 Which of the following cycle is performed by this sequence in the instruction
cycle?
(a) Fetch cycle (b) Execute cycle
(c) Indirect cycle (d) Interrupt cycle

Q35. Consider the following sequence of micro-operations

t1: MBR(PC)
t2: MARsave-address;
PCroutine-address;
t3: memory(MBR)
Which of the following cycle is performed by this sequence in the instruction
cycle?
(a) Fetch cycle (b) Execute cycle
(c) Indirect cycle (d) Interrupt cycle

Q36. Consider the following sequence of micro-operations

t1: MAR(IR address)
t2: MBR(memory)
t3: IR address(MBR address)
Which of the following cycle is performed by this sequence in the instruction
cycle?
(a) Fetch cycle (b) Execute cycle
(c) Indirect cycle (d) Interrupt cycle

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Q37. Which of the following set of control signals can be used to transfer data from
register R4 to register R5?
(a) R4out, R5in (b) R4out, MARin, MDRout
(c) R5out, R4in (d) R5out, MARin, R4in
Correct answer is (a).
For the data transfer to take place, the data output of register R4
should
be enabled (R4out) and the data load control of R5 should be activated
(R5in).

Q38. Which of the following statements are true when the control signals PCout,
MARin, and READ are activated simultaneously?
1. Content of PC is made available in the internal processor bus
2. The content of PC is moved to MAR and MDR
3. The instruction fetch operation is activated
4. The content of PC is moved to MAR
(a) 1 and 3 only
(b) 2, 3 and 4 only
(c) 2 and 4 only
(d) 1, 3 and 4 only
Answer :- 4

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 Correct answers are (1), (3) and (4). When the control signals PCout
and MARin are activated, the contents of PC will get transferred via the
internal processor bus to the MAR register. And since READ is also
active, the address in MAR will be used to initiate a read operation to
memory to fetch the next instruction.

For the next two questions, consider the following Single data path of a CPU.

Using one bus, the CPU registers and the ALU use a single bus to move outgoing and
incoming data. Since a bus can handle only a single data movement within one clock
cycle, two-operand operations will need two cycles to fetch the operands for the ALU.
PC can incremented locally and all other operations including GPRs are to be carried
out in the ALU. Two clock cycles are needed for memory read operation – the first one
for loading address in the MAR and the next one for loading data from the memory
bus into the MDR. Additional registers may also be needed to buffer data for the ALU.
The instruction “Add R1, R2, R0”. This instruction adds the contents of source
registers R1 and R2, and stores the results in destination register R0.
Q39. The minimum number of clock cycles needed for fetch cycle of this instruction
is:_____
Q40. The minimum number of clock cycles needed for execute cycle of this
instruction is:___
Q41. Consider the following path diagram

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 Consider An instruction: R0R1+R2.the following steps are used to execute it
over
the given data path. Assume that PC is incremented appropriately. The
subscripts
r and q indicate read and write operations, respectively.
1. R2r, TEMP1r, ALUADD, TEMP2W
2. R1r, TEMP1W
3. PCr, MARW, MEM r
4. TEMP2r, R0w
5.MDRR, IRW
Which one of the following is the correct order of execution of the above steps?
(a)2,1,4,5,3
(b)1,2,4,3,5
(c)3,5,2,1,4
(d)3,5,1,2,4
Answer :- C

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For the next five questions, the system shown in the figure below uses a control
memory of 1024 word of 32 bits each. The microinstruction has three fields as shown
in the diagram. The micro-operation field has 16 bits.

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Q42. How many bits are there in the branch address field? _________________

Q43. How many bits are there in the select field? _____________________

Q44. If there are 16 status bits in the system, how many bits of the branch logic are
used to select a status bit?_________

Q45. How many bits are left to select an input for the multiplexers? _________

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Q46. If the control memory in the figure above has 4096 words of 24 bits each, How
many bits are there in the control address register?__________

Q47. Which of the following statements are true for horizontal microinstruction
encoding?
(a) If there are k control signals, every control word stored in control memory
(CM) consists of k bits, one bit for every control signal.
(b) Parallel activation of several micro-operations in a single time step can be
performed. (c) Parallel activation of several micro-operations in a single time
step cannot be performed.
(d)Both (a) and (b) is correct.

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Q48. Consider the instruction set architecture of a general-purpose machine.
Suppose that a total of 20 control signals are present, out of which 7 are
mutually exclusive while the rest are not. The number of bits required in the
control word (for microprogramming) will beat least_________.

Correct answer is 16. The 7 mutually exclusive signals can be encoded in

ceiling(log2 7) = 3 bits, while the remaining 13 signals will remain un-
encoded.
So the number of bits in a control word will be 3 + 13 = 16.

Q49. Suppose an instruction set architecture of a general-purpose machine has a

total of 126 control signals. The number of bits required in control word for
horizontal and vertical micro-instruction encoding are:
(a) 126, 7 (b) 128, 7
(c) 7, 126 (d) 126, 8

Correct answer is (a). For horizontal encoding, one bit is used for each
control
signal; therefore, we shall require 126 control signals. For vertical
encoding, the 126 control signals can be encoded in ceiling(log2 126) = 7
bits
Q50. Consider the control unit in which the control signals can be divided into the
following mutually exclusively groups?
Group 1: 23 control signals to activate gates that transfer data from the
internal bus to the register/ALU input.
Group 2: 20 control signals to activate gates that transfer data from the
registers to the internal bus.

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 Group 3: 32 control signals to specify ALU operation.
Group 4: 8 control signals to specify shifter operation.
How many bits of the control words can be saved by using vertical
microprogramming over horizontal microprogramming? _________

Q51. How many address and data lines will be there for a 16M x 32 memory system?
(a) 24 and 5 (b) 20 and 32
(c) 24 and 32 (d) None of the above
Correct solution is (c). Since there are 16M words, the number of address
lines
will be 24, since 224 = 16M. Also since the word size is 32 bits, the number
of data
lines will also be 32.

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Q52. Assume that a 1G x 1 DRAM memory cell array is organized as 1M rows and
1K columns. The number of address bits required to select a row and a column
will be:
(a) 20 and 10
(b) 30 and 1
(c) 220 and 210
(d) None of the above
Correct answer is (a).
Since there are 1M rows, the number of row address lines will be 20, as
220 = 1M. Also, for selecting one of the 1K columns, the number of column
address lines will be 10, as 210 = 1K.

Q53. To build a 1G x 16 memory system, the number of 256M x 8 memory modules

required will be_________
Correct answer is 8.
4 x 256 M = 1G, and 2 x 8 = 16.
Hence the number of memory modules required will be 4x2 = 8.

Q54. RAM chip has a capacity of 1024 words of 8 bits each. The number of 2-to-4
decoders with enable lines needed to construct a 16K x 16 RAM system will be
_________

Correct answer is 5.
To construct a memory system with 16K words using 1024x8 RAM chips,we
have
to connect 16 such chips in parallel. The decoder will have toselect one of
the
16 chips. To construct a 4x16 decoder, we require 5 2x4decoders.

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