Serial Communication

Protocols
– Parallel: Faster / More expensive
Communication Protocols
– Serial: Cheaper / slower
Communication Protocols
• Parallel
• Parallel Vs. Serial
Vs. Serial
– Parallel: Faster / More expensive
• Parallel
• Faster
– Serial:
• More Cheaper
expensive / slower
• Serial
• Cheaper
• Slower
 Serial Communication
• Transmission of one bit of information at a time.
• One bit -> a time delay -> next bit
• Peripheral devices such as printers, keyboards, scanners, and mice
operate have their own computer
• Communication problem can be generalized to one of transmitting
information between two computers.
• Serial channel is the collection of signals (or wires) that implement
the communication between 2 computers/devices/modules
• To improve bandwidth, remove noise and increase range,
• Place interface logic between the digital device and the serial channel.
define the data terminal equipment (DTE) as the computer or a term
Serial Channel
communication equipment (DCE) as the modem or printer.

Figure• Data
7.1.terminal
A serial channel
equipment connects
(DTE): the computer two
or a terminal thatdata
generateterminal
or receive eq
data
devices.
• Data communication equipment (DCE): equipment that facilitates the transmission
of data between DTE.
When transmitting in a serial fashion, there are many ways to encode b
 Transmitting Data Serially
• Many ways to encode binary information on the line
• maximize bandwidth and minimize errors
• Non-return-to-zero (NRZ) encoding is a binary code in which signal is
never at zero voltage. Ex: UART
• Level the matches the logical signal (digital data (0/1) is converted to digital
signal(v/0)) where a 1 is a positive voltage or current
• More energy in the wire compared to typical VOL/VOH digital logic
• Always a voltage causing current to flow continuously
• On a twisted pair, voltages are differential.
• Binary values of 1 and 0 are encoded as positive or negative voltage
differences.
• In positive logic, 1 is a positive voltage difference and 0 is a negative voltage
difference.
• In negative logic, the voltage representing 0 is higher than the voltage representing
1.
a Example: NRZ Unipolar/bipolar
e
s

n
-
d
f
l
t
e
f
y
• Unipolar:
The clock highlightseither abovetransition
the different or belowmethods.
the axis NRZ is level sensitive
n related•toBipolar: Both
the values sides
being sent.of
RZaxis
has a transition for a 1 value with respect to
 Transmitting Data Serially
• Non-return-to-zero-inverted (NRZI) – Ex USB
• Method of encoding binary signal as transitions or changes in the signal.
• Transitions in the middle of the clock cycle, but this only occurs when there
is a 0/1 depending the type of NZRI
• Similar to NRZ, the signal in a NRZI protocol is never zero.
• Binary information is encoded as the presence or absence of a transition at
a clock boundary,
• Both the transmitter and receiver will synchronize their clocks so the
receiver knows when to look for the transition.
• Transition is a change from positive to negative or from negative to positive
• Send a 1 by placing a transition on the signal, or send a 0 by causing no
transition
• NRZI might take the opposite convention, as in Universal Serial Bus (USB),
where a transition means 0 and a steady level means 1.
 Example: NRZI

The clock highlights

• Flip only the1different
either on transition
or 0 (depends methods. NRZ
on architecture) afterishalf
level sensitive
cycle
related to the values being sent. RZ has a transition for a 1 value with respect to
 Transmitting Data Serially
• Manchester encoding – Ex Ethernet
• Encodes binary bits as either a low-to-high transition, or a high-to-low
transition.
• Information transmitted as phase shifts, combining the clock and data
signals into one stream
• Duration of a bit is divided into two halves
• voltage remains the same at one level during the first half & moves to the
other level.
• Transitions that signify 0 or 1 occur at the midpoint of a period
• NRZ or NZRI encoding: 1 Mb/s
• IEEE 802.3 Ethernet: 2 Mb/s
he
n
s-a
Example: Manchester
d
he
of
ms
al
at
In
hes-
of
ld
y
of
al The clock highlights the different transition methods. NRZ is level sensitive
• Flip at both 0 and 1 after half cycle
nat related to the values being sent. RZ has a transition for a 1 value with respect to
• If 1->1 or 0->0, 2-flips on beginning of cycle
es
he the clock. Manchester and NRZI have transitions based on the value. Manchester
h
of has a falling transition for a 1, while NRZI has a transition for a 1.
e
ly
square wave at 1 MHz. However, using IEEE 802.3 encoding
Example: Altogether
wave at 2 MHz.
 Communication Protocols
• Timing in serial communication
• Synchronous Serial – same Clock frequency
• Grouping characters together in an envelope
• Start and stop bits for each group. Permits greater flexibility.
• Extra ending sequence is added to perform error checking.
• Example: Serial Peripheral Bus (SPI) Inter-Integrated Circuit (I2C)
• Asynchronous Serial – May not be same Clock frequency
• Send data bytes (max) between the sender and receiver by packaging the data in an
envelope.
• Transmission link separates the sender and receiver.
• Transmitter creates the envelope, and the receiver uses the envelope to extract the data.
• For each character the sender transmits is preceded with a start bit, and suffixed with a
stop bit
• These extra bits serve to synchronize the receiver with the sender.
• Example: Universal Asynchronous Receive/ Transmit (UART), Universal Serial Bus (USB),
Ethernet, and Controller Area Network (CAN)
 Asynchronous Serial Interface
• Only data is transmitted from the transmitter to the receiver, at a
mutually agreed bit rate.
• The clock is not transmitted by the sender,
• receiver generates a local clock signal, of same frequency as that of
transmitter, to reliably receive the transmitted data bits.
• If the transmitter has to switch to a different baud (bit per second)
rate, it has to inform this new baud rate to the receiver, before
starting data transmission at new rate.
• One of the widely used asynchronous serial communication
interfaces is Universal Asynchronous Receiver/Transmitter (UART)
and USB
 Synchronous Serial Interface
• Both data and clock signals are transmitted simultaneously.
• Sender can change baud rate without informing the receiver.
• Two common synchronous serial interfaces available on
microcontrollers are
• Inter-Integrated Circuit (I2C) and
• Serial Peripheral Interface (SPI).
 The classifications of different serial communication
Classifications of different serial
interfaces, based on the mentioned two attributes, are
communication
summarized.
 Communication
Communication Modes Modes
• A serial interface can have
• A serial interface can
different communication modes
have different
• Full Duplex - means both devices
communication
can send and receive
modes
simultaneously.– Full Duplex - means both
devices
• Half-Duplex - means can
serial send and
devices
receive simultaneously.
must take turns sending and
receiving. – Half-Duplex - means
serial devices must take
turns sending and
receiving.
 Full Duplex/Half Duplex
• Full duplex communication system: Allows information (data, characters) to
transfer simultaneously in both directions.
• Full duplex channel Allows bits (information, error checking, synchronization or
overhead) to transfer simultaneously in both directions
• Half duplex communication system: Allows information to transfer in both
directions, but in only one direction at a time.
 – Synchronous Serial

Rules of Asynchronous Protocols – Asynchronous Serial

• Rules of Asynch. Protocols
• Synch bit – Synch bit
• Required to define the beginning/end of the data
– Parity bit
Parity and Baud Rate
• The start bit[LOW] and the stop bit[HIGH]
• Parity bit – Baud Parity
Baud Rate
rate and
• Even: number • ofParity Parity
ones in the data plus •parity is an even
– Data bit number
• 10101010101 -> 6 one’s -> EP = 0 – Even Parity : 10101010101 à 6 one’s à EP=0
– Even
• Odd: number of ones Parity
in the data: plus
10101010101
parity
– is
Offan
àodd6: one’s
Parity numberà EP=0
1010101010 à 5 one’s à OP=0
Off Parity
• 1010101010 ->–5 one’s -> OP=0: 1010101010 à 5 one’s à OP=0
• Baud Rate 9600 8N1 – 9600 bps/
• Baud rate • Baud Rate – Pulse per second 9600 8N1 – 8 bits per data / No
9600 bps/
parity / One Stop bit
• Pulse per second – In digital world: Bits per second8 bits per dataAlways
/ No has start bit
– Pulse
• In digital world: Bits per second
per second
– 9600 baud à 9600 bps or 104parity
µs per /bit.
One Stop bit
• 9600 baud -> 9600 bps -> 104 μs per bit.
– In digital world: Bits per second
• Synch bit
Always has start bit
• Data bit – 9600 baud à 9600 bps or 104toµs perthe
bit.beginning/end of the data
– Required define
• BW
• • Synch
amount of data or usefulbit
– the start bit [LOW] and the stop bit [HIGH]

information transmitted per

– Required to define the beginning/end of the data
second
– the start bit [LOW] and the stop bit [HIGH]
 Data Frame
• Sender and receiver uses the same transmission speed
• Data frame
• One start bit
• Data(LSB first or MSB, and size of 7, 8 bits)
• Optional parity bit
• One or two stop bit
• Overhead % = 1-(Useful Data / Total Data)
• 9600/(1 + 8 + 1 + 1) = ~862 bits/second
• In this case how many frames are required to send out 100,000 bits?
• Data
How long does it take to transmit 100,000 bits at 57,600 Frame
baud rate?

Tolerate 10% clock shift during transmission

 Baud Rate
• Total number of bits (/symbols) transmitted (information, overhead, and idle)
per second is called the baud rate
• Reciprocal of the baud rate is the bit time
• Example: 10-bit frames running at 9600-bps (baud rate) transmitter to
receiver.
• Latency of a frame: 1.04 ms
• Bandwidth: 9600 bps/(8+1-sr+p(0/1)+1-st) = 960 bytes/s
 Transmitting 0x32
Transmitting 0x32 and 0x3C and 0x3C

1 start bit, 1 stop bit, 8 data bits, no parity, baud rate = 9600
 Serial Communication - UART
Serial
• Universal Asynchronous Receiver Communication
and Transmitter (UART)
• UART is asynchronous full-duplex communication
• Universal Asynchronous Receiver and Transmitter (UART)
• Asynchronous – UART is programmable.
• Sender provides no •clock signal to receivers
Asynchronous
• Full-duplex – Sender provides no clock signal to receivers
• Separate Tx and Rx line – FT232R converts the UART port to a standard USB interface
 implementing serial communication
• USART – Supports synchronous
UART
communication
• Universal Asynchronous Receiver/Transmitter
(UART)
• Asynchronous communication,
• Full duplex.
• Only two data lines (along with third line for
common ground) are sufficient for minimum
connectivity.
• The communicating UART devices can be either a
microcontroller or any other device equipped
with UART interface.
• Each data byte is transmitted sequentially bit by
bit, as single standalone UART frame.
• On the receiver side, the received bits are
assembled to reconstruct the data byte.
 Flow Control
• If during data transmission, the receiving device runs out of buffer space and
it becomes essential to inform the transmitter to stop further data
transmission. This additional control signaling between transmitter and
receiver is called flow control.
• Flow control can be implemented using hardware or software.
• Hardware flow control: dedicated hardware connections are used for flow control
purpose.
• Software flow control: no extra hardware is required. Rather a communication protocol
implemented as part of the software is used for flow control purpose.
• UART has also been used extensively for modem connections. In that context, it is
possible to employ hardware flow control. For that purpose, dedicated lines labeled as
request to send (RTS) and clear to send (CTS) are used in addition to UART receive
(U_RX) and transmit (U_TX) data lines.
 UART Frame Format
• When data of appropriate size (5 to 8 bits) is passed to the UART
module for transmission, a Start bit is placed at beginning of the
data. The Start bit is the first bit that is transmitted by the
transmitter and is marked by the transmission of logic low level for
one bit duration.
• If the UART module is idle before the beginning of transmission, its
transmit pin (labeled as U_TX) is kept at logic level high.
• The start of UART frame transmission is marked by a logic “Low” to
low transition on U_TX pin generated by the transmitter and is
sensed by the receiver.
• Stop bit is High
 UART Data Transmission
• At the completion of Start bit transmission, the first data bit (corresponding to LSB of data)
is transmitted followed by bit by bit transmission of the entire data field.
• After the transmission of last data bit, the optional parity bit, if configured, is transmitted.
• Finally, one or two stop bits are transmitted to mark the end of UART frame transmission.
The transmission of next UART frame can start immediately after the transmission of stop
bit(s) corresponding to previous UART frame.
 Example
A typical UART frame comprising of 1 Start bit, 8 data bits,
• A typical UART frame comprising of 1 Start bit, 8 data bits, 1 parity bit and 1
1 parity bit and 1 stop bit is shown below where S is the Start
stop bit is shown below where S is the Start bit, D0-D7 are the data bits. D0 is
bit,parity
the LSB, P is the D0-D7bitareand
theEdata bits.stop
is the D0 bit.
is the LSB, P is the parity bit
and E is the stop bit.

22 TCES430, Autumn 2019 11/12/2019

 transmitter has a 16-element FIFO and a 10-bit shift
Transmitting in UART accessed by the programmer (Figure 4.35). The FIFO
are separate from the FIFO and shift register associa
• UART Transmission: using the UART, the software will first check to mak
• A Data output pin will wait if TXFF is 1) and then write to the transmi
• 16-element FIFO The bits are shifted out in this order: start, b0, b1, b2,
• a 10-bit shift register b0 is the LSB and b7 is the MSB. The transmit data re
• Transmitter Data Register software can write to it (to start a new transmission)
• Separate transmitter and receiver FIFO theand shift register
transmit data register is at the same address as th
• SW will check first if Tx FIFO is not fulland
then write data
receive data to the Tx data
registers register
are two separate registers.
• Bits are shifted out in order: start,
b0, b1, b2, b3, b4, b5, b6, b7, and
then stop, where b0 is the LSB and b7
is the MSB.
• FIFO guarantees the data are
transmitted in the order they were
written
 UART Baud Rate
• UART Baud Rate – Both transmitter and receiver should be configured with same
baud rate for reliable data transmission.
• The UART baud rate is selected by configuring an appropriate value to the baud rate
divisor field (baud_divisor) in one of the UART configuration registers.
• Baud16: Serial port hardware is controlled by a clock that is 16 times faster than the
baud rate
• When the data are being shifted out, the digital hardware in the UART counts 16 times in
between changes to the Tx output line.
• Assuming the frequency of the clock fed to the UART module is fuart, then the UART
baud rate can be obtained using the following expression.
• UARTBaud (UBR) = fuart/(k × baud_divisor)
• fuart = 16MHz, k = 16, UBR = 9600
• Here k is the clock divisor constant and can take different values depending on
selected hardware platform. Based on the available configuration parameters, an
arbitrary baud rate can be used for data transfers. However, there are some standard
baud rates that are used by different applications.
 from UART0_DR_R , data are removed from the FIFO.
the RXFE flag will be set, meaning there are no more inp
Receiving in UART associated with the receiver. There is a Receive FIFO full
the FIFO is full. There are four status bits associated with
• Needs to synchronize the receiver reason, the receive
to receive FIFO isdata
incoming 12 bits wide. The overrun erro
lost because the FIFO is full and more input frames are ar
• Receiver portion of the UART includes overrun Rx data
error input when
is caused pin with digital logic
the receiver levels
interface latenc
• Input of the microcontroller, true BE, is 3.3V andwhen
is set falsethe
is 0V
input is held low for more than a fram
• Receiver contains: error. Because the error rate is so low, most systems do no
• 16-element FIFO error, FE, is set when the stop bit is incorrect. Framing er
• a 10-bit shift register mismatch in baud rate.
• Receiver data register
• Receiver recognize a new frame
with start bit (0)
• Bits are shifted in order: start (0),
b0, b1, b2, b3, b4, b5, b6, b7, and
then stop (1)
 UART Receiver Synchronization
• To send and receive data using UART we can use several methods including:
• polling, interrupt
• Since no clock signal in TX/RX, the receiver needs to synchronize itself to the
incoming data locally.
• The UART receiver uses a clock signal that is 16 times the UART baud rate – Baud16
• After the 1 to 0 (start bit) edge, the receiver waits 8 Baud16 clocks and samples the start bit.
• Every 16 Baud16 clocks it samples another bit until it reaches the stop bit
• UART needs an internal clock faster than the baud rate so it can wait the half a bit time between
the 1 to 0 edge
• When the transmission of a new UART frame is initiated by Start bit, the UART
receiver resets a local counter on the reception of this falling edge.
• When the counter count equals 8, it corresponds to the mid point of the Start bit.
The midpoints of subsequent bits in the UART frame are expected to occur every 16
cycles thereafter.
• The higher clock signal used by the receiver increases correct bit detection capability
by improving the receiver synchronization.
 UART Error Types
• Parity Error – when the received parity bit does not match with the parity
calculated from the received data.
• Framing Error – when a Start bit is received but the receiver does not get the
corresponding stop bit.
• Baud rate issue
• Overrun Error – when the UART receive buffer is full and new data is received,
then the newly received data overwrites the previous data. This situation leads
to overrun error.
• Break Error – when the receiver detects a break condition, it results in break
error. A break condition is detected when UART RX pin is held low for more
than one UART frame transmission time.
• Input is held low for more than a frame
 command from the master. In the other direction, however, a
Communication Systems Based on the UARTs
because multiple slave transmitters are connected to the same
transmit after specifically being triggered by the master, no co

• 3-communication systems
• Master-slave configuration
• Ring Network
• Multi-drop System
• UART is mostly 1-master, 1-
slave communication

Figure 11.3. A master-slave network implemented w

 using wire-or open drain logic, allowing for the slaves to resp
ODE (Open Drain Enable) in the slaves should be set to acti
Master-slave Configuration transmitters. The low-level device driver for this communica
UART driver developed in Program 5.9. When the master pe
broadcast to all the slaves. There can be no conflict when the
• Master (transmit output) is connected single output is connected to multiple inputs. When a slave re
to all slave (receive inputs) command from the master. In the other direction, however, a
because multiple slave transmitters are connected to the same
• All slave are connected together using transmit after specifically being triggered by the master, no c
wire-or open drain logic, allowing for
the slaves to respond one at a time.
• Master broadcast output through
UART to all the slaves
• When a specific slave receives input, it
knows it is a command from the
master
• All other slaves ignore
 shown in Figure 11.4. Building a ring network is a matter as
cable in a circle with one DB9 connector for each node. Mes
Ring Network Configuration address, destination address and information. If computer A
computer C, it sends the message to B. The software in comp
notices it is not for itself, and it resends the message to C. Th
• Ring network is built simply by receives the message, notices it is for itself, and it keeps the m
chaining the transmit and receive build, this system has slow performance (response time and b
lines together in a circle to add/subtract nodes.

• Messages will include source address,

destination address and information.
• If computer A wishes to send
information to computer C, it sends the
message to B. The software in computer
B receives the message, notices it is not
for itself, and it resends the message to
C. The software in computer C receives
the message, notices it is for itself, and
it keeps the message
• Slow performance
• Difficult to add/remove nodes
 Issues with Asynch. Communication Protocols
• Asynchronous Communications
• Devices must agree ahead of time on a data rate
• The two devices must also have clocks that are close to the same
rate
• Excessive differences between clock rates on either end will cause
garbled data
• Asynchronous serial ports require hardware overhead
• The UART at either end is relatively complex and difficult to
accurately implement in software if necessary
• Most UART devices only support a certain set of fixed baud rates,
and the highest of these is usually around 230400 bits per second
 Asynchronous Transmission
Asynchronous and Synchronous
Transmission
Example of an “A” followed by a “B”

Synchronous Transmission
Stop
Stops Start Stop Start

A = 0x41 B = 0x45

Example of an “A” followed by a “B”

Clock

Data

A = 0x41 B = 0x42
 Synchronous Transmission – I2C
• The Inter-integrated Circuit (I2C)
• I2C Protocol is a protocol intended to allow multiple “slave” (or secondary)
digital integrated circuits (“chips”) to communicate with one or more “master”
chips.
• Multi-master system, allowing more than one “master ” (or primary) to
communicate with all devices on the bus
• When multiple primary devices are used, the master devices can’t talk to each other
over the bus and must take turns using the bus lines.
• In I2C there are three additional modes specified:
• Fast-mode plus, at 1MHz;
• High-speed mode, at 3.4MHz; and
• Ultra-fast mode, at 5MHz.
 I2C Characteristics
• Serial, byte-oriented
The SCL clock is used in a synchronous fashion to communicate on the bus. Even though
• Multi-master, multi-slave
data transfer is always initiated by a master device, both the master and the slaves have
• Two bidirectional lines,
control plus
over ground
the data rate. The master starts a transmission by driving the clock low, but i
a slave wishes to slow down the transfer, it too can drive the clock low (called clock
• Serial Data Linestretching).
(SDA) In this way, devices on the bus will wait for all devices to finish. Both addres
• Serial Clock Line (SCL)
(from Master to Slaves) and information (bidirectional) are communicated in serial
• SDA and SCL need to pull
fashion up with resistors
on SDA.
 I2C Communication Signals
• 5-componenets for communications:
• START: master to initiate a transfer
• DATA: sent in 8-bit blocks (MSB first) and consists of
• 7-bit address and 1-bit direction from the master
• control code for master to slaves
• information from master to slave
• information from slave to master
• ACK: used by slave to respond to the master after each 8-bit data transfer
• RESTART: used by the master to initiate additional transfers without
releasing the bus
• STOP: used by the master to signal the transfer is complete and the bus is
free
 I2C Bus Connection
• Each device connected with the I2C bus can be either in master mode or in
slave mode.
• But only a master device can initiate the data transfer process.
• Usually, there are one master and one slave or multiple slave devices connects
with the same I2C bus through pull-up resistors.
• Each salve address has a 7-bit unique address.
 then subsequent data transmissions contain information sent from master to

Timing Diagram
For a write data transfer, the master drives the RDA data line for 8 bits, then
drives the acknowledge condition during the 9 clock pulse. If the direction
th

• A START condition is athen

high-to-low transition on SDA when SCL is
subsequent data transmissions contain information sent from slave to m
read data transfer, the slave drives the RDA data line for 8 bits, then the mas
high. acknowledge condition during the 9 clock pulse. The STOP component is
th

• A STOP condition is a master

low to high
to signify transition
the on
end of transfer. A SDA when
STOP begins SCL
with SCLisand high.
SDA bot
makes the SCL clock high, and ends by making SDA high. The rising edge o
• The address and the data
SCL is bytes are the
high signifies sent
STOP most significant bit first.
condition.
• Master generates the clock signal and sends it to the slave during
data transfer
 Timing Diagram
• Idle bus has both SCL and SDA high.
• A transmission begins when the master pulls SDA low, causing a START (S)
component.
• The timing of a RESTART is the same as a START.
• After a START or a RESTART, the next 8 bits will be an address (7-bit address
plus 1-bit direction).
• There are 128 possible 7-bit addresses, however, 32 of them are reserved as special
commands.
• The address is used to enable a particular slave.
• All data transfers are 8 bits long, followed by a 1-bit acknowledge.
• During a data transfer, the SDA data line must be stable (high or low)
whenever the SCL clock line is high.
• There is one clock pulse on SCL for each data bit, the MSB being transferred
first.
 8th SCL pulses are used to shift the address/direction into all the slaves. In
Timing Diagram
acknowledge the master, the slave that matches the address will drive the
• Next, the low
selected
duringslave
the will respond
9th SCL pulse.with a positive
During the 10acknowledge
th
through 17th(Ack)SCLor a se
pulses
negative acknowledge (Nack).
the selected slave. The selected slave will acknowledge by driving the SD
• For a write datathe
during transfer: master
18th SCL drivesAthe
pulse. RDA data
second dataline for is
byte 8 bits, then the from
transferred slave drives
master
the acknowledge condition during the 9th clock pulse.
same manner. In this particular example, two data bytes were sent, but th
• For a read data transfer: slave drives the RDA data line for 8 bits, then the master drives
used to send
the acknowledge any number
condition during theof9th
bytes,
clockbecause
pulse. once the master captures the b
• If the slaveasreceiver
many bytesdoesasnotit wishes. If the slave
acknowledge receiverthe
the master, doesSDAnot acknowledge
line will be left th
high (Nack).line will be left high (Nack). The master can then generate a STOP signal
• The master transfer or agenerate
can then RESTART signalsignal
a STOP to commence
to abort thea newdatatransmission.
transfer or aThe ma
end oftotransmission
RESTART signal commence by sending
a new a STOP condition.
transmission.
• The master signals the end of transmission by sending a STOP condition.
 address and 1-bit direction. During the first start, the address selects the first s
I2C to Transfer 2-Bytes to Different
direction is read. During the 10 th
through 17 th
SCL pulsesDevices
the first slave sends
the master. Because this is the last byte to be read from the first slave, the mas
• Master to Slave1:
acknowledge letting the SDA data float high during the 18th SCL pulse, so the
releases
• Address:theFirstSDA
7-bitsline. Rather
and 1-bit than (SCL
direction issuing
Pulsea1-STOP
8) at this point, the master iss
• Ack: 9th SCL pulse
repeated start orth RESTART. The 7-bit address and 1-bit direction transferred i
• Data: 10th to 17 SCL Pulse
through 27th th SCL pulses will select the second slave for writing. In this examp
• Ack: 18 SCL pulse
direction is low, signifying
• Slave1 release SDA on 19th SCL pulse a write format. The 28th
pulse will be used by the s
pulls SDA low to acknowledge it has been selected. The 29th through 36th SCL
• Master to Slave2:
the data to the second slave. During the 37 th
pulse the second slave pulls SDA
• Address: 20 to 27 SCL Pulse
th th
acknowledge the data it received. The master signals the end of transmission
• Data: 29th to 36th SCL pulse
STOP condition.
• Ack: on 37th SCL pulse
 I2C Synchronization
• Two or more masters try to issue a START command on the bus at the same
time, both clock synchronization and arbitration will occur.
• Clock synchronization is procedure that will make the low period equal to the
longest clock low period and the high is equal to the shortest one among the
masters
• Master #2 is the first to drive its clock low.
• SCL clock will be low from the time the
first master drives it low (time 1), until
the time the last master releases its
clock (time 2)
• Similarly, the SCL clock will be high
from the time the last master releases
its clock (time 2), until the time the first
master drives its clock low (time 3)
 Priority in Masters
• Relative priority of the contending masters is determined by a data arbitration
procedure
• Master loses arbitration if it transmits logic “1” while another master transmits
logic “0”.
• Losing masters immediately switch over to slave receive mode and stop driving
the SCL and SDA outputs
• In the example from previous slide:
• Master #1 is generating an address with A7=1 and A6=0, while master #2 is generating
an address with A7=1 and A6=1. Between times 2 and 3, both masters are attempting to
send A7=1, and notice the actual SDA line is high.
• At time 4, master #2 attempts to make the SDA high (A6=1), but notices the actual SDA
line is low.
• In general, the master sending a message to the lowest address will win arbitration.
 Master to Slave Data Transfer
Master to Slave Data Transfer
• In this configuration, the transmission direction never
• In this configuration,
changes the transmission direction never changes (MSB first)

Zambreno, Spring 2017 © ISU CprE 488 (Interfacing Technologies) Lect-04.13

 Slave to initiates
• Master Master the Data Transfer
data transfer by generating the START
condition followed by the start byte (with read/write bit set to
• Master 1,
initiates the mode)
i.e. read data transfer by generating the START condition followed
by the
• start
Afterbyte
the (with read/write
first ack from the bitslave,
set to the
1, i.e. read mode)
direction of data
• After the first ackand
changes fromthe themaster
slave, the direction
becomes of dataand
receiver changes
slaveand the master
becomes receiver and slave transmitter.
transmitter.
• The STOP
• The condition is still generated
STOP condition by the master
is still generated (master
by the sends
master not-ACK
(master
before generating
sends not-ACKthe STOP)
before generating the STOP)
 7.14 shows the I/O port locations of the synchronous serial ports for the
SSI(Synchronous Serial
microcontrollers discussed Interface)
in this book. Tables 2.7 and 2.8 describe ho
to the SSI modules on the TM4C123/TM4C1294.
• Typically communicate across short distances
• Characteristics:
• 4-wire synchronized (clocked) communications
bus
• supports single master and multiple slaves
• always full-duplex: Communicates in both
directions simultaneously
• multiple Mbps transmission speeds can be
achieved
• transfer data in 4 to 16 bit serial packets
 SSI Organization
• Two hardware FIFOs. Transmit FIFO and Receive FIFO
• Both FIFOs are 8 elements deep and 4 to 16 bits wide, depending on the selected data
width
• Shift registers (half of the distributed register)
• Data moves in and comes out from shift register
• Transmits and receives bits at the same time.
• SSI0_DR_R: FIFO receives and writes in this register
• Bus wiring: 4 I/O lines
• MOSI (Master Out Slave In) – carries data out of master to slave
• MISO (Master In Slave Out) – carries data out of slave to master
• Both MOSI and MISO are active during every transmission
• SS (or CS) – signal to select each slave chip
• System clock SCLK – produced by master to synchronize transfers
 Data in the master shift register are transmitted to the slave. Data in the sla
are transmitted to the master. Typically, the microcontroller is master and th
SPI Serial Peripheral Interface Bus
SSI Organization is the slave, but one can operate the microcontroller in slave mode. When d
SSI, you will need to consult the data sheets for your specific microcontrol
More detailed circuit diagram:
• More detailed circuit diagram:
details vary between
• details vary between different
different vendors and
vendors and implementations
implementations

• Timing diagram:
iming diagram:
Figure 7.15. A synchronous serial interface between a microcon
an I/O device.
system clock SCLK
Table 7.8 lists the SSI0 registers on the LM3S/TM4C. The LM3S/TM4C ca
slave mode, but we will focus on master mode. The PCTL bits are defined
writing data output:and 4.4.
MOSI or MISO Address 31-6 3 2 1 0 N
reading data input
$400F.E61C SSI3 SSI2 SSI1 SSI0 S
in the middle of bit:
3 ‐ 41
 SSI Signaling
• The SSI bus can operate with a single master device and with one or
more slave devices
• If a single slave device is used, the SS pin may be fixed to logic low
• Most slave devices have tri-state outputs so their MISO signal
becomes high impedance (logically disconnected) when the device is
not selected
• Devices without tri-state outputs can't share SPI bus segments with other
devices
• Only one such slave could talk to the master, and only its chip select could
be activated
 peripheral. It uses a single clock signal which is used to clock the
shift registers in each transmitter and receiver. The shift registers

SSI Operation
each have a small FIFO for buffering. The clock signal is shown as
being bidirectional: in practice it can be supplied by one of the
devices or by the device that is transmitting. Obviously care has to
be taken to prevent the clock from being generated by both sides
• Data registers in the master and the slave form a distributed register
and this mistake is either prevented by software protocol or
through the specification of the interface.
• When a data transfer operation is performed, this distributed register is
Serial peripheral interface
serially shifted by the SCK clock from the master
This bus is often referred to as the SPI and is frequently used
• SCK, is a 50% duty cycle clock generated on
byMotorola
the master.
processors such as the MC68HC05 and MC68HC11
microcontrollers to provide a simple serial interface. It uses the
• Can shift in burst mode basic interface as described in the previous section with a shift
register in the master and slave devices driven by a common clock.
• Transmitting device uses one edge of the clock to change its output, and the
It allows full-duplex synchronous communication between the
MCU and other slave devices such as peripherals and other
receiving device uses the other edge to accept the data
processors.

SPDR — m a st e r M C U SPDR — sl a v e M C U

M OSO
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

SS
SCK

M O SI
 Data Transmission
• To begin a communication, the bus master first configures the clock,
using a frequency less than or equal to the maximum frequency the
slave device supports. Such frequencies are commonly in the range
of 10 kHz–100 MHz
• The master then transmits the logic 0 for the desired chip over the
chip select line. A logic 0 is transmitted because the chip select line
is active low, meaning its off state is a logic 1; on is asserted with a
logic 0
• If a waiting period is required (such as for analog-to-digital
conversion), then the master must wait for at least that period of
time before starting to issue clock cycles
 stable. Data available is the time when the out
is the time when the input data must be valid.
Data Transmission During transmission, the output data will be v
S5min after the next clock edge. The maximum
• Transmission starts by software putting dataand intothethe transmit
minimum is 0.FIFO
Whenby writingthe set
receiving
to the SSI0_DR_R register hold time (S9) is 2 system bus periods. In orde
• Or, getting from the receive FIFO by reading from the the
error, SSI0_DR_R register.
data available from the device that is
• If data in FIFO Tx SSI distributed shift registerbefore will and end after) the data required by the
transmit that
this overlap that will determine the maximum
• SSI shift register transmits and receives bits at the same time can occur. The concepts of da
communication
• Distributed 8- to 32-bit register is serially shifted 4 topreviously
presented 16 bit positions
in Sectionby
4.2.the
SCK clock
• In implementation need to select which
edge of clk to transmit and other to
Receive
 Data Transmission
• Data valid from S5max (clk edg) to S5min (clk edg)
• S5 time is 1 system bus period (20ns for 50MHz)
• Communication to occur without error, the data available from the device
that is driving the data line must overlap (start before and end after) the data
required by the other device that is receiving the data
• This overlap that will determine the maximum frequency at which
synchronous serial communication can occur
 X 0 1 12 bits of data 0 Load input register; DAC regi
Example: Interface Maxim MAX5353 digital to analog unchanged.
converter with TM4C123...
X 1 0 XXXXXXXXXXXX X Update DAC register from inp
• Maxim MAX5353 12-bit digital to analog converter – This is the data
1 1 1 XXXXXXXXXXXX X Shutdown
• Word size: Initialization command first 3-bits (hence 000), then data 12-bits
(MSB first), then stop 1-zero
0 1= Total
1 information 16-bits
XXXXXXXXXXXX X No operation
• Clock phase: MAX5353 samples data on rising edge, so SSI must change data
Table 7.9. MAX5353 protocols
on falling edge. Polarity does not matter.
• BW: MAX5353 min clock low width = 40ns. Min Period = 80 ns. So, SSI period
>80ns. Say 100ns
 Universal Serial Bus (USB)
• Based on Polling – initiated by host
• Asynchronous, Half duplex
• Host-controlled, token-based high-speed serial network
• Handle many devices with different speed
• Much more complex than other 3-protocols
• Maximum range within 4-meters
• Now USB on 4th generation (USB 1, 2, 3, and 4): Varies on data transfer rates,
appearance, and direction of data processing
• USB 1: 2 speed, 1.5, 12 Mbps
• USB 2: 3 speed, 1.5, 12, 480 Mbps
• USB 3: Max 5Gbps
• USB 4: Max 40 Gbps
 hub or function, as shown in Figu
power to each device switching o
USB Hub other devices. The hub can filter o
• USB uses a tiered star topology, using a hub devices do not receive them. Beca
to connect additional devices. connected.
• A hub is at the center of each star.
• Each wire segment is a point-to- point
connection between the host and a hub or
function, or a hub connected to another
hub or function,
• Hub provides power, it can monitor power
to each device,
• switching off a device that is drawing too much
current without disrupting other devices.
• The hub can filter out high speed and full speed
transactions so lower speed devices do not
receive them
 USB-2 Architecture
• Uses 7-bit address, up to 127 devices can be connected.
• Use 4-shielded wires (+5V power, D+, D- and ground)
• D+ and D- are twisted pair differential data signals.
• Uses Non-Return to Zero Invert (NRZI) encoding to send data with a sync field
to synchronize the host and receiver clock
 USB Operation
• USB drivers will dynamically load and unload.
• When a device plugged into the bus, the host will detect this addition, interrogate the
device and load the appropriate driver.
• Similarly, when the device is unplugged, the host will detect its absence and automatically unload the
driver.
• USB architecture comprehends four basic types of data transfers:
• Control Transfers: Used to configure a device at attach time and can be used for other
device-specific purposes, including control of other pipes on the device.
• Bulk Data Transfers: Generated or consumed in relatively large quantities and have wide
dynamic latitude in transmission constraints.
• Interrupt Data Transfers: Used for timely but reliable delivery of data, for example,
characters or coordinates with human-perceptible echo or feedback response
characteristics.
• Isochronous Data Transfers: Occupy a pre-negotiated amount of USB bandwidth with a
pre-negotiated delivery latency. (Also called streaming audio/video real- time transfers).
 Pull-up Resistors
• USB device indicates its speed by pulling either the D+ or D- line to 3.3 V,
with pull-up resistor
• pull-up resistor attached to D+ specifies full speed, and a pull-up resistor
attached to D- means low speed.
• Device-side resistors are also used by the host or hub to detect the presence
of a device connected to its port.
• Without a pull-up resistor, the host or hub assumes there is nothing connected.
 is used to synchronize the clock of the receiver with th
USB Packets ID) is used to identify the type of packet that is being
The address field specifies which device the packet is
• USB transaction consists of three packets length allows for 127 devices to be supported. Addres
• Token Packet (header), is not yet assigned an address must respond to packets
• Host initiates all communication, field is made up of 4 bits, allowing 16 possible endpoi
• Describes the type of transaction, direction, device address and designated endpoint
can only have 2 additional endpoints on top of the def
• Optional Data Packet, (information) Checks are performed on the data within the packet p
• Contains information and Data bit CRC while data packets have a 16-bit CRC. EOP s
• Status Packet (acknowledge) Frame Packets (SOF) consist of an 11-bit frame numb
• Reporting if the data or token was received
500nssuccessfully,
on a fullorspeed
if the endpoint is stalled
bus or every or µs ± 0.0625 µs
125
not available to accept data
 Packet Fields
• Sync: All packets start with Sync field.
• 8 bits long at low and full speed or 32 bits long for high speed and is used to synchronize the
clock of the receiver with that of the transmitter
• 00000001 that becomes with NRZI as D+(0)10101011 or, D-(1)01010100
• PID (Packet ID): Used to identify the type of packet that is being sent
• Address: Specifies which device the packet is designated for
• 7-bits. 127 devices to be supported
• Address 0 is not valid, as any device which is not yet assigned an address must respond to
packets sent to address zero
• Endpoint: is made up of 4 bits, allowing 16 possible endpoints
• Low speed devices, can only have 2 additional endpoints on top of the default pipe
• Cyclic Redundancy Checks (CRC5/CRC16): Performed on the data within the packet
payload.
• All token packets have a 5- bit CRC
• Data packets have a 16-bit CRC.
 Example
• How a clk is synchronized with Sync: 00000001 bit?
• As USB uses NRZI format bit sequence 00000001 will become Z+=10101011, and Z-
=01010100. So, the receiver understand the clock.
• If, Address = 1100111, ENDP=0011, and polynomial (known by receiver and
sender) = x^5 + x^3 + x^2 + 1, what is CRC5.
• Representation of polynomial = 101101
• Do XOR on (1100111 0011 0000) by 101101 repetitively from left to right
 Packet Fields
• End of packet (EOP): 2-bits
• Frame Number: 11-bit frame number is sent by the host every 1ms ± 500ns on a full speed
bus or every 125 μs ± 0.0625 μs on a high speed bus
• End points (ENDP): Part of Token. described as sources or sinks of data, shown as EP0In ,
EP0Out
• As the bus is host centric, endpoints occur at the end of the communications channel at the USB
function.
• Host software may send a packet to an
endpoint buffer in a peripheral device.
• If the device wishes to send data to the host,
the device cannot simply write to the bus as
the bus is controlled by the host.
• Therefore, it writes data to endpoint buffer
specified for input, and the data sits in the buffer
until such time when the host sends a IN packet to
that endpoint requesting the data.
• Endpoints can also be seen as the interface
between the hardware of the function device and the
firmware running on the function device.
 Group PID Packet Identifier
Value

PID Token 0001

1001
OUT Token, Address + endpoint

IN Token, Address + endpoint

0101 SOF Token, Start-of-Frame marker and frame

number

1101 SETUP Token, Address + endpoint

Data 0011 DATA0

1011 DATA1

0111 DATA2 (high speed)

1111 MDATA (high speed)

Handshake 0010 ACK Handshake, Receiver accepts error-free

data packet

1010 NAK Handshake, device cannot accept data or

cannot send data

1110 STALL Handshake, Endpoint is halted or pipe

request not supported

0110 NYET (No Response Yet from receiver)

Special 1100 PREamble, Enables downstream bus traffic to

low-speed devices.

1100 ERR, Split Transaction Error Handshake

1000 Split, High-speed Split Transaction Token

0100 Ping, High-speed flow control probe for a

bulk/control endpoint
 Pipe
• pipe is a logical connection between the host and endpoint(s).
• Contains some parameters
• Transfer type: Control, Bulk, Iso or Interrupt type it uses to transfer,
• Direction of data flow
• Maximum packet/buffer sizes
• 2-types of pipes:
• Stream pipes: send unformatted data. Data flows sequentially and has a pre-
defined direction, either in or out.
• Support bulk, isochronous (real time transfer audio/video) and interrupt transfer types.
• Can either be controlled by the host or device.
• Message pipes: send defined USB format. They are host-controlled, which are
initiated by a request sent from the host.
• Data is then transferred in the desired direction, dictated by the request.
• Message pipes allow data to flow in both directions but will only support control transfers.
 USB Interface
• Modular Interface: Appropriate for adding USB functionality to an
existing system
• Embedded system hardware and software is standard RS232 serial
• Use standard existing approach to transfer data
• + Easy to use, --- Not optimized performing
• Integrated Interface
• Implementing USB interface for an embedded system is to integrate the
USB capability into the microcontroller itself
• ++ Great flexible and performance, --- Requires time and effort