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Tutorial Task 2

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4 views4 pages

Tutorial Task 2

Uploaded by

vcformal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Adding timing constraint, synthesizing report, writing timing constraint Tutorial

1. First, navigate to the MY_design folder created in Task 2.

2. Use ls make sure all the files created in Task 2 are still there. Then, open DC shell.

3. As in the previous tutorial, set your target and link library using target_library and
link_library respectively.

4. Use read_verilog MY_DESIGN.v to load MY_DESIGN.v Verilog file.


5. Next, type current_design MY_DESIGN into the DC shell. This makes MY_DESIGN the
top design module.

6. Then, type link into DC shell. The related linking message should be displayed as
following:

7. Afterwards, type check_design into DC shell. You should see a summary like the one
provided below. This command will check design violation in Design Compiler.

8. Follow the lines of code provided below to determine your timing constraints.

9. Use report_clock to check the setup of clock signal in your design. You should get all
information of the clock signal like period, duty-cycle.
10. Use report_timing to check the delay of any path in this design. You can set start point
and end point to get the max/min delay of this path.
11. Using write_script -out myd_design.wscr to export all your timing constraints to the file”
myd_design.wscr”. Using this file to comparing with your specification document, make
sure you didn’t miss any constraint.
12. Using write -format ddc -h -out unmapped_design.ddc to export all your timing
constraints to the file” unmapped_design.ddc”. This file can be used by other EDA tools
for future design check.

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