ARM Assembly

Memory access instructions Branch instructions

LDR Rd, [Rn] ; load 32-bit number at [Rn] to Rd B label ; branch to label Always
LDR Rd, [Rn,#off] ; load 32-bit number at [Rn+off] to Rd BEQ label ; branch if Z == 1 Equal
LDR Rd, =value ; set Rd equal to any 32-bit value (PC rel) BNE label ; branch if Z == 0 Not equal
LDRH Rd, [Rn] ; load unsigned 16-bit at [Rn] to Rd BCS label ; branch if C == 1 Higher or same, unsigned ≥
LDRH Rd, [Rn,#off] ; load unsigned 16-bit at [Rn+off] to Rd BHS label ; branch if C == 1 Higher or same, unsigned ≥
LDRSH Rd, [Rn] ; load signed 16-bit at [Rn] to Rd BCC label ; branch if C == 0 Lower, unsigned <
LDRSH Rd, [Rn,#off] ; load signed 16-bit at [Rn+off] to Rd BLO label ; branch if C == 0 Lower, unsigned <
LDRB Rd, [Rn] ; load unsigned 8-bit at [Rn] to Rd BMI label ; branch if N == 1 Negative
LDRB Rd, [Rn,#off] ; load unsigned 8-bit at [Rn+off] to Rd BPL label ; branch if N == 0 Positive or zero
LDRSB Rd, [Rn] ; load signed 8-bit at [Rn] to Rd BVS label ; branch if V == 1 Overflow
LDRSB Rd, [Rn,#off] ; load signed 8-bit at [Rn+off] to Rd BVC label ; branch if V == 0 No overflow
STR Rt, [Rn] ; store 32-bit Rt to [Rn] BHI label ; branch if C==1 and Z==0 Higher, unsigned >
STR Rt, [Rn,#off] ; store 32-bit Rt to [Rn+off] BLS label ; branch if C==0 or Z==1 Lower or same, unsigned ≤
STRH Rt, [Rn] ; store least sig. 16-bit Rt to [Rn] BGE label ; branch if N == V Greater than or equal, signed ≥
STRH Rt, [Rn,#off] ; store least sig. 16-bit Rt to [Rn+off] BLT label ; branch if N != V Less than, signed <
STRB Rt, [Rn] ; store least sig. 8-bit Rt to [Rn] BGT label ; branch if Z==0 and N==V Greater than, signed >
STRB Rt, [Rn,#off] ; store least sig. 8-bit Rt to [Rn+off] BLE label ; branch if Z==1 or N!=V Less than or equal, signed ≤
PUSH {Rt} ; push 32-bit Rt onto stack BX Rm ; branch indirect to location specified by Rm
POP {Rd} ; pop 32-bit number from stack into Rd BL label ; branch to subroutine at label
ADR Rd, label ; set Rd equal to the address at label BLX Rm ; branch to subroutine indirect specified by Rm
MOV {S} Rd, <op2> ; set Rd equal to op2
MOV Rd, #im16 ; set Rd equal to im16, im16 is 0 to 65535
MVN {S} Rd, <op2> ; set Rd equal to -op2
Interrupt instructions Logical instructions
CPSIE I ; enable interrupts (I=0) AND {S} {Rd,} Rn, <op2> ; Rd=Rn&op2 (op2 is 32 bits)
CPSID I ; disable interrupts (I=1) ORR {S} {Rd,} Rn, <op2> ; Rd=Rn|op2 (op2 is 32 bits)
Arithmetic instructions EOR {S} {Rd,} Rn, <op2> ; Rd=Rn^op2 (op2 is 32 bits)
BIC {S} {Rd,} Rn, <op2> ; Rd=Rn&(~op2) (op2 is 32 bits)
ADD {S} {Rd,} Rn, <op2> ; Rd = Rn + op2
ORN {S} {Rd,} Rn, <op2> ; Rd=Rn|(~op2) (op2 is 32 bits)
ADD {S} {Rd,} Rn, #im12 ; Rd = Rn + im12, im12 is 0 to 4095
LSR {S} Rd, Rm, Rs ; logical shift right Rd=Rm>>Rs (unsigned)
SUB {S} {Rd,} Rn, <op2> ; Rd = Rn - op2
LSR {S} Rd, Rm, #n ; logical shift right Rd=Rm>>n (unsigned)
SUB {S} {Rd,} Rn, #im12 ; Rd = Rn - im12, im12 is 0 to 4095
ASR {S} Rd, Rm, Rs ; arithmetic shift right Rd=Rm>>Rs (signed)
RSB {S} {Rd,} Rn, <op2> ; Rd = op2 - Rn
ASR {S} Rd, Rm, #n ; arithmetic shift right Rd=Rm>>n (signed)
RSB {S} {Rd,} Rn, #im12 ; Rd = im12 – Rn
LSL {S} Rd, Rm, Rs ; shift left Rd=Rm<<Rs (signed, unsigned)
CMP Rn, <op2> ; Rn – op2 sets the NZVC bits
LSL {S} Rd, Rm, #n ; shift left Rd=Rm<<n (signed, unsigned)
CMN Rn, <op2> ; Rn - (-op2) sets the NZVC bits
MUL {S} {Rd,} Rn, Rm ; Rd = Rn * Rm signed or unsigned
Notes Ra Rd Rm Rn Rt represent 32-bit registers
MLA Rd, Rn, Rm, Ra ; Rd = Ra + Rn*Rm signed or unsigned
value any 32-bit value: signed, unsigned, or address
MLS Rd, Rn, Rm, Ra ; Rd = Ra - Rn*Rm signed or unsigned
{S} if S is present, instruction will set condition codes
UDIV {Rd,} Rn, Rm ; Rd = Rn/Rm unsigned
#im12 any value from 0 to 4095
SDIV {Rd,} Rn, Rm ; Rd = Rn/Rm signed
#im16 any value from 0 to 65535
{Rd,} if Rd is present Rd is destination, otherwise Rn
Examples of flexible operand <op2> creating the 32-bit number. #n any value from 0 to 31
E.g., Rd = Rn+op2 #off any value from -255 to 4095
ADD Rd, Rn, Rm ; op2 = Rm label any address within the ROM of the microcontroller
ADD Rd, Rn, Rm, LSL #n ; op2 = Rm<<n Rm is signed, unsigned op2 the value generated by <op2>
ADD Rd, Rn, Rm, LSR #n ; op2 = Rm>>n Rm is unsigned
ADD Rd, Rn, Rm, ASR #n ; op2 = Rm>>n Rm is signed
ADD Rd, Rn, #constant ; op2 = constant