University of Technology

Department of Electrical Engineering

Microprocessor Engineering
Third Class

Lecture Eight/Part 2
The 8086 Microprocessor
Hardware Specifications

Assist. Prof. Dr. Hadeel Nasrat

Abdullah
 SYSTEM CLOCK
 To synchronize the internal and external operations of the 8086
microprocessor a clock (CLK) input signal is used. The CLK can be generated
by the 8284 clock generator IC.
 The 8086 is manufactured in three speeds: 5 MHz, 8 MHz and 10 MHz.
 For 8086, we connect either a 15-, 24- or 30-MHz crystal between inputs X1
and X2 of the clock chip.
 The fundamental crystal frequency is divided by 3 within the 8284 to give
either a 5-, 8- or 10-MHz clock signal, which is directly connected to the CLK
input of the 8086.

Lecture 8/Part 2: 8086 Up. H.W. Specification

Assist. Prof. Dr. Hadeel N. Abdullah
 Bus cycle and time state
A bus cycle defines the basic operation that a microprocessor performs to
communicate with external devices. Example of bus cycles are
• Memory read
• Memory write
• IO read
• IO write
The bus cycle of 8086 microprocessors consists of at least four clock
periods (T1, T2, T3, and T4)
 During T1 the 8086 puts an address on the bus.
 During T2 the 8086 puts the data on the bus (for write memory cycle) and
maintained through T3 and T4
 During T2 the 8086 puts the bus in high-Z state (for read cycle) and then the
data to read must be available on the bus during T3 and T4.
These four clock states give a bus cycle duration of 125 ns × 4= 500 ns in an 8-
MHz system.

Lecture 8/Part 2: 8086 Up. H.W. Specification

Assist. Prof. Dr. Hadeel N. Abdullah
Read Cycle
The read bus cycle begins with state T1. During this period, the 8086 output the 20bit
address of the memory location to be accessed on its multiplexed address/data bus AD0
through AD15 and multiplexed lines A16/S3 through A19/S6. Note that at the same time a
pulse is also produced at ALE. The signal is also supplied with the address lines.

Lecture 8/Part 2: 8086 Up. H.W. Specification

Assist. Prof. Dr. Hadeel N. Abdullah
 Write Cycle
The write bus cycle is similar to the read bus cycle except that signal
instead of the signal and signal is set to 1.

Lecture 8/Part 2: 8086 Up. H.W. Specification

Assist. Prof. Dr. Hadeel N. Abdullah
Idle States
If no bus cycles are required, the microprocessor performs what are known
as idle state. During these states, no bus activity takes place. Each idle state is one
clock period long, and any number of them can be inserted between bus cycles.
Idle states are performed if the instruction queue inside the microprocessor is full
and it does not need to read or write operands form memory.
Wait States
Wait states can be inserted into a bus cycle. This is done in response to
request by an event in external hardware instead of an internal event such as a
full queue. The READY input of the 8086 is provided specifically for this purpose.
As long as READY is held at the 0 level, wait states are inserted between states T3
and T4 of the current bus cycle, and the data that were on the bus during T3 are
maintained. The bus cycle is not completed until the external hardware returns
READY back to the 1 logic level.

Lecture 8/Part 2: 8086 Up. H.W. Specification

Assist. Prof. Dr. Hadeel N. Abdullah
Instruction Cycle
Time taken by processor to execute an instruction- specified in terms of no.
clock cycles needed to do it.
Once instruction is fetched and ready to be executed, then it can be
decoded and execution can be set.
Fetch-execute cycle can be divided into 6 stages
– Fetch instruction
– Decode instruction
– Calculate operand address
– Fetch operand
– Execute instruction
– Write/store result in memory

Lecture 8/Part 2: 8086 Up. H.W. Specification

Assist. Prof. Dr. Hadeel N. Abdullah
 DELAY LOOPS
* Certain amount of time or delay is associated with the execution of an
Instruction.
* Thus instruction execution gives us a means of generating a delay .
* Consider instructions below,
MOV CX, 100 4 cycles
HERE: LOOP HERE 17/5 cycles
 Total no. of clock cycles required is 4+(100*17) -12 =1692 cycles
 In a system with 12 MHz clock, clock period is .083µ Sec
 Total delay in this case .083 *1692 =140 µ Sec
 It is possible to fix the value of N so as to get a desired value of delay .
* To increase the delay, we can use the NOP (No operation ) instruction which
has no operands and no function except to execute within 3 cycles.
* The NOP instruction is usually used to reserve space in programs ,for
instructions which may needed to be added later.
Lecture 8/Part 2: 8086 Up. H.W. Specification
Assist. Prof. Dr. Hadeel N. Abdullah
EXAMPLE: Write a program to create a delay of 1 msec.
Solution:
MOV CX,N 4 cycle
HERE: NOP 3 cycle
LOOP HERE 17/5 cycle

• Most of the delay occurs within the loop

• the total cycles of delay is =[(3+17) x N]-12.
• Total delay time =1 m sec =20N x 0.083 µsecs
• For 1 msec delay ,the value of N =602 or 25AH
• This value of N is inserted into program to create a delay
of 1msec
• Generating delays in this manner is called software delays
Lecture 8/Part 2: 8086 Up. H.W. Specification
Assist. Prof. Dr. Hadeel N. Abdullah
What is clock cycle, machine cycle, and
instruction cycle in a microprocessor?
The speed of a computer processor, or CPU, is determined by the clock cycle, which
is the amount of time between two pulses of an oscillator
The sequence of operations that the cpu has to carry out while execution is called
instruction cycle.
machine cycle the steps performed by the computer processor for each machine
language instruction received. The machine cycle is a 4 process cycle that includes
reading and interpreting the machine language, executing the code and then storing
that code.

Lecture 8/Part 2: 8086 Up. H.W. Specification Assist.

Prof. Dr. Hadeel N. Abdullah
 Homework
1. The pin of minimum mode AD0-AD15 has ____________ address
A. 16 bit B. 20 bit C. 32 bit D. 4 bit

2. The pin of minimum mode AD0- AD15 has _________ data bus
A. 4 bit B. 20 bit C. 16 bit D. 32 bit
3. The address bits are sent out on lines through __________
A. A16-19 B. A0-17 C. D0-D17 D. C0-C17
4. ________ is used to write into memory
A. RD B. WR C. RD / WR D. CLK
5. The RD, WR, M/IO is the heart of control for a __________ mode
A. minimum B. maximum C. compatibility mode D. control mode
6. In a minimum mode there is a ___________ on the system bus
A. single B. double C. multiple D. triple
7. If MN/MX is low the 8086 operates in __________ mode
A. Minimum B. Maximum C. both (A) and (B) D. medium

Lecture 8/Part 2: 8086 Up. H.W. Specification Assist.

Prof. Dr. Hadeel N. Abdullah
Homework
8. In max mode, control bus signal So,S1 and S2 are sent out in ______ form
A. decoded B. encoded C. shared D. unshared
9. The _________ bus controller device decodes the signals to produce the
control bus signal
A. internal B. data C. external D. address
10. What is DEN?
A. direct enable B. data entered C. data enable D. data encoding
11. ALE stands for ___________
A. address latch enable B. address level enable
C. address leak enable D. address leak extension
12. During a read operation the CPU fetches ________.
A. a program instruction B. another address
C. data itself D. all of the above
Lecture 8/Part 2: 8086 Up. H.W. Specification
Assist. Prof. Dr. Hadeel N. Abdullah