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Unit-3 Microprocessor

The document discusses various aspects of microprocessors, including their architecture, data buses, and communication protocols. It outlines the functions of different buses such as data, address, and control buses, as well as the role of registers and memory in processing instructions. Additionally, it touches on interrupt handling and the significance of timing signals in microprocessor operations.

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abiavinash128
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
19 views

Unit-3 Microprocessor

The document discusses various aspects of microprocessors, including their architecture, data buses, and communication protocols. It outlines the functions of different buses such as data, address, and control buses, as well as the role of registers and memory in processing instructions. Additionally, it touches on interrupt handling and the significance of timing signals in microprocessor operations.

Uploaded by

abiavinash128
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Date /

basially hau thou


Systuma inmicnophotekAA
Cepu)to aecoqnie_and tasy

,
a teutnal poctskin nat
pand i

Out and eutput intulau to

ot pkngam instuetis inpt


handle comnuhicatin betoun the

the eide oold and memory


imssutonl and dat
Micuaproc tNOAA hich dave mmphy Qnd00nieus
nput Lautpt all en the yam chip
annangemust
Calud Mic3D COntrollu

koch bit o wtd


ic Sepexate tl Bae clo notemploy Suial
Sent alo ng it
tuanmisson oit all the bit of a woxd
Busee cmploy paallel tranamiskhon buing nnt along a siqle conductox.

Adceess bus

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Memos
Memny Output outpit
ROM pot
Micso Adses RAM
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ata bu

Contuol bu

Ghenual fom a mucoophoON Sytom and its busu


AGE
Date /

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A

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aihtlectnical gnala an be and
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ay L bit a olata a0nd
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he

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to
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data fom an cingud ceuie atalata to am


Date /

tem READ ed besin Am npust


otput dsite Jhe

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for tndinga ig nalJhe tondxol bs
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ota bw

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and ngint

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Gsunal iiinoal hanchittwe


ofaa minnpaoLCOl
Date /

micopsocesor
ad

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aritknastiand logie i niti iuagpabaor.
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insdrub odata mosyt han to supply

thei data hu. Since enlaysen nnohyshilocatien can be


Date /

addamdat

sugisaOA laq aita


Stata agista,oa ondilin Cad

att
londiuidualbita oidhach bit aauing

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apuial mguifcanu Jhe bit av callid

ttoindate al speui state

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Rent

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0CCUN dos nat ccw


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stdtol allas te CPU to kep tak
it pealin na pBgPamJhia suqintia Contoin the adda
mamony loatie toat Conlau the nut prcqram.

gita updaled.
s extuded. the
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the data the acumt
00000
Date /

Jhu aunlt is than stord a a meaoayloanon addamel by the


mmoyuadarn kugitu

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Jhis
onualan
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qu
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hethenotan

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RAM. Jhe wtack
pal
tae mmoy a ahich program Cauntia Valuus cam.
he stoud.

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data and taket intgaaid
numbu
bing apsatad.
Jhe Soww s the bits countd by each timu
by thu CT bit th kit
Date /

statd
nn clokadid by 2Jhe timu tann be

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TRO TR 1 to 1 amd

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alloseing a
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INTO DA INI4 pin tn tmicmortholla going
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Sntosagt iIntuut foru tapragam
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36
emable ugisl IE at addruh

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PD
Date /

Micnochip TM micnot onteollr


Anote
widely nd amily &-bt micoocontaolle es trat
provicud by Micobip TM Jhe tem PIC

nac xOLOnt rollus Jhu


fem architectuw temad
Hawad anchitutn Havad ahi techu
executn be
tnablesat
Spud achicved
a gewn clock

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memoy
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2AM
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Date /

Time ) TIso|Tik)
Rco

Hmu ,ond
RCI
VTISI JCp2

Comparu pOM
Intesupt RU3
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CPU SDI
intoloct, SDO

S DA

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WART
RCT
RX

RRO
INTE
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RBIF
EPROM RB+

oogramCode
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timd A NO RAo
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Poxt A
AN2
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ANG PortE
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RE
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0SNtor
op hioh

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post
RDO

Pot D
Dsillato Mtes
clecr

RDt
VDD VDD

Plc IGC+4|44A
Date /

3
tcrs Port ba

and 3 input

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nput lad Output poak


fo
e bidisekional input loukaut port A
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pOat B

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t bidisulional inputloutput B
fon the bídisectional input loutput port E

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fins al post A and post E cam also be nd ad o analouge inpuk

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3. Jim

fimns timu o, timn 1, and mu .


be etu dhe intnal

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modul
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Anial communiataona
providae
a ls- šn biclictional istalau hat
oith a Can abo Ld for conned nq a

to slaye micoLont vo lleus -


Date /

s.Pallel dau pot


and E amd enablu
pou

mocotaallu do piauide

6.
extenal tlot
Pin 13 a osallatoy

Soe input pn u

Cnd s takmlens to

Pin 1 th maa cha MCLR

uxt

o input laukpt coatnla


spial-puapo ugiotus
Jhe

frle
Banko Bankl adc

INDE 8Dh
INDE
TMRO DPTION
0h PCL 82h
03h STATUS S TATUS

PDRTA
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TRISA
ttrt

6.5 4 32
RPO Reqstu ]
PORTC TRISC Khbank Selt bit

b
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84h NOT- TO Rut statu
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OAh PCAATH PcLATH
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o th 8ch
PIR P1EI
STATUS
PON
Loh

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PR2 A2h
13h

$SPLON SS21A1
1Sh
16h CPRIH

RcSTA TXSTA
|Ah RGRE Ga
Bh
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ADRES
4Eh.

1Fh Ah
micaotontollu ea
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micaDLOntola hudto be
faloiggatan
cenndud

Numba o input oukput pin


Hos man nput loutput phnk aai going
task Concand?

3Intlace suquinud
hwhat be
gaing
PWM
2.qta PlCaCH tw

ZMomatuyiseh

Hoks

Jhe ta kes hime to exeutolinctuet'ans thiu


micxoprDCCSIOA
dtsmiaud by th pzoieSSax clock

ROM EPROM RAM Jimws I[o pot Snteomps


80bIAH 128 S
8olsIAH HK 128

8o59AH o 156 6

851H HK |28 S

Intel &osI amiy mnmkea


Date /

US AR T
EPROM RAM ADC channs CCP
moc

128

142
Piclkc3
33
PTCIc6HA
33 142
PIcGCG SA
PT dlGC
PI clkc3A
33 l92
PICGC2A

PIC1GC membuu
lamiy

A A sbrá al mitabtandro llu mgbt


be main

tmpeaatahsmo
Connected to on ADe nput ls e mcDLOntrollu
Ihe minontollu

BCh Qutpt we can be uadoStch


*Jhe
t4HCTS 13,

he
MinoLontola.
t postia gng alg akcloLknptm
8CD data

Qutpat
pOxt B D
{up- Jlop

68HC)1.
BCD data,
Poat C

oatus Lnput
Tomp Jiming puby
Port E
with its
t4HCTa13
ADC miapontolle

enpenalone
manrmnt
Date /

|Qomusti hlasling naclcia


Jhe

and motor sped ia táe analogu -te-digital' iaput poi

the
Poxt A provica
do contaol machine and
H displa Postc
input trom the

ybaad tund to input o Hho machine


pgam
letions Jhe PhM ection el the tm produ aPhM Siqml to

Control the spud macline


motox Jhe
pragm
maline

Bensor
Tenporata

ADC
Spud t input
lim
Pont B

Pulse th moduloted
Aianhl to control motor
opud
Doos mith, ohm door opund

Watu-dsith
Hot watu valve ROM
Cold watu vav
Post C
Watu pomp Control

PAtA
Aoon lock

Buzz
EPROM Kegboad
Moto direchon

Heatu ontrol
Date /

>Micz0Ocnt3ollu
comptu
aAl micxo contxol CMe) a small
to covalapiha
Dt combin the fantin a CPU
ystons

hszmongandinpit Joatpt
inteyau all onasingh chip

duuiu
mabeddud sustenndmial
sdily

bcwn MicxopsDcM0L iamd t Micxootaol

Micsocontxolle Micxoprohes

A micaoLodanlla is a Apeialid micxopzoAQL idnigud


to be
guusal -ppt

unit
a dyuut
Jlae minoLontsollea 9Aud to

a paaticulas tasks a ceatain task


ufom

7ts

14 tontasns CPURAM, RoMkqistat Tt


|isand inpud Zouut pot

dui
ng clipconpatu ealled

AicaDCOntyolle lau no
advantageIt haue

Can dide
RA M,Ro M

Port as neecud
Q0000
Date /

Tts nalla 1ts

Its procsing

Haxvand Aachitectw Von Neumann


Ascutectur

kach intueten Qn
ntanal
spsala atanal epatasn

Zon exanple Tellvision


tox czample peAOnal camputr

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