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Be Computer-Engineering Semester-4 2023 November Microprocessor-Pattern-2019

This document is an examination paper for a Microprocessor course, consisting of 8 questions with options to choose between pairs. Each question covers various topics related to the 80386 microprocessor, including address translation, protection mechanisms, task switching, and interrupt handling. The exam is designed for a duration of 2.5 hours and carries a maximum of 70 marks.

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asusawani
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0% found this document useful (0 votes)
31 views2 pages

Be Computer-Engineering Semester-4 2023 November Microprocessor-Pattern-2019

This document is an examination paper for a Microprocessor course, consisting of 8 questions with options to choose between pairs. Each question covers various topics related to the 80386 microprocessor, including address translation, protection mechanisms, task switching, and interrupt handling. The exam is designed for a duration of 2.5 hours and carries a maximum of 70 marks.

Uploaded by

asusawani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Total No. of Questions : 8] SEAT No.

8
23
P9113 [Total No. of Pages : 2

ic-
[6179]-238

tat
S.E. (Computer)

3s
MICROPROCESSOR

9:2
02 91
(2019 Pattern) (Semester - IV) (210254)

9:3
0
Time : 2½ Hours] [Max. Marks : 70

30
3/1 13
Instructions to the candidates:
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1) Answer Q1 or Q2, Q3 or Q4, Q5 or Q6, Q7 or Q8.
2/2
.23 GP

2) Neat diagrams must be drawn wherever necessary.


3) Figures to the right indicate full marks.
E
82

8
C

23
ic-
Q1) a) With the help of necessary diagram, explain the complete address
16

tat
translation process in 80386. [6]
8.2

3s
b) Enlist various types of system and non system descriptors in the 80386.
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9:2
91
Explain their use in brief. [6]
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9:3
30

c) Write a short note on GDTR, IDTR, LDTR. [6]


30
01
02

OR
2/2
GP

Q2) a) Explain the page translation process in 80386. [6]


3/1

b) Explain the use of following instructions in detail. [6]


CE
82

8
23
i) LGDT
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ic-
16

ii) LIDT
tat
8.2

3s

iii) SIDT
.24

9:2
91

c) Draw and explain the general descriptor format available in various


49

9:3

descriptor tables. [6]


30
30
01
02
2/2

Q3) a) Explain various aspects of protection mechanism of segmentation unit.[6]


GP
3/1

b) Write a short note on EPL, DPL, and IOPL. [6]


CE
82

c) With the help of neat diagram explain various levels of protection and
.23

rules for protection check. [5]


16

OR
8.2
.24

P.T.O.
49
Q4) a) Explain how control transfer instructions are executed using the call gate

8
in the system? [6]

23
ic-
b) Elaborate on the concept of combining segment protection and page

tat
level protection in 80386. [6]

3s
c) List and explain various privilege instructions. [5]

9:2
02 91
9:3
0
30
Q5) a) Explain the TSS descriptor and its role in multitasking.
3/1 13 [6]
b) Explain the structure of V86 task in detail. How is protection provided
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2/2
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within the V86 task? [6]


c) Differentiate between real mode and virtual mode. [6]
E
82

8
C

23
OR

ic-
Q6) a) Define task switching and explain the steps involved in task switching
16

tat
8.2

operation. [6]

3s
.24

9:2
b) List and explain various features of virtual 8086 mode. [6]
91
49

9:3
c) Draw and explain task state segment of 80386. [6]
30
30
01
02

Q7) a) With the help of neat diagram explain the process of handling interrupts
2/2
GP

in protected mode. [6]


3/1
CE

b) Explain different types of exceptions in 80386 with suitable examples. [6]


82

8
23
.23

c) With the help of neat diagram explain the architecture of typical


microcontroller. [5] ic-
16

tat
8.2

3s

OR
.24

9:2

Q8) a) Explore various descriptors present in IDT of 80386. [6]


91
49

9:3

b) Explain the following exceptions in brief. [6]


30
30

i) Divide error
01
02
2/2

ii) Invalid opcode


GP
3/1

iii) Overflow
CE
82

c) Explain various features of the 8051 microcontroller. [5]


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16
8.2


.24

[6179]-238 2
49

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