ESMT AD52090

2x30WStereo / 1x60W Mono Class-D Audio Amplifier

With Power Limit

Features Applications
 Single supply voltage  TV audio
4.5V ~ 26V for loudspeaker driver  Boom-Box
Built-in LDO output 5V for others  Powered speaker
 Supports Multiple Output Configurations  Monitors
BTL Mode: 30W/CH into 8at 24 V  Consumer Audio Equipment
BTL Mode: 30W/CH into 4at 18 V
PBTL Mode: 60W/CH into 4at 24 V Description
PBTL Mode: 45W/CH into 4at 18 V
PBTL Mode: 60W/CH into 2at 18 V The AD52090 is a high efficiency stereo class-D
 Loudspeaker performance audio amplifier with adjustable power limit
BTL Mode: 30W/CH into 8<1% THD+N@24V function.The loudspeaker driver operates from
BTL Mode: 30W/CH into 4<1% THD+N@18V 4.5V~26V supply voltage and analog circuit
 >90% efficient Class-D operation eliminates need operates at 5V supplyvoltage. It can deliver 30W/CH
for heat sink output power into 4or 8loudspeakerwithin 1%
 Differential inputs THD+N at 24V supply voltage.
 Four selectable, fixed gain settings AD52090 provides parallel BTL (Mono)
 Internal oscillator application, and it can deliver 60W into 4
 Short-Circuit protection with auto recovery option loudspeaker at 24V supply voltage. The adjustable
 Under-Voltage detection power limit function allows user to set a voltage rail
 Over-Voltage protection lower than half of 5V to limit the amount of current
 Pop noise and click noise reduction through the speaker.
 Adjustable power limit function for speaker
protection Output DC detection prevents speaker damage
 Output DC detection for speaker protection from long-time current stress.AD52090output short
 Over temperature protection with auto recovery circuit and over temperature protection include
auto-recovery feature.

Simplified Application Circuit

AD52090
1uF 0.22uF
LINP BSPL
1uF OUTPL
LINN LC Filter
1uF OUTNL
RINP
BSNL
1uF 0.22uF
RINN

0.22uF
GAIN0 BSPR
GAIN1 OUTPR
LC Filter
AGND OUTNR
1uF BSNR
0.22uF
GVDD

PBTL PVCCL 4.5V to 26V

PLIMIT PVCCR
SD AVCC
FAULT PGND

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 1/26
ESMT AD52090
Pin Assignments

E- TSSOP -28 L
( TOP VIEW )
SD 1 28 PVCCL
FAULT 2 27 PVCCL
LINP 3 26 BSPL
LINN 4 25 OUTPL
GAIN 0 5 24 PGND
GAIN 1 6 23 OUTNL
AVCC 7 22 BSNL
AGND 8 21 BSNR
GVDD 9 20 OUTNR
PLIM 10 19 PGND
RINN 11 18 OUTPR
RINP 12 17 BSPR
NC 13 16 PVCCR
PBTL 14 15 PVCCR

Pin Description
E-TSSOP
NAME TYP DESCRIPTION
-28L
Shutdown signal for IC (low = disabled, high = operational). Voltage compliance
SD 1 I
to AVCC.

Open drain output used to display short circuit or dc detect fault. Voltage

compliant to AVCC. Short circuit faults can be set to auto-recovery by

FAULT 2 O
connecting FAULT pin to SD pin. Otherwise, both short circuit faults and dc
detect faults must be reset by cycling AVCC.

LINP 3 I Positive audio input for left channel.

LINN 4 I Negative audio input for left channel.

GAIN0 5 I Gain select least significant bit. Voltage compliance to AVCC.

GAIN1 6 I Gain select most significant bit. Voltage compliance to AVCC.

AVCC 7 P Analog supply.

AGND 8 P Analog signal ground. Connect to the thermal pad.

GVDD 9 O 5V regulated output, also used as supply for PLIMIT function.

Power limit level adjustment. Connect a resistor divider from GVDD to GND to

PLIMIT 10 I set power limit. Give V(PLIMIT) <2.4V to set power limit level. Connect to

GVDD (>2.4V) or GND to disable power limit function.

RINN 11 I Negative audio input for right channel.

RINP 12 I Positive audio input for right channel.

NC 13 NA NC pin.

Parallel BTL mode switch, high for parallel BTL output. Voltage compliance to
PBTL 14 I
AVCC.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 2/26
ESMT AD52090
High-voltage power supply for right-channel. Right channel and left channel
PVCCR 15,16 P
power supply inputs are connect internal.

BSPR 17 I Bootstrap I/O for right channel, positive high side FET.

OUTPR 18 O Class-D H-bridge positive output for right channel.

PGND 19 P Power ground for the H-bridges.

OUTNR 20 O Class-D H-bridge negative output for right channel.

BSNR 21 I Bootstrap I/O for right channel, negative high side FET.

BSNL 22 I Bootstrap I/O for left channel, negative high side FET.

OUTNL 23 O Class-D H-bridge negative output for left channel.

PGND 24 P Power ground for the H-bridges.

OUTPL 25 O Class-D H-bridge positive output for left channel.

BSPL 26 I Bootstrap I/O for left channel, positive high side FET.

High-voltage power supply for right-channel. Right channel and left channel
PVCCL 27,28 P
power supply inputs are connect internal.

Thermal Pad P Must be soldered to PCB’s ground plane.

Ordering Information

Product ID Package Packing Comments

2500 Units / Reel

AD52090-QG28NRR E-TSSOP 28L Green
1 Reels / Small Box

Available Package
Package Type Device No. θJA(℃/W) θ JT(℃/W) Ψ JT(℃/W) Exposed Thermal Pad

E-TSSOP 28L AD52090 28 27.1 1.33 Yes (Note 1)

Note 1.1: The thermal pad is located at the bottom of the package. To optimize thermal
performance, soldering the thermal pad to the PCB’s ground plane is necessary.
Note 1.2: θ JA is simulatedon a room temperature (TA=25℃), natural convection environment test
board, which is constructed with a thermally efficient, 4-layers PCB (2S2P). The
measurement is simulated using the JEDEC51-5 thermal measurement standard.
Note 1.3: θ JT represents the thermal resistance for the heat flow between the chip junction and the
package’s top surface. It’s extracted from the simulation data with obtaining a cold
plate on the package top.
Note 1.4: Ψ JTrepresents the thermal parameterfor the heat flow between the chip junction and
the package’s top surface center. It’s extracted from the simulation data for
obtainingθ JA, using a procedure described in JESD51-5.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 3/26
ESMT AD52090
Marking Information
AD52090

● Marking Information ESMT

AD 52090
Line 1：LOGO Tracking Code
Line 2：Product No
Line 3：Tracking Code PIN 1 DOT

Absolute Maximum Ratings

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT
PVCC Supply voltage PVCCL, PVCCR, AVCC -0.3 30 V
SD , GAIN0, GAIN1, PBTL, FAULT -0.3 30
VI Interface pin voltage V
PLIMIT -0.3 5.5
o
TA Operating free-air temperature range -40 85 C
o
TJ Operating junction temperature range -40 150 C
o
Tstg Storage temperature range -65 150 C
BTL (Stereo) 3.2 
RL Minimum Load Resistance PBTL (Mono) 3.2 
PBTL (Mono) ≦ 18V 1.6 
Human Body Model ±2k
ESD V
Charged Device Model ±500

Recommended Operating Conditions

SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT
PVCC Supply voltage AVCC, PVCCL, PVCCR 4.5 26 V
VIH High-level input voltage SD , GAIN0, GAIN1, PBTL 2 V
VIL Low-level input voltage SD , GAIN0, GAIN1, PBTL 0.8 V
VOL Low-level output voltage FAULT, RPULL-UP=100k, PVCC=18V 0.8 V

IIH SD , GAIN0, GAIN1, PBTL, VI=2V,

High-level input current 50 uA
PVCC=18V

IIL
SD , GAIN0, GAIN1, PBTL, VI=0.8V,
Low-level input current 5 uA
PVCC=18V
o
TA Operating free-air -40 85 C
temperature

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 4/26
ESMT AD52090
General Electrical Characteristics
 PVCC=24V, RL=8TA=25°C (unless otherwise noted)

SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT

=2V, no load,
ICC(q) Quiescent supply current SD 20 35 mA
PVCC=12V
Quiescent supply current SD =0.8V, no load,
ICC(SD) <12 25 uA
in shutdown mode PVCC=12V
Drain-source on-state
resistance-High side 90 m
NMOS PVCC=12V, Id=500mA,
RDS(on)
Drain-source on-state TJ=25°C
resistance-Low side 90 m
NMOS
Class-D output offset
|VOS| voltage (measured PVCC=12V VI=0V, mV
1.5 15
Gain=36dB
differential)
tON Turn-on time SD =2V 90 ms

tOFF Turn-off time SD =0.8V 2 us

Operating current for
IAVCC 8.5 12.8 mA
AVCC
GVDD Regulator output IGVDD=0.1mA 4.75 5 5.25 V

GAIN1 GAIN0=0.8V 17.5 18.5 19.5

=0.8V GAIN0=2V 25 26 27
G Gain dB
GAIN0=0.8V 31 32 33
GAIN1
=2V GAIN0=2V 35 36 37

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 5/26
ESMT AD52090
Electrical Characteristics and Specifications of Loudspeaker Driver
 PVCC=24V, RL=8with passive LC low-pass filterin ESMT EVB (unless otherwise noted).
SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT
THD+N=0.3%, f=1kHz, PVCC=24V 30
THD+N=10%, f=1kHz, PVCC=12V 10

THD+N=0.35%,f=1kHz, VCC=21V, 4ohm 30

Output power (BTL)
THD+N=0.95%,f=1kHz, VCC=18V, 4ohm 30

PO THD+N=10%,f=1kHz, PVCC=12V, 4ohm 19 W

THD+N=10%,f=1kHz, PVCC=8V, 4ohm 8.5

THD+N=0.27%, f=1kHz, PVCC=24V, 4ohm 60

Output power (PBTL) THD+N=10%, f=1kHz, PVCC=18V, 4ohm 45

THD+N=0.5%, f=1kHz, PVCC=18V, 2ohm 60

PVCC=24V, RL=8f=1kHz, PO=15W
0.025
Total harmonic distortion (half-power)
THD+N %
plus noise PVCC=12V, RL=8f=1kHz, PO=5W
0.18
(half-power)
Maximum output at THD+N<1%, f=1kHz,
SNR Signal to noise ratio 103 dB
Gain=18.5dB, a-weighted
F=20Hz ~ 20kHz, Gain=18.5dB, a-weighted
Vn Output integrated noise 75 uV
filter, RL=8

Power Supply Rejection Vripple=200mVpp at 1kHz, Gain=18.5dB, inputs

KSVR -70 dB
Ratio ac-grounded

X-talk Crosstalk F=1kHz, VO=1Vrms, Gain=18.5dB -95 dB

fOSC Oscillator frequency 250 310 370 kHz

o
Thermal trip point 170 C
TSENSOR
o
Thermal hysteresis 35 C

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 6/26
 ESMT AD52090
Typical Characteristics

THD+N vs. Output Power, 8 load(BTL) THD+N vs. Output Power, 4 load(BTL)
20 10
Gain=26dB Gain=26dB
10 Load=8ohm 5 Load=4ohm
5
2

2
1

THD+N(%)
THD+N(%)

1
0.5
0.5

0.2
0.2
0.1
0.1
24V 21V
0.05
0.05 18V
21V
18V 12V
0.02 12V 0.02 8V
8V
0.01 0.01
10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 100 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 100

Output Power(W) Output Power(W)

THD+N vs. Output Power, 4 load (BTL) THD+N vs. Output Power, 2 load (PBTL)
10 20
Gain=26dB Gain=26dB
5 Load=4ohm 10 Load=2ohm
V PLIMIT =1.678V
5
2

2
1
THD+N(%)
THD+N(%)

1
0.5
0.5

0.2
0.2
0.1
0.1
18V
0.05
24V 0.05 15V
12V
0.02 0.02

0.01 0.01
10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 100 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 100

Output Power(W) Output Power(W)

Noise, 24V, 4 load (BTL) Supply Ripple Rejection Ratio vsFrequency (BTL)
200u +0
Gain=18.5dB -5 Gain=26dB
Load=4ohm -10 PVCC = 12VDC + 200mVPP
-15 Load=8ohm
100u
-20
80u
70u -25
60u -30
50u
RCH -35
PSRR(dB)

40u LCH -40

V

30u -45
-50
20u -55
-60
-65
-70
10u
-75
8u
7u -80
6u -85
0u
20 50 100 200 500 1k 2k 5k 10k 20k -90
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency(Hz) Frequency(Hz)

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 ESMT AD52090

Maximum Output Power vs Supply Voltage (BTL) Maximum Output Power vs. Supply Voltage (BTL)
50 100
Gain=26dB Gain=26dB
45 Load=8ohm 90 Load=4ohm
Maximum Output Power (W)

Maximum Output Power (W)

40 80

35 70

30 60

25 50

20 40

15 30

10 20
THD+N = 1% THD+N = 1%
5 THD+N = 10% 10 THD+N = 10%

0 0
4 6 8 10 12 14 16 18 20 22 24 26 4 6 8 10 12 14 16 18 20 22 24 26
Supply Voltage (V) Supply Voltage (V)

Maximum Output Power vs Supply Voltage (BTL) Maximum Output Power vs Supply Voltage (PBTL)

100 100
Gain=26dB Gain=26dB
90 Load=6ohm 90 Load=4ohm
Maximum Output Power (W)

Maximum Output Power (W)

80 80
70 70
60 60
50 50
40 40
30 30
20 20
THD+N = 1% THD+N = 1%
10 THD+N = 10% 10 THD+N = 10%
0 0
4 6 8 10 12 14 16 18 20 22 24 26 4 6 8 10 12 14 16 18 20 22 24 26

Supply Voltage (V) Supply Voltage (V)

Maximum Output Power vs Supply Voltage (PBTL)

160
Gain=26dB
Load=2ohm
Maximum Output Power (W)

140

120

100

80

60

40
THD+N = 1%
20
THD+N = 10%
0
4 6 8 10 12 14 16 18 20 22 24 26
Supply Voltage (V)

Note: Dashed Line represent thermally limited regions.

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 ESMT AD52090

THD + N (%) vs. Frequency, 24V, 8 load (BTL) THD + N (%) vs. Frequency, 24V, 4 load (BTL)
10 10

5
Gain=26dB Po=1W 5 Gain=26dB Po=1W
Load=8ohm Po=5W Load=4ohm Po=5W
2 Po=10W 2 Po=10W
1 1

0.5 0.5
THD+N(%)

THD+N(%)
0.2 0.2

0.1 0.1

0.05 0.05

0.02 0.02

0.01 0.01

0.005 0.005

0.002 0.002

0.001 0.001
20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k

Frequency(Hz) Frequency(Hz)

THD + N (%) vs. Frequency, 18V, 2 load (PBTL) Gain vs. Frequency, 12V, 8 load (BTL)
+5
10
Po=1W +4.5 Gain=26dB
5 Gain=26dB +4 Load=8ohm
Load=2ohm Po=5W
Po=10W
+3.5 Cin=4.7uF
2 +3

1 +2.5
+2
0.5 +1.5
THD+N(%)

+1
Gain (dB)

0.2 +0.5

0.1 -0
-0.5
0.05 -1
-1.5
0.02
-2
0.01 -2.5
-3
0.005
-3.5
-4
0.002
-4.5
0.001 -5
20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k

Frequency(Hz) Frequency(Hz)

Gain vs. Frequency, 12V, 4 load (BTL) Gain vs. Frequency, 12V, 2 load (PBTL)
+5 +5
+4.5 Gain=26dB Gain=26dB
+4 Load=4ohm +4 Load=4ohm
+3.5 Cin=4.7uF Cin=4.7uF
+3 +3
+2.5
+2 +2
+1.5
+1 +1
Gain (dB)

Gain (dB)

+0.5
-0
+0
-0.5
-1
-1
-1.5
-2
-2
-2.5
-3
-3
-3.5
-4
-4
-4.5

-5
20 50 100 200 500 1k 2k 5k 10k 20k
-5
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency(Hz) Frequency(Hz)

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 ESMT AD52090

Efficiency, 8 load / 2ch (BTL) Efficiency,4 load / 2ch (BTL)

100 100

90 90

80 80

70 70

Efficiency(%)
Efficiency(%)

60 60

50 50

40
40

30
30

20
20 12V
12V
18V
Gain=26dB 18V 10 Gain=26dB
24V
10
24V Load=4ohm
Load=8ohm
0
0
0 10 20 30 40 50 60 70 80
0 10 20 30 40 50 60 70 80
Output power(W) Output power(W)

Efficiency,4 load (PBTL) Efficiency,2 load (PBTL)

100 100
90 90
80 80

70 70
Efficiency(%)
Efficiency(%)

60 60

50 50

40 40

30 30

20 12V 20 12V
18V 10 15V
10 Gain=26dB Gain=26dB
Load=4ohm 24V 18V
Load=2ohm
0 0
0 20 40 60 80 100 120 0 20 40 60 80 100 120
Output power(W) Output power(W)

Cross-Talk,24V, 8 load (BTL) Cross-Talk,24V, 4 load (BTL)

+0 T T T T T
+0 T T T T T

-10 Gain=26dB -10

Gain=26dB
Load=8ohm Load=4ohm
-20 -20
Cin=4.7uF Cin=4.7uF
-30 Vo=1Vrms -30 Vo=1Vrms
-40 -40

-50 -50
Crosstalk (dB)

Crosstalk (dB)

-60 -60

-70 -70

-80 -80

-90 -90

-100 -100

-110 -110

-120 -120

-130 -130

-140 -140
20 50 100 200 500 1k 2k 5k 10k 20k
20 50 100 200 500 1k 2k 5k 10k 20k

Frequency(Hz) Frequency(Hz)

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ESMT AD52090

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ESMT AD52090

Functional Block Diagram

PVCCL
BSPL
LINP Power OUTPL
Gain Control PLIMIT PWM
Modulator Stage
LINN Amplifier Logic OUTNL
N/N
BSNL
PGND

DC Short-Circuit
∆-wave Protection
Detect

PVCCR
BSPR
RINP Power OUTPR
Gain Control PWM Stage
PLIMIT Modulator
RINN Amplifier Logic OUTNR
N/N
BSNR
PGND
GAIN0
Gain Select
GAIN1
Thermal
PLIMIT
PLIMIT Detect
Reference Bias
SD Control Logic And
Reference Under-Voltage
AGND Protection
Regulator

PVCC GVDD

Short Circuit Error FAULT

DC Detect Error Logic FAULT

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

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ESMT AD52090
Operation Descriptions

 Gain settings
The gain of the AD52090 is set by two input pins, GAIN0 and GAIN1. By varying input
resistance in AD52090, the various volume gains are achieved. The respective volume
gain and input resistance are listed in Table 1. However, there is 20% variation in input
resistance from production variation.

Table 1. Volume gain and input impedance

GAIN1 GAIN0 Volume Gain (dB) Input Resistance, Rin (k)
0 0 18.5 70.5
0 1 26 30
1 0 32 15
1 1 36 9

 Shutdown ( SD ) control
Pulling SD pin low will let AD52090 operate in low-current state for power conservation.
The AD52090 outputs will enter mute once SD pin is pulled low, and regulator will also
disable to save power. If let SD pin floating, the chip will enter shutdown mode because
of the internal pull low resistor. For the best power-off performance, place the chip in the
shutdown mode in advance of removing the power supply.

 DC detection
AD52090 has dc detection circuit to protect the speakers from DC current which might
be occurred as input capacitor defect or inputs short on printed circuit board. The
detection circuit detects first volume amplifier stage output, when both differential
outputs’ voltage become higher than a determined voltage or lower than a determined
voltage for more than 420ms, the dc detect error will occur and report to FAULT pin. At
the same time, loudspeaker drivers of right/left channel will disable and enter Hi-Z. This
fault can not be cleared by cycling SD , it is necessary to cycle the PVCC supply.

The minimum differential input voltages required to trigger the DC detect function are
shown in table2. The input voltage must keep above the voltage listed in the table for
more than 420msec to trigger the DC detect fault. The equivalent class-D output duty of
the DC detect threshold is listed in table3.

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ESMT AD52090

Table 2. DC Detect Threshold

AV (dB) Vin (mV, differential)
18.5 286
26 136
32 64
36 44

Table 3. Output DC Detect Duty (for Either Channel)

PVCC (V) Output Duty Exceeds
8 40
12 40
16 40

 Thermal protection
If the internal junction temperature is higher than 170oC, the outputs of loudspeaker
drivers will be disabled and at low state. The temperature for AD52090returning to
normal operation is about 135oC. The variation of protected temperature is about 10%.
Thermal protection faults are NOT reported on the FAULT pin.

 Short-circuit protection
To protect loudspeaker drivers from over-current damage, AD52090 has built-in
short-circuit protection circuit. When the wires connected to loudspeakers are shorted to
each other or shorted to VSS or to PVCC, overload detectors may activate. Once one of
right and left channel overload detectors are active, the amplifier outputs will enter a
Hi-Z state and the protection latch is engaged. The short protection fault is reported on
FAULT pin as a low state. The latch can be cleared by reset SD or power supply
cycling.

The short circuit protection latch can have auto-recovery function by connect the FAULT
pin directly to SD pin. The latch state will be released after 420msec, and the short
protection latch will re-cycle if output overload is detected again.

 Under-voltage detection
When the GVDD voltage is lower than 2.8V or the AVCC voltage is lower than 4V,
loudspeaker drivers of right/left channel will be disabled and kept at low state. Otherwise,
AD52090 return to normal operation.

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ESMT AD52090
 Over-voltage protection
When the AVCC voltage is higher than 29.5V, loudspeaker will be disabled kept at low
state. The protection status will be released as AVCC lower than 29V.

 Power limit function

 The voltage at PLIMIT pin can used to limit the power of first gain control amplifier
output. Add a resistor divider from GVDD to ground to set the voltage V PLIMIT at the
PLIMIT pin. The voltage VPLIMIT sets a limit on the output peak-to-peak voltage.
PLIMIT is adjustable from 1.33V~2.5V.

For normal BTL operation (Stereo) and PBTL (Mono) operation:

2
 2.5V  PLIMIT 
 2.1V  0.81 P  2  PVDD  1.22  0.0092  PVDD
Po @1%   LIMIT 
2  RL

Po @10%  ( Po @1%)  1.21  0.021 PVDD

Connect PLIMIT pin to ground or GVDD to disable power limit function. The output
variation during power limit feature enable may have +-20% variation due to process
window.

Table 4.1 PLIMIT Typical OperationⅠ

VPLIMIT (V) @
Test Conditions Output PO (W)
THD+N=10%
5 1.973
8 1.851
PVCC=24V 10 1.785
RL=8 12 1.727
15 1.652
20 1.545

Table 4.2 PLIMIT Typical OperationⅡ

VPLIMIT (V) @
Test Conditions Output PO (W)
THD+N=10%
3 1.744
PVCC=12V 5 1.564
RL=8 8 1.371
9 1.319

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ESMT AD52090
Table 4.3 PLIMIT Typical Operation Ⅲ
VPLIMIT (V) @
Test Conditions Output PO (W)
THD+N=10%
10 1.973
PVCC=24V 15 1.869
RL=4 20 1.785
30 1.651

Table 4.4 PLIMIT Typical Operation Ⅳ

VPLIMIT (V) @
Test Conditions Output PO (W)
THD+N=10%
5 1.8
PVCC=12V 8 1.646
RL=4 10 1.564
15 1.4

 PBTL (Mono) function

AD52090 provides the application of parallel BTL operation with two outputs of each
channel connected directly. If the PBTL pin is tied high, the positive and negative
outputs of left and right channel are synchronized and in phase. Apply the input signal to
the RIGHT channel input in PBTL mode and let the LEFT channel input grounded, and
place the speaker between the LEFT and RIGHT outputs. The output swing is doubled
of that in normal mode. See the application circuit example for PBTL (Mono) mode
operation. For normal BTL (Stereo) operation, connect the PBTL pin to ground.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 16/26
ESMT AD52090

Power On/Off sequence
Hereunder is AD52090’s power on/off sequence.

P V C C L /R
t1 t5

AVCC
t2 t4

PBTL
t3

SD

A u d io

Symbol Min. (ms) Typ. (ms) Max. (ms)

t1 0 - -
t2 0.1 - -
0.2
t3 - -
(Don’t care for PBTL=0 in stereo operating)
t4 0.1 - -
t5 0 - -

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 17/26
ESMT AD52090
Application information

 Input capacitors (Cin)

The performance at low frequency (bass) is affected by the corner frequency (fc) of the
high-pass filter composed of input resistor (Rin) and input capacitor (Cin), determined in
equation (2). Typically, a 0.1F or 1F ceramic capacitor is suggested for Cin. The
resistance of input resistors is different at different gain setting. The respective gain and
input resistance are listed in Table 1 (shown at GAIN SETTING). However, there is 20%
variation in input resistance from production variation.

-3 dB
fc 
1
Hz  2
2π R in Cin

fC

 Ferrite Bead selection

If the traces from theAD52090 to speaker are short, the ferrite bead filters can reduce
the high frequency emissions to meet FCC requirements. A ferrite bead that has very
low impedance at low frequency and high impedance at high frequency (above 1MHz)
is recommended. The impedance of the ferrite bead can be used along with a small
capacitor with a value around 1000pF to reduce the frequency spectrum of the signal to
an acceptable level.

FB
OUTP
1000pF

1000pF
FB
OUTN

Figure 2. Typical Ferrite Bead Filter

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 18/26
ESMT AD52090

 Output LC Filter
If the traces from theAD52090 to speaker are not short, it is recommended to add the
output LC filter to eliminate the high frequency emissions. Figure 3 shows the typical
output filter for 8 speaker with a cut-off frequency of 61 kHz and Figure 4 shows the
typical output filter for 4 speaker with a cut-off frequency of 34 kHz.

10uH
OUTP
0.68uF
8
0.68uF
10uH
OUTN

Figure 3. Typical LC Output Filter for 8 Speaker

10uH
OUTP
2.2 uF
4
2.2 uF
10uH
OUTN

Figure 4. Typical LC Output Filter for 4 Speaker

4.7uH
OUTP

2.2 uF 2

4.7uH
OUTN

Figure 5. Typical LC Output Filter for 2 Speaker

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 19/26
ESMT AD52090

 Power supply decoupling capacitor (Cs)

Because of the power loss on the trace between the device and decoupling capacitor,
the decoupling capacitor should be placed close to PVCC and PGND to reduce any
parasitic resistor or inductor. A low ESR ceramic capacitor, typically 1000pF, is
suggested for high frequency noise rejection. For mid-frequency noise filtering, place a
capacitor typically 0.1F or 1F as close as possible to the device PVCC leads works
best. For low frequency noise filtering, a 100F or greater capacitor (tantalum or
electrolytic type) is suggested.

PVCC Power Supply

1000pF 0.1uF 100uF

Figure 6. Recommended Power Supply Decoupling Capacitors.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 20/26
ESMT AD52090
Application Circuit Example
 Application circuit for BTL (Stereo) mode configuration and Single-Ended Input

1k 1 28
S h u td o w n
C o n tro l SD PVCCL PVCC
2 27
PVCCL 0 .1 u F 1 0 0 u F
FAULT
3 26 (0 .4 7 u F )
1uF
L -c h N o te 3
In p u t L IN P BSPL
1k 4 25 0 .2 2 u F
10uH
1uF
L IN N OUTPL
PVCC
5 24 2 .2 u F +

Speaker
4ohm
G A IN 0 PGND
N o te 4 6 23 2 .2 u F -
100 G A IN 1 OUTNL (0 .4 7 u F ) 10uH
7 22 0 .2 2 u F
AVCC BSNL N o te 3
1uF 0 .1 u F 8 AD52090 21 N o te 3
AGND BSNR
1uF 0 .2 2 u F
9 20 (0 .4 7 u F ) 10uH

1uF
RPL2 GVDD OUTNR
RPL1 10 19 2 .2 u F -

Speaker
4ohm
P L IM PGND
N o te 2 11 18 2 .2 u F +
1uF
R IN N OUTPR (0 .4 7 u F )
1k 10uH
1uF 12 17 0 .2 2 u F
R -c h
In p u t
R IN P BSPR N o te 3
13 16
NC PVCCR PVCC
14 15
PBTL PVCCR 0 .1 u F 1 0 0 u F

Note 2: These resistances must be connected to ground, resistance=1Kohm.

Note 3: These capacitors should be change to 0.47uF, while the PVCC<=5V.

Note 4: The under-voltage threshold for AVCC could be adjusted by RAVCC, the formula will be

followed RAVCC  PVCC  4 k to adjust it.

30

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 21/26
ESMT AD52090
Application Circuit Example
 Application circuit for parallel BTL (Mono) mode configuration and Single-Ended Input

1k 1 28
S h u td o w n
C o n tro l SD PVCCL PVCC
2 27
PVCCL 0 .1 u F 1 0 0 u F
FAULT
3 26
L IN P BSPL
4 25 0 .4 7 u F
L IN N OUTPL
PVCC
5 24
G A IN 0 PGND
N o te 6 6 23 10uH
100 G A IN 1 OUTNL
7 22
AVCC BSNL 2 .2 u F -

Speaker
4ohm
1uF 0 .1 u F 8 AD52090 21
AGND BSNR 2 .2 u F +
1uF 9 20
1uF
RPL2 GVDD OUTNR 10uH
RPL1 10 19
P L IM PGND
N o te 5 1uF 11 18
R IN N OUTPR
1k
1uF 12 17 0 .4 7 u F
R -c h
In p u t
R IN P BSPR
13 16
NC PVCCR PVCC
14 15
PVCC PBTL PVCCR 0 .1 u F 1 0 0 u F

Note 5: These resistances must be connected to ground, resistance=1Kohm.

Note 6: The under-voltage threshold for AVCC could be adjusted by RAVCC, the formula will be followed
PVCC  4
RAVCC  k to adjust it.
30
Note 7: Be noted that input should be applied on R-channel only for Mono application

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 22/26
ESMT AD52090
Package Dimensions
 E-TSSOP 28L(173 mil)

28 15

D2

E2 E E1 DETAIL A
PIN#1
MARK 1 14
c
TOP VIEW
D

A
A1
1 14
b e
L
SIDE VIEW

Dimension in mm Exposed pad

Symbol
Min Max Dimension in mm
A -- 1.20 Min Max
A1 0.05 0.15 D2 5.00 6.40
b 0.19 0.30 E2 2.50 2.90
c 0.09 0.20
D 9.60 9.80
E 4.30 4.50
E1 6.30 6.50
e 0.65 BSC
L 0.45 0.75

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021

Revision:1.5 23/26
ESMT AD52090

Revision History

Revision Date Description

0.1 2018.09.13 Initial version.
Remove “Preliminary” and reversion to 1.0 ver. &Modify gain
1.0 2019.01.07 max/min spec& modify Package Dimensions& modify plimit
table 4.1~4.4.
1.1 2019.03.15 Update typical characteristics.

Update operation descriptions for under-voltage detection.

1.2 2020.01.02
Update application circuit.

Updateabsolutemaximumratings.
1.3 2020.08.17
Update application circuit example.

1.4 2020.12.07 Update application circuit example.

1) Added IAVCC spec. into.

2) Modified OVP description.
1.5 2021.10.13
4) Added power on/off sequence into.
3) Updated RAVCC formula in application circuit.

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Revision:1.5 24/26
ESMT AD52090

Important Notice
All rights reserved.

No part of this document may be reproduced or duplicated in any form or by

any means without the prior permission of ESMT.

The contents contained in this document are believed to be accurate at the

time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.

The information contained herein is presented only as a guide or examples for

the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express, implied or
otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.

Any semiconductor devices may have inherently a certain rate of failure. To

minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should
be provided by the customer when making application designs.

ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.

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Revision:1.5 25/26