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N O - 1 D E S T I N AT I O N F O R V L S I & E M B E D D E D S Y S T E M S T R A I N I N G

Advanced ASIC
Verification Course
Offline | Blended | Online

5000+ 250+
Global Alumni Hiring Partners

Hands-on Training Placement Assistance 1:1 Mentoring 24/7 Lab Access & Support
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MAVEN SILICON Maven Silicon is a leading provider of VLSI & Embedded training for students and profession-
als. We offer a range of high-quality VLSI & Embedded training programs and internships,
taught by experienced industry professionals, aimed at helping engineers to upskill and
advance their careers in the fast-growing Semiconductor Industry. From digital design and
verification to physical design and design for testing, Maven Silicon covers a wide variety of
topics along with labs and projects through Industry standard EDA tools. Our
state-of-the-art training facilities, coupled with innovative training methods, provide
students with hands-on experience and a strong foundation in the latest VLSI & Embedded-
technologies. Our curriculum is designed to meet the demands of the industry and is
constantly updated to keep pace with the latest advancements. In addition, Maven Silicon
offers flexible scheduling options and customized training programs to accommodate
student's busy schedules.

With a commitment to excellence and a passion for empowering students and professionals,
Maven Silicon is dedicated to providing the highest quality hands-on training to help
engineers reach their full potential in the Semiconductor industry.

My vision is to create an excellent learning ecosystem of

superior technical expertise, hands-on training experience,
and industry-oriented courses with innovative learning
processes.

For more than 15 years, Maven Silicon has been a benchmark

for the VLSI training ecosystem in India, offering high-quality
VLSI training courses for VLSI aspirants, professionals, and
organizations across the globe.

Sivakumar P R
Founder and CEO

Our CEO, Sivakumar P R, has 25+ years of experience in the engineering and semiconductor industries. He has worked as a Verification
Consultant in the top EDA companies like Synopsys, Cadence, and Mentor Graphics. During this tenure, he worked very closely with
various ASIC and FPGA design houses and helped them to use the EDA solutions effectively for the successful tape-outs of multi-million
gate designs.

To know more about our CEO, visit https://www.linkedin.com/in/sivapr/

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Five reasons to muse with MAVEN SILICON

Dynamic VLSI courses designed and delivered by Industry experts
01
Maven Silicon is the Best VLSI training center which provides high-class industry standard VLSI training. The courses have been
designed by industry experts, based on the job opportunities and career growth in the semiconductor industry and we keep
updating our VLSI Curriculum as per the latest industry trends.

Superior Training Methodology and Infrastructure

02
Our training methodology is unique. It helps our students to learn even complex technologies in a short span of time and make
them experts. 70% of the course time is dedicated to the labs, mini projects, and the final project. Our training courses help you
to acquire the technical skills which are highly required to get a job in the semiconductor industry.

100% Placement Support

03
Maven Silicon provides 100% placement assistance to the eligible trainees of the job-oriented programs and keeps supporting
them until 12 months after course completion. Our primary objective is to help electronics engineers successfully build a career
in the semiconductor/VLSI Industries. We work closely with various VLSI products & services companies and identify the right
opportunities. Most of our students have been successfully placed in reknowned semiconductor companies.

Excellent Support
04
Maven Silicon offers 1:1 mentoring and 24/7 online support through the MASS platform. The trainees have 24/7 lab access to
enhance technical skills and participate in group discussions to gain new knowledge. Business communication sessions and
mock interviews provide the necessary skills to succeed in a professional setting.

Free Internship
05
This program offers hands on experience with various verification methodologies such as Constraint Random Coverage Driven
Verification (CRCDV), Assertion Based Verification (ABV) using the languages like SystemVerilog and Methodologies like UVM on
the project life cycle from Verification planning to Verification signoff, making the trainees industry ready.

EDA Partner

Siemens is a leader in Electronic Design Automation. Synopsys is at the forefront of Smart Everything
Its innovative products and solutions help engineers with the world's most advanced tools for silicon
conquer design challenges in the seemingly daunting chip design, verification, IP integration, and
world of board and chip design. application.
https://eda.sw.siemens.com/en-US/ https://www.synopsys.com/

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Advanced VLSI Physical Design

COURSE CURRICULUM

& Verification
Advanced ASIC
Verification Course
Course
17 Modules OS - Linux Ubuntu EDA Tools - Synopsys,Siemens, Xilinx, Aldec

Advanced Digital CodeIV

MODULE Coverage SystemVerilog HVL

Module I Module V Module IX

Combinational Circuits - Design Statement coverage Introduction to SystemVerilog

and Analysis Branch Coverage New Data types
Shift Registers and Counters Expression Coverage Tasks and Functions
Interfaces
Sequential Circuits - Design and Path Coverage
Analysis Clocking blocks
Toggle Coverage
Finite State Machine FSM - State, Transition Coverage Object Oriented Programming and
Randomization
OOP Basics
Introduction to Linux Design Automation using Scripts - Perl Classes - Objects and handles
Polymorphism and Inheritance
Module II Module VI
Randomization
Components of the UNIX system Introduction to Perl Constraints
Directory Structure Functions and Statements
Utilities and Commands Numbers, Strings, and Quotes Threads and Virtual Interfaces

Vi Editor Comments and Loops Fork Join

Regular Expressions Fork Join_any
Fork Join_none
File Operations
Event controls
Static Timing Analysis
MODULE III Mailboxes and semaphores
Module III Virtual Interfaces
Introduction to STA ASIC Verification Methodologies Transactors
Comparison with DTA Module VII Building verification environment
Timing Path and Constraints Directed Vs Random Testcases

Different types of clocks Functional verification process Callbacks

Clock domain and Variations Monitors and reference Facade Class
Clock Distribution Networks models
Building Reusable Transactors
How to fix timing failure Stimulus Generation Inserting Callbacks
Methods to improve timing Verification Planning and manage- Registering Callbacks
ment
Bus functional model Direct Programming Interface
Coverage Driven Verification
Advanced Verilog for verification Functional Coverage
Coverage models
Moduel IV
Business communication Coverpoints and bins
Tasks and Functions Cross coverage
Race Conditions Module VIII
Regression testing
File I/O operation Transition from College to Corporate
TB Constructs Interpersonal skills and
Presentation Skills Interfaces and Protocols
Self checking Testbenches
Delays - Regular, Intra Assignment, Email Etiquette
Module X
and Inertial Delays Resume writing
Lectures by Industry Experts
Mockup Interviews Technical/HR
Interview Skills: Group Discussion
and HR Round Preparation

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COURSE CURRICULUM

Advanced ASIC
Verification Course
17 Modules OS - Linux Ubuntu EDA Tools - Synopsys,Siemens, Xilinx, Aldec

Advanced SystemVerilog Verification Planning and Management RISC V Processor

Module XI Module XIV Module XVII

Environment Configuration Verification Plan RISC-V Instruction Set Architecture
Reference Models and Predictor Logics TB Architecture RISC-V processor overview
Using Legacy BFMs Coverage Model RISC-V ISA Overview
Scenario Generation Tracking the simulation process RV32I – R and I Type Instruction
Testcases - Random, Directed, and Building regression test suite RV32I – S and B Type Instructions
corner case Test suite optimization RV32I – J and U Type Instructions
Coding styles for VIP RV32I – Assembly Programs

RISC-V RV32I RTL Architecture Design

Assertion Based Verification - SVA Verification Mini Project RISC-V Execution Stages and Flow
Module XII Module XV RISC-V Register File and RV32I
Instructions Format
Introduction to ABV Verification and RTL sign-off
RV32I – R and I Type ALU Datapath
Immediate Assertions Project specification analysis
RV32I – S Type ALU Datapath -
Simple Assertions Defining verification plan Load and Store
Sequences Creating Testbench architecture RV32I – B and U Type ALU Datapath
Sequence Composition Implementing the transactors - Genera- RV32I – J Type ALU Datapath –
Advanced SVA Features tor, Driver, Receiver, and Scoreboard JAL and JALR
Assertion Coverage Defining Transaction
MODULE III
Implementing the coverage model RISC-V RV32I 5 Stage Pipelined RTL Design

Building the top-level verification CPU Performance and RISC-V 5 Stage

environment Pipeline Overview
UVM - Universal Verification Methodology Building regression test suite RISC-V 5 Stage Pipeline – Data
Coverage Analysis and Coverage Closure Hazards and Design Approach
Module XIII
RISC-V 5 Stage Pipeline – Control
Introduction to UVM Methodology Hazards and Design Approach
Overview of Project
UVM TB Architecture Industry Standard Project
Stimulus Modeling Module XVI Design for Testability - DFT
Creating UVCs and Design specification analysis ELECTIVE MODULE
Environment
Creating the design architecture Introduction to DFT
UVM Simulation Phases
Partitioning the design Types of Testing
Testcase Classes
RTL coding in Verilog Basic Testing Principles
TLM Overview
RTL functional verification Fault Collapsing
Configuring TB Environment
RTL Synthesis Introduction to Tessent Shell
UVM Sequencers
Building regression test suite Structured Techniques
Connecting DUT- Virtual Interface
Coverage Analysis and Coverage BIST & Boundary Scan
Virtual Sequences and Sequencers Closure DFT Techniques - Ad-hoc
Creating TB Infrastructure Techniques
Connecting multiple UVCs Scan Chain
Building a Scoreboard Test Coverage
Introduction to Register Modeling Fault Change
Building reusable environments Tessent Shells
System Modes & TSDB

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South Taluk, 21/1A, III Floor, MS Plaza,

Gottigere Uttarahalli Hobli,
Bannerghatta Main Rd, Bengaluru,
Karnataka 560076
[email protected]

080 6909 6300 +91 74064 79555

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