AHSANULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY

Department of Electrical & Electronic Engineering

Project Report

Course No : EEE 4228

Course Title : Power Electronics Lab

Project Name : Single phase SPWM full-bridge inverter

Semester (Session) : Spring 22

Submitted by:

Name : Wahidul Alam, Zahir Khan Dipto, Ashikur Rahman, Miraz Ahmed Choyon, Ismat Zarin
ID no : 190105132, 190105133, 190105135, 190105136, 190105137
Group : C2
Lab Group :2
Year :4
Semester :2
Objective: The goal of this project is to design a single phase SPWM full bridge inverter. The term
SPWM refers to Sinusoidal Pulse Width Modulation. It is a technique where the duty cycle of the
PWM signal is changed with time to achieve a sinusoidal equivalent output. Unlike other type of
inverters this inverter does not require large filters. Rather, a small filter capable of attenuating the
switching frequency can work quite well to generate a sinusoidal/AC output. The switching
operation is done using four power MOSFETS connected in full-bridge/H-bridge manner. For
generating the SPWM signal Arduino NANO is used as an MCU.

Equipment:

• MCU - Arduino NANO x1

• Power MOSFET - IRF2807 x4
• Driver - L293D x1
• 5V Voltage Regulator - 7805 x1
• Filter Capacitor - 10µF x1
• Filter Inductor - 1mH x\1
• Diode - 1n5408 3A x4
• Step-up Transformer - 12V/220V 1A x1
• Batteries - 18650 Li-ion 3.7V 5000mAh x4
Circuit Diagram
:

Fig. 1. Final Circuit Diagram

Alternative Circuit Diagram:

Operating Principle: The operating principle of the designed inverter can be divided into few
parts.
Powering The Circuit: For delivering power to the driving circuit and the MCU a 7805 IC is
used. It is a 5V constant output voltage regulator. On the design 7812 IC is also used to maintain
a constant 12V output from the batteries. But, in practical circuit it has not been used as the output
current rating of 7812 is only 1A.

SPWM Generation: Digital pin 9 and 10 of Arduino NANO is used for SPWM generation.
Separate PWM signals with varying duty cycle is used to form the SPWM. Timer 1 of Arduino
NANO is utilized for generating these waves on pin 9 and 10. The value of TCCR1A and TCCR1B
register of the Atmega328p (MCU of Arduino NANO board) is set in such a way, that the ‘fast
PWM’ mode is activated for the timer 1 and no pre-scaler is set. In fast PWM mode the counter
stops counting at the value of ICR1 register and starts counting from the bottom. The value of this
register is set to 1600. In fast PWM mode the PWM frequency is defined as,

𝑓𝑐𝑙𝑘
𝑓𝑝𝑤𝑚 =
𝑁 × (1 + 𝑇𝑂𝑃)

Here, N refers to the pre-scaler value and TOP refers to the value of ICR1 register. fclk is the main
clock frequency of Atmega328p which is 16MHz. Putting the values in the equation we get a
frequency of 10kHz. For achieving the 20ms period of our desired AC signal 200 duty cycle values
are calculated for each half. The values are stored on two lookup tables. The changing duty cycle
is achieved by utilizing the timer overflow interrupt feature. Whenever the timer reaches TOP, it
overflows, and a flag is pulled high which triggers an interruption. TIMSK1 register of
Atmega328p is modified to enable the overflow interrupt feature. Inside the interrupt service
routine, the next value of duty cycle is then set to the OCR1A and OCR1B register. To control the
200 points, cycle a variable is used which is set to zero whenever its value reaches 200. The code
is provided below,

int pwm_data_M1M3[] = { 50, 100, 151, 201, 250, 300, 349, 398, 446, 494, 542, 589, 635,
681, 726, 771, 814, 857, 899, 940, 981, 1020, 1058, 1095, 1131, 1166, 1200, 1233, 1264,
1294, 1323, 1351, 1377, 1402, 1426, 1448, 1468, 1488, 1505, 1522, 1536, 1550, 1561, 1572,
1580, 1587, 1593, 1597, 1599, 1600, 1599, 1597, 1593, 1587, 1580, 1572, 1561, 1550, 1536,
1522, 1505, 1488, 1468, 1448, 1426, 1402, 1377, 1351, 1323, 1294, 1264, 1233, 1200, 1166,
1131, 1095, 1058, 1020, 981, 940, 899, 857, 814, 771, 726, 681, 635, 589, 542, 494, 446,
398, 349, 300, 250, 201, 151, 100, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0 };

int pwm_data_M2M4[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 50, 100, 151, 201, 250, 300, 349, 398, 446, 494, 542, 589, 635, 681, 726, 771, 814, 857,
899, 940, 981, 1020, 1058, 1095, 1131, 1166, 1200, 1233, 1264, 1294, 1323, 1351, 1377,
1402, 1426, 1448, 1468, 1488, 1505, 1522, 1536, 1550, 1561, 1572, 1580, 1587, 1593, 1597,
1599, 1600, 1599, 1597, 1593, 1587, 1580, 1572, 1561, 1550, 1536, 1522, 1505, 1488, 1468,
1448, 1426, 1402, 1377, 1351, 1323, 1294, 1264, 1233, 1200, 1166, 1131, 1095, 1058, 1020,
981, 940, 899, 857, 814, 771, 726, 681, 635, 589, 542, 494, 446, 398, 349, 300, 250, 201,
151, 100, 50 };

int i = 0;
 void setup()
{
DDRB |= 6;
cli();
TCCR1A = 162;
TCCR1B = 25;
ICR1 = 1600;
TIMSK1 = 1;
sei();
}

void loop()
{
}

ISR(TIMER1_OVF_vect)
{
if (i >= 200) { i = 0; }
i++;
OCR1A = pwm_data_M1M3[i];
OCR1B = pwm_data_M2M4[i];
}

H-bridge Formation: Full-Bridge Configuration: The full-bridge configuration, also known as

the "H-bridge," uses four switches to create a bridge-like structure. These switches are arranged to
allow the generation of both positive and negative half cycles of the AC output waveform. How it
works: By switching the diagonally opposite switches on and off in a coordinated manner, the
polarity of the output voltage across the load can be controlled. For example, if the upper-left and
lower-right switches are on, and the upper-right and lower-left switches are off, a positive voltage
is applied across the load. By modulating the switching sequence according to SPWM, a sinusoidal
output waveform is synthesized.

Filter: The output waveform of an SPWM full bridge inverter should, in theory, be a pure sinusoid,
however this is not always the case due to dead time, switching losses, and harmonics, which can
cause distortion and contain harmonics of the fundamental frequency. A low-pass filter is applied
after the inverter to diminish the higher order harmonics while allowing the fundamental frequency
component of the output waveform to pass in simulated circuit. But we haven’t used the filter as
it diminishes the output near to invisible. However, the use of SPWM inverter techniques reduces
the harmonic content in the output waveform, which in turn reduces the need for a large filter to
smooth the waveform. When using an SPWM inverter, the output waveform already has a quasi-
sinusoidal shape, which means that there are fewer high-frequency harmonics present in the output
waveform. As a result, a smaller filter is usually sufficient to smooth the output waveform and
reduce the harmonic content. In our case, we have set the cut-off frequency of an LC filter to 1.591
kHz. LC filter is chosen as it has minimized division of voltage across the filter components.
Simulation Results:

Fig: Proteus CKT

Fig: Oscilloscope Output [Simulated]

Oscilloscope Output:

Fig. 4. SPWM gate pulse

Image of Final Setup:

Fig. 5. Final Setup

Harmonics Performance Parameter:
Pulse width modulation results in numerous harmonics that necessitate consideration during
inverter design. Three aspects are of significance:
1. Harmonics produced by the inverter legs.
2. Harmonics present in the current of the filter circuit.
3. Harmonics exist in the filtered output voltage.
All harmonics can be characterized using typical mathematical formulations based on key circuit
parameters and PWM control data, which encompass:
- DC input voltage: U0
- Inverter leg switching frequency: fs
- Transistor bridge pulse frequency: fb
- Fundamental frequency: f
- Modulation factor: Θm4
- Parameters of the choke and filter capacitor: L, C
- The resonance frequency of L and C.

The effects of harmonic distortion induced by PWM in single-phase inverters within UPS systems
have been examined in both the frequency and time domains. A comprehensive general expression
describes all harmonics and can be evaluated through numerical methods. Peak-to-peak and RMS
values can be determined using straightforward analytical equations. These derived formulas are
particularly valuable for inverter design, as well as for analyzing and comparing existing inverters
within UPS systems.

[Ref: https://ieeexplore.ieee.org/document/483469]

Discussion:
Single-phase SPWM is a modulation technique widely used in power electronics to control the
output voltage of inverters and other devices. It's especially popular in applications where high-
quality sinusoidal waveforms are required, such as in motor drives, uninterruptible power supplies
(UPS), and renewable energy systems. The basic idea behind SPWM is to generate a series of
pulses whose widths are modulated in such a way that they mimic the shape of a sine wave. By
varying the pulse width, the average value of the output voltage can be controlled, effectively
generating a variable-frequency AC signal. The SPWM process compares a reference sine wave
with a high-frequency triangular waveform (carrier wave). The comparison generates a pulse width
that varies based on the instantaneous value of the sine wave. When the sine wave value is greater
than the carrier wave, a high pulse is generated; when the sine wave value is less, a low pulse is
generated.