Bunny Workflow and Operation Manual

——BunnyV1.0

Suzhou SILINTECH Co., Ltd.

Technical Support: [email protected]
W ebs i t e: www.silintech.com
Table of Contents

Chapter I Bunny System Overview and Installation ..................................................................... 5

1.1 Bunny System Overview ................................................................................................... 5
1.1.1 System Requirements ......................................................................................................... 5
1.1.2 Installation Portfolio for Optimal Performance of Software Operation ............................. 6
1.2 System Installation Instructions ............................................................................................ 6
1.2.1 Installation File .................................................................................................................. 6
1.2.2 Installation of Service Program.......................................................................................... 7
1.2.3 Client Installation ............................................................................................................... 9
Chapter II Create Cell and Divide Tasks .......................................................................................... 11
2.1 Flowchart ........................................................................................................................... 11
2.2 Create a New Library .......................................................................................................... 11
2.3 Attach Library Image .......................................................................................................... 13
2.4 Create Main Macro Cell ...................................................................................................... 17
2.5 Divide Functional Modules (Macro Cells).......................................................................... 20
2.6 Divide Tasks based on Macro Cell ..................................................................................... 23
Chapter III Library Parameter Setting............................................................................................... 25
3.1 Image Layer Mapping ......................................................................................................... 25
3.2 Wire Width Setting ............................................................................................................ 27
3.3 Via Dimension Setting ...................................................................................................... 29
3.4 Analog Device Setting ........................................................................................................ 30
Chapter IV Workflow for Extracting Netlist of Analog Circuit .................................................. 33
4.1 Open Cell ............................................................................................................................ 33
4.2 Library Parameter Setting ................................................................................................... 33
4.3 Drawing WL Mark .............................................................................................................. 33
4.4 Extract Devices ................................................................................................................... 38
4.5 Connection .......................................................................................................................... 41
4.6 Electric Rule Check (ERC ) ............................................................................................... 42
4.7 Schematic View of Export .................................................................................................. 47
Chapter V Workflow for Extracting Netlist of Digital Circuit ........................................................ 49
5.1 Open Cell ........................................................................................................................... 49
5.2 Library Parameter Setting ................................................................................................... 49
5.3 Divide Tasks ...................................................................................................................... 49
5.3.1 Instance Placement ........................................................................................................... 49
5.3.2 Wire Identification ........................................................................................................... 49
5.3.3 Via Identification ............................................................................................................. 50
5.4 Integrate Tasks and Generate Netlist .................................................................................. 50
5.5 Electric Rule Check (ERC ) .............................................................................................. 53
5.6 Schematic View of Export .................................................................................................. 54
Chapter VI Enumeration Screen ....................................................................................................... 56
Chapter VII Cell Identification ......................................................................................................... 58
7.1 Create Cell Template .......................................................................................................... 58
7.2 Edit Cell Template .............................................................................................................. 62
7.3 ERC Check for Cell Template ............................................................................................ 68
 7.4 Generate Schematic view of Basic Cell .............................................................................. 70
7.5 Auto Search Cell Instance ................................................................................................... 74
7.6 Perspective Inspection of Cell to Confirm Instance ............................................................ 78
Chapter VIII Wire Identification ....................................................................................................... 80
8.1 Auto Search Wires .............................................................................................................. 80
Chapter IX Via Identification ........................................................................................................ 84
9.1 Auto Search Via .................................................................................................................. 84
Chapter X Connect ............................................................................................................................ 87
10.1 Connect by Pressing P...................................................................................................... 87
10.2 Wire Tracking Function .................................................................................................... 87
Chapter XI Workspace Data Export ................................................................................................. 89
11.1 Verilog ............................................................................................................................. 90
11.2 Edif200 ............................................................................................................................ 91
11.3 CDL ................................................................................................................................. 92
11.4 Spice ................................................................................................................................ 93
Chapter XII Cross Reference ............................................................................................................ 94
12.1 Cross Reference Instances................................................................................................. 95
12.2 Cross Reference Signals .................................................................................................... 97
12.3 Cross Reference of Instances and Signals ......................................................................... 99
Chapter XIII Net Track Navigation .................................................................................................100
13.1 Net Track Relationship of Probe .....................................................................................100
13.2 Shortest Route Inspection ...............................................................................................102
13.3 Pin To Pin Line Shown in Jump Wire............................................................................104
Chapter XIV Circuit Hierarchical Arrangement ..............................................................................105
14.1 Export Schematic view, and Create Sub Cell...................................................................106
14.1.1 Generate Flattened Netlist .............................................................................................107
14.1.2 Create Subschematic for Sub Cell.................................................................................108
14.2 Preliminary Hierarchical Arrangement of Circuits ..........................................................112
14.2.1 Arrange Modules...........................................................................................................112
14.2.2 Auto Search Macrocell ..................................................................................................119
14.2.3 Error Correction ............................................................................................................124
14.3 Layers Integration ............................................................................................................129
Chapter XV Circuit Analysis ...........................................................................................................130
15.1 Net Track Navigation .......................................................................................................130
15.2 Cross Reference ...............................................................................................................130
Chapter XVI Default Shortcut Setting .............................................................................................131
Chapter XVII FAQ..........................................................................................................................137
17.1 Conversion between Cadence514 and Cadence615 .........................................................137
17.2 Modify the coloring scheme of the library ......................................................................142
17.3Attach image layer and shape layer...................................................................................146
17.4 Change shortcut for switching image layer ......................................................................147
17.5 Deploy the Image Library to Different Servers or Different Partitions of the Same
Computer..................................................................................................................................147
17.6 How to modify the width of the entire wire after it is highlighted by double-clicking?
.............................................................................................................................................…150
17.7 How to extend and slight adjust the local parts when the path line is long, and it contains
some line segments , which indicates some deviation? ..................................................152
17.8 When selecting cells, multiple devices in parallel connection are selected as one. When it
needs to be separated, how to separate the path and cell and remove a single path only? .......152
17.9 It can’t distinguish the target cell when the distance of pins between the neighboring cells
is close. Can the pin be highlighted when the cell is highlighted? ...........................................154
17.10 Add the required parameter when the default device parameters are insufficient .........154
17.11 When the circuit diagram only shows M=, or L=,W= ..................................................157
17.12 How to modify pin size of the cell when it is not intuitive enough when connecting with
pin? ...........................................................................................................................................157
17.13 Modify Via size ..............................................................................................................159
17.14 When connecting with pin, the default layer of B end of MOS tube is DIFF, which is
POLY for G end. Can they be modified? .................................................................................160
17.15 How to add new device ..................................................................................................162
17.16 What if it is a three-terminal resistor? ............................................................................163
17.17 What if it fails to connect with one end of the device? ..................................................163
17.18 What if wrong device type is extracted after labeling some devices? ............................164
17.19 What if the device pins are missing after labeling some devices? .................................165
17.20 What if the name of cell created on Windows platform contains English letters in upper
case and %？............................................................................................................................165
17.21 Automatic extraction of W, L, M values of analog devices ...........................................165
Chapter I Bunny System Overview and
Installation
1.1 Bunny System Overview

Bunny 系统
System

Server （DesignServer） Client (Bunny)

（DesignServer）

Bunny system is composed of two parts: Design Server and Bunny Client. Before using Bunny software, it is
required to download and install server and client successfully. (Note: When both the server and the client are
installed on the same PC, it should download the correct version of server and client based on the operating system
of the PC.)

1.1.1 System Requirements

Currently the Server supports the following platforms:

1. Windows x64 system (XP/Win7/Win10)

2. Unix/Linux x64 system (RedHat6/Centos6/Ubuntu14)

The Client supports Windows x86, x64, Unix/Linux x86, x64 system.
1.1.2 Installation Portfolio for Optimal Performance of Software Operation

Design Server

Client 1 Client 2 Client 3 …… N N+1

To relieve load of capacity on the host, and improve the operation performance and the efficiency
of the software, we recommend installing a server for multiple clients. Under such architecture, the
client version is not limited by the PC platform where the server is installed. At the meantime, it
supports multiple clients accessing multiple servers (The IP address of the target server is
required). It is recommended to install Redhat Enterprise Linux 6.x 64-bit on the server.

1.2 System Installation Instructions

1.2.1 Installation File

1. designserver_xxx.zip: Compressed file of server installation program.

2. bunny_xxx.zip: Compressed file of Bunny client, which will be decompressed as Bunny
software.
Path:

a. bin path: Software installation, startup service and executable

file

b. setup path: Script of register or uninstall service

 setup.bat: Register service

 uninstall.bat: Uninstall service
 c. template path: Default PDK library of integrated circuit

 analoglib:
 basic:
 defTechLib:
 sample:
 US_8ths:
 bunnyLib:
d. etc path: including software log file, license file, and SN
e. images path: library image bank

f. projetcs path: project database

1.2.2 Installation of Service Program

1. Decompress and install server

Decompress designserver_xxx.zip file, locate setup file and double-click on it to install.

2. Register service and application of license file.

After the installation is completed, it will show the register information as shown below:
Please send us the sn.txt file under the path of pc-code:XXXX-XXXX-XXXX-XXXX or
/designserver/etc/, to obtain the license file.

Put your license.txt file in the folder /designserver/etc under the installation path.

3. Server startup

3.1 Windows system

Locate startServer in designserver/bin, and double-click on it to start up server.

3.2 Linux system

Open terminal with root user and run service designserver start to start up server.
/designserver/bin/…/designserver requires executable privilege.
Note: When downloading designserver_xxx.zip file, don’t rename it randomly. If you need to
create another directory, don’t name the folder with Chinese. Otherwise, the server startup will fail.
Under such circumstance, the user needs to return the setup path to complete the register service
again. Then the server may be started.
 Chinese name is not
supported

1.2.3 Client Installation

Please follow the steps below to install Bunny client:

1. Download and decompress the target bunny_xxx.zip file onto the hard disk of PC. Right-click on it
and select Send to Desktop (Create Shortcut).
2. Run the shortcut bunny on the desktop, as shown below:

Enter the IP address of the server, and click OK to connect with the server. Enter localhost if the
client and the server are installed on the same PC.
Chapter II Create Cell and Divide Tasks
2.1 Flowchart

2.2 Create a New Library

Click on bunny shortcut on the desktop to en ter th e Lib ra r y Man ag er scree n .

C lick o n file-New-New Library to create a new library. You may also click the icon under
File to enter the library creation screen directly.
 a. Enter library name,
such as : P20170502
b.Path(The default
setting can’t be modified)
c. Name of library
image to be attached

d.Edit an ASCII technology file

e.Refer to the existing technology libraries

f. Don’t need a techfile(default setting)

Before the layout drawing, please refer to the minimum width of the existing technology to set the
software grids uniformly. Generally, it is 0.01 by default.

2.3 Attach Library Image

After creating a New Library, it needs to decompress the library image and place it in Image
folder under the designsever path , which can be read then.

You may encounter two situations when attaching library in Bunny Library Manager:
(1) The library image is placed under designserver/Image before a New Library is created.
In this case, when you create a New Library, click the drop-down menu of Name
under Image Library, it will list the image name. Select the target name and press
OK. In this example, the name of new library is P20170504, and the image with
the name of B170202_018 is selected as the Image Library. Lastly, press OK.
Go back to the library list and locate the library P20170504 . Right-click on New CellView to
create macro cell.
In the dialog of New CellView, name it as Cell:M20170504. Select Type-Layout, and click OK.
Double-click the layout under the library to enter the workspace, then you will see the library image.
(2) If the image is not placed under the path designserver/Image before the New Library is created,
select Tools-Attach Image. In the pop-up dialog of Attach Image, select the target library. Then
select the target file under the drop-down menu of inverted triangular.
【Note】 Naming rule for New Library and Macro Cell
(1)In Windows platform, the English letters in lower case are recommended.
(2) Don’t mix the English letters in upper case and lower case in the name.
(3) If the name contains English letters and numbers, it must be started with English letter, and it is
recommended: English letters+ numbers+ underline.
Note: It can’t contain any space and dash. Please shift the input method to English, or the name
can’t be identified.

2.4 Create Main Macro Cell

A chip is composed of multiple functional modules and devices. In practice case, the library
manager will assign these functional areas to other IC engineers, which are called cells. In Bunny
Library Manager, we call the workspace of the entire chip as main macro cell, which includes: the
sub macro cells (functional modules) and symbol cells (devices). Generally, we name the main
macro cell as “ BLOCK” or “ TOP ”, and select its view Type as “annotatelayout”. (If you
need to draw formal layout, please select annotatelayout view). Layout view is reserved for
formal layout.
Right-click on a library and select New CellView to create a main macro cell. Each main macro
cell matches a sub cell of the entire data area under the target library.

There are two ways to create main macro units (TOP layer):
 Create cell on TOP layer from menu selection: Right-click on a library and select New CellView.
Enter the Cell name and select View Type.
a. Name of library/project

b. Cell name

c. Cell type

Create cell on TOP layer through Toolbar: Select a library and click on the toolbar icon In
the window of New CellView, create Top and select layout type. Finally click OK and open the cell
directly to enter the workspace.
After the main macro cell is created, you may set the parameters under the library. For more details,
please refer to § Chapter III L i b r a r y P a r a m e t e r S e t t i n g .

2.5 Divide Functional Modules (Macro Cells)

Open the chip background (the library image) to enter the workspace.

Select or to select. You may select target area from Create-Shape-

Rectangle/Polygon.

Use the polygon tool to select the digital circuit module, as shown below.
 Right-click on the polygon framework, and select Make Cell to create a new cell. In the sample
screen below, the new cell is:Top_DG1.

Note for cell naming:

Index relationship exists
between the cell and the main
macro cell (TOP layer). The
naming for any cell is based on
the TOP layer.

After the above steps, press OK directly to finish creation.

Select Edit to open a new window for editing.

Select Edit In Place to edit under the original window.

In the Bunny Library Manager screen, press the Toolbar icon for refreshing, which can be viewed in Cell tab.

Top is the main macro unit of

library P20170512

Top_DG1 is the sub cell

2.6 Divide Tasks based on Macro Cell

It is to divide the macro cells, namely, further dividing the task under macro cell. A task is corresponding to a sub
area in the macro cell, and each macro cell area includes various data operation such as cell instance, line and Via.
The library manager may divide and assign the data in the entire macro cell, so as to assign the tasks in
three forms of instance, line and Via. Namely: The project members may finish the tasks of three
types of instance placement, line identification and Via identification, which can be performed at the
same time generally.

Task
Data
Instance Line Via identification
placement identification

POLY / /
DG_Cell
M1 / /

Via1 / DG_Via1

M2 DG_M2 /
/
Via2 / DG_Via2
Chapter III Library Parameter Setting
Before analog circuit and digital circuit netlist extraction, create a new library, add a main macro
unit (namely top cell: Block/Top), and set the related parameters related to the library (image
layer mapping, width, Via dimension, and analog device) for the convenience of subsequent
work.

(Note: when extracting the netlist of analog circuit, you may set the minimum wire width as the
default value.)

3.1 Image Layer Mapping

Image layer mapping: It is to map the image layers (STAIN, POLY, M1, and M2) with wire net
layer, Pin layer and Via layer.
 Wire net Line Shortcut to switch
Image layer layer Pin layer Via layer width image layer
 Image layer Wire net layer Pin layer Via layer

M2 MET2 drawing MET2 drawing VIA1_C

M1 MET1 drawing MET1 drawing VIA_C

POLY POLY1 drawing POLY1 drawing P1_C

STAIN DIFF drawing DIFF drawing ND_C

3.2 Wire Width Setting

Before the wire width setting, it should measure the width of the tube in the image layer

corresponding to the chip. Press the toolbar icon (or the shortcut K)，to measure the tube
width with the ruler.

After the measurement, select Create-Shape-Geometric Wire option, or click the icon on
toolbar, or press the shortcut P and then F3 to set the width. Finally click Hide.
 Wire width

Four snap modes when drawing wire:

Orthogonal
Diagonal
L90XFirst
L90YFirst
3.3 Via Dimension Setting

Via diameter

• Margin from layer

1/layer 2 to the via
along X axis.
• Margin from layer
1/layer 2 to the via
along Y axis.

• Margin from via to via

along X axis.
• Margin from via to via
along Y axis.
 Width and Height
are the via
Rows Spacing: Via
diameter
margin along X
axis
Rows and Cols are Column Spacing:
the via rows and Via margin along
columns. For Y axis.
example,1X1 refers
to one row and one
column, while 1X2
refers to one row and
two columns.

3.4 Analog Device Setting

If the devices and tubes are of different types when extracting netlist of analog circuit, the Analog
Device Setting option is required to add based on specific demands. Moreover, it should set the
image layer corresponding to G pin and B pin (G pin is corresponding to POLY layer, B pin is
corresponding to DIFF layer, and other pins are corresponding to MET1 layer.)
Device type Name list

MOS3 nmos pmos

MOS4 nmos4 pmos4 ndep ldpc ldns ldps ldnd ldpd esdn esdp

esdnhv esdphv hvns hvps hvnd hvpd

BJT Npn pnp npnc pnpc lnpn lpnp

 RES rp1 rp2 rpp rnp rnw rpw rsh rbs mfuse pfuse rpp_t rnp_t

DIO Pdio ndio

CAP Pip pipdw mom mim plpw

IND ind

Note:
 Power/Ground Names is to set the name of power ground, which is VS and GS by default.
 In Module Names, you may add different names for the same device. Double-click on it to add module
name.
Chapter IV Workflow for Extracting Netlist
of Analog Circuit
4.1 Open Cell

Open a cell or create a new cell. For how to create cell, please refer to §2.2 Create a New Library, §2.4
Create a Main Macro Unit.

4.2 Library Parameter Setting

Please refer to §3.4 Analog Device Setting

4.3 Drawing WL Mark

Default setting is: The width of Path wire is L value, while the length of Path wire is W value.
 L value is the width of path
wire by default.

M Min value is the length of

path wire by default

Poly Mark Layer can’t use the layers corresponding to the items below. (Including: The layers corresponding
to PrBoundary, G,D,S,B and text)

When drawing wire, the engineer sets the distance between D pin and S pin as the wire width, namely,
the L value in default setting. Due to different habits of individuals, there are two situations when
drawing link.
(1) Use the ruler to measure the distance between D pin and S pin , namely L value=wire width;

In the Property column, it shows: Path width is: 2um, length: 0,97um
In this dialog, L=wire
width=2um
(2) Use ruler to measure the distance between G pin and B pin, and set L value as such value.
However, under such circumstances, when extracting devices, namely selecting with the device
icons under Toolbar , it should select Swap option in the dialog of
“Device Type and Param”.
 Select Swap to
exchange W value
and L value
4.4 Extract Devices

1. To jud ge th e tu be d irec tio n, u se th e ru ler (Press the shortcut K to show the

ruler, while press SHIFT+K to hide ruler) to measure the W/L value of Poly tube on the module.
2. Select icon , press the shortcut F3 to access Mark W/L Value dialog. Select “Poly Text” layer
under “Poly Mark Layer” option, and set the L value as the measured width. Click Hide to save setting.

3. Draw wire based on the tube direction.

4. Judge the tube type(MOS4, MOS3, BJT, RES, DIO, CAP, IND)and select the corresponding
device icon for selection. Set the tube type in the pop-up dialog.

5. Mark pin and generate pin. G tube is corresponding to POLY layer, tube D and tube S are corresponding
to M1 or DIFF layer. Tube B is corresponding to DIFF layer.
4.5 Connection

For more details, please refer to § Chapter X Connect

The link only supports Geometry Wire(Pathseg) function, but doesn’t support drawing with polygon or
rectangle. The line drawn with Geometry Wire/Pathseg can’t be linked with polygon or rectangle. It
is recommended to set the wire width as the value that matches the image. To draw wire with Geometry
Wire, when switching layer, it supports adding Via in the turning point automatically.
4.6 Electric Rule Check (ERC )

After extracting the netlist of each functional module, it needs to perform ERC prior to exporting
netlist data. The ERC function of this software can help to find out the wire net error, such as:
empty thread, floating pin, cell pin without input or output. By performing ERC, it may eliminate
nearly all errors in the circuit, including the reference name, physical and logical errors.
Click the column to
select all options
under it

Click Select All to

select all options in
the dialog
 Physical ERC Digital ERC Analog ERC

Floating Wire Floating InstPin Floating Pin

(The net corresponding to the instance pin
is not connected with any other instance
pin or any pin of this cell.)

Three Wire Point Floating Net Lose W/L Parameter

(The net is not connected with any pin or No w, l parameter of the module
instance.)

Four Wire Point PowerGround Short MOS L>W Value

The power wire net is connected with L value of MOS tube is larger than the W
the grounding wire net. value.

Wire Connect More Than Parallel PowerGround Connect Output Inst Pin RES L<W Value
Wires L value of resistor is smaller than the W
(The power grounding wire net is value.
connected with an instance output pin)

A Wire Connect Two or more vias PowerGround Connect other Inst Pin Device M>1
Power grounding wire Devices in parallel connection
includes other pins.

Floating Via No Signal Source RES S>1

(The wire net is not connected with pin, Resistors in serial connection
and it is not connected with the bi-
directional or output instance pin)

Via Connect More Than Two Output Connected Output Pin IO Error
Lines (The wire net is connected with multiple
output instance pins. )

Overlap Inst Instance Only Connected Self Pin Not Overlap Boundary
(The wire net includes multiple pins of the Pin not included in the accessory of cell
same instance.) framework
Floating Label Instance(Input)Connected Self MOS4 B Term Net
B end is not connected with power
grounding wire net.

Overlap Via Instance(Output)Connect Self MOS D/S Self Connect

MOS D, S are self-connected.

Repeated Via Naming Pin Error (The name of pin MOS D/S Position Error
doesn’t follow the rule of instance
name_pin name. )

MOS D and S are placed in the wrong

position.

More Label
Multiple labels on the wire net
(including pins)

Connected By Label

Repeated Pin
ERC check for analog circuit needs to select the options as below:

Physical ERC:
①Floating Wire

⑥Floating Via

Digital ERC:
① Floating Inst Pin:
The net corresponding to the instance pin is not connected with any other instance pin or any pin of this cell.
② Floating Net:
The net is not connected with any pin or instance.
③ PowerGround Short:
The power wire net is connected with the grounding wire net.
④ PowerGround Connect Output Inst Pin:
Power grounding wire is connected with the instance pin of a certain instance.
⑤ No Signal Source:
The wire net is not connected with pin, and it is not connected with the bi-directional or output instance pin.
⑥ Output Connected Output:
The wire net is connected with multiple output instance pins.
⑦ Instance Only Connected Self:
The wire net includes multiple pins of the same instance.
⑪ Naming Pin:

The name of pin doesn’t follow the rule of instance name_pin name.
Analog ERC:
①Floating Pin

②Lose W/L Parameter

③MOS L > W Value

④RES L > W Value

⑤Device M > 1

⑥RES S > 1

4.7 Schematic View of Export

Tools → Generate Schematic view
Chapter V Workflow for Extracting Netlist
of Digital Circuit
5.1 Open Cell

Open a cell or create a new cell. For how to create cell, please refer to §2.2 Create a New Library, §2.4
Create a Main Macro Unit.

5.2 Library Parameter Setting

Please refer to §Chapter III Library Parameter Setting

5.3 Divide Tasks

Please refer to §2.6 Divide Tasks based on Macro Cell

5.3.1 Instance Placement

The instance placement refers to creating cell template and marking pins in the macro cell area
(Please refer to §7.1 Create Cell Template ) , and then execute auto search for cell instance (Please
refer to §7.5 Auto Search Cell Instance), to search all cell instances of the entire workspace. Moreover,
it may perform the perspective inspection on the searched cell instances. (Please refer to §7.6
Perspective Inspection of Cell, to Confirm Instance )。

5.3.2 Wire Identification

Please refer to §8.1 Auto Search Wires

5.3.3 Via Identification

Please refer to §9.1 Auto Search Vias

5.4 Integrate Tasks and Generate Netlist

1. Refer to Templates
Select Create-Instance to access the pop-up dialog. Click Browse and select the corresponding sub
module.
Click “Module Loc” to move the cell to the corresponding position on the image. After the corresponding
position is found, left-click to drop it.

2. Flatten the sub modules and place the data in the cell

After the templates are referred in the cell, it needs to flatten the sub modules by right-clicking on it and
selecting Flatten.
Generate the wire net and pin for ERC check.

5.5 Electric Rule Check (ERC )

ERC check for analog circuit needs to select the options as below:

Physical ERC:
①Floating Wire

⑥Floating Via

Digital ERC:
①Floating Ins Pin:

②Floating Net

③PowerGround Short

④PowerGround Connect Output Inst Pin:

⑥No Signal Source

⑦Output Connected Output

⑧Instance Only Connected Self

⑪Naming Pin:
Analog ERC:
① Floating Pin

5.6 Schematic View of Export

To generate the schematic view on the macro unit area and TOP area, please select Tools-Generate
Schematic View.
 Basic Library：It is Basic Analog Library: The
library of the analog
by default
cell

Scalar: Conversion
ruler
Chapter VI Enumeration Screen
It is a split-screen positioning function for error inspection during ERC check, wire identification and
Via identification. It can split the target area into multiple screens of the same size, so the user may
perform observation and operation conveniently. Here are the operation instructions: Select View-
Enum Workspace, select prBoundary drawing in Boundary Layer, and set the overlap parameter
percent (generally 5%) between areas, as well as rows and columns. The number of screens can be
viewed in Output column.
Right-click to save the enumeration information to file, and record the enumeration position. Then it can be
positioned to the target position the next time you open it.
Chapter VII Cell Identification
7.1 Create Cell Template

It is applicable to digital circuit. Generally, the cell is defined in POLY layer. Open Workspace, and

select Create-Device-Template Device, or select the icon on the Toolbar to select the image to be
searched.

In the pop-up dialog, select “Search Reduplicate Templs”” to search for similar cells (so as to
prevent creating the same unit for several times repeatedly). Adjust the Min Threshold value
according to the image definition.
If the same template exists, select the searched template and click Use Selected on the lower left to use
it directly.

If none, the pop-up window will show the message that there is no similar cell instance, and you need
to create a cell template.
In this case, please click Create New to add a new one.
Double-click to add a pin.

The pin is located in the position of poly Via or active area Via in MET1 layer. User may switch
between MET1 and Poly layer to confirm the pin position.

After labeling the pin, press the shortcut F8 to finish creation.

7.2 Edit Cell Template

After the cell template is created, return to the Bunny Library Manager screen. In the cell library,
you may see the cell template named templ_XX. Double-click the template on the right view to
enter workspace.
 7.2.1 Draw Device on MOS3 End
Use ruler to measure L value of wire width of POLY pile on POLY layer, and save it. Then switch
the library image to STAIN or DIFF layer, and use ruler to measure W value of width in the active

area. Return to POLY layer, press the toolbar icon to label the tube. After that, identify the
types of tubes under the cell template, and select all P tubes or N tubes. Right-click to select Selected
Poly To MOS. Select PMOS/NMOS if it is PMOS/NMOS. Label the power wire at NB Net point
of the power wire. Match G layer with POLY Drawing, D/S layer with MET1 Drawing. Then G,
D, S pins will be generated.

Step1: Right-click to
select selected Poly
to MOS
Step2: Select
MOS pipe and
power wire
type; match the
pin with the
image layer; and
set parameters
7.2.2 Draw Pin Link

Add P1_C Via at the turning point between POLY and MET1 layers, and link up the wires between POLY and
MET1 layers.
Add global power ground pin

Click the toolbar icon to label the power wire.

7.3 ERC Check for Cell Template

After that, perform ERC check for the data in the area of cell template. Click the menu Check-
ERC Check, select the options of Floating Via and Floating Pin, and click OK. Then it will
perform ERC check automatically.
If any Floating Via and Floating Pin are detected, it will show the error position in the output column
Note:

Floating Via: It refers to the via is not connected

with M1 and M2 layers.
Floating Pin: It refers to the pin is not connected
with any wire.

7.4 Generate Schematic view of Basic Cell

After editing the cell template, right-click to select Template To Schematic, to convert the data in
the template into schematic view. If the schematic view already exists in the library, it will
generate the existing schematic and symbol diagrams automatically.
If there is no result of auto search, it needs to sort the result manually, and update the pin
synchronously.

Instructions for updating pin synchronously: Tools-Update Pins

7.5 Auto Search Cell Instance

Select Tools-Auto Search Instances. In the pop-up screen, set the appropriate similarity. Select the cell
template to be searched and click Start to search. Set the search scope and click OK.
 Set the appropriate similarity, which is 0.7
by default.

Select the target cell

template to be
searched
 Select the search scope.

In the Layout view of the current Top_DG1, view the Output column that shows: There are a total of 12 similar
instances, and it takes 9 seconds to search.
 Output column:
Show the number of
cell templates
searched.

As shown below, I109, I108, I110 and I111 are the cell instances searched. Select any item and you can view the current
template (templ_5) in the Property column on the right side.
 The searched template
templ_5 is shown
under Property.

7.6 Perspective Inspection of Cell to Confirm Instance

After the auto search cells, it needs to confirm the searched cells one by one. In Output column,
press TAB key to locate and view the individual item (press SHIFT+TAB to return to the last
entry). Press the shortcut T to perform perspective inspection in each layer. In the sample screen
below, the searched instance images are shown on the left, while the original cell images after T is
pressed are shown on the right.
 Press T to confirm the cell instances searched.

Besides the perspective inspection function, the software also provides the functions of rotating cell image
horizontally and vertically. When the searched cell image has some difference from the original cell image in
terms of the pin direction and link direction, such function can be used for adjustment.

*Press icon to rotate 90 degrees counter-clockwise

*Press icon to rotate 90 degrees clockwise

*Press icon to view the image related to Y axis

*Press icon to view the image related to X axis

If the searched cell instance is inconsistent with the original cell image, press “Delete”
button to remove such instance.
Chapter VIII Wire Identification
8.1 Auto Search Wires

Before auto search wires, select the ruler to measure the wire width, and set the L value of wire width of the
tube in the current image layer (generally M2 layer or the layer above M2). Select PrBoundary image layer and
the subject, and then press Tool-Auto Search Wires. Set the corresponding image layer and wire net layer. Input
the measured L value of wire width, press Start, set the search scope and press OK.
When the rectangular box
is in the state of selected,
the color of the frame will
turn white.
Chapter IX Via Identification
9.1 Auto Search Via

Select PrBoundary image layer and the subject, and then press Tools-Auto Search Via. Set Via
Definition, and click Get Threshold By Cursor. Move the cursor on the Via and select the brightness
of Via. Confirm the search scope and click OK.
via auto-search is
completed.
 Chapter X Connect
10.1 Connect by Pressing P

Bunny software provides three methods of connecting:

(1) Connect by pressing the shortcut P;
(2) Connect by selecting Create-Shape-Geometric Wire ;

(3) Connect by selecting the toolbar icon .

10.2 Wire Tracking Function

The connect tool of Bunny software can track the wire. That is: When the user needs to drill Via during
the link, it doesn’t need to stop connecting and switch to the tool of drilling Via, but can finish the
Via drilling work while connecting synchronously.
Point to the Via position
Chapter XI Workspace Data Export
The software provides the workspace data export function, which specifies the formats of
processed files. It supports exporting the data in the formats of Edif200, Verilog, CDL and Spice.
After the netlist of each functional module is extracted, it can export the netlist to the positive design
software such as Synopsys and Cadences for re-design.

Supported platforms: Linux or Windows

system

Linux platforms: /bin/linux/opt/edifout

Windows platforms: /bin/win64/opt/edifout.exe

The program is scripts with parameters, which can be called by batch with scripts.

s
11.1 Verilog

Library: Name of library

CellName: Name of cell

Viewname: The name of library, cell and view for the target to be exported. It should be the view
name corresponding to the schematic view, which is schematic by default.

OutputFile: Name of output file

Note: When exporting Verilog file, it is exported by layers until the cell contains functional view. If
the cell contains functional view, the HDL of the cell is represented by the content of the functional
view.
11.2 Edif200

Linux platform: edifout libname cellname viewname [extendLibNames] [outputFile]

extendLibNames: It is the name of dependent external library. Generally, it should enter the self-
library of cadence software (basic, analogLib). In case of multiple names, it should be separated
by “,” .

outputFile: The file path of edif200 to be exported

Windows platform

Edifout.exe libname cellname viewname [extendLibNames] [outputFile]

When it is the console or script, set the current path in this executable file folder, or add the path in
the system environment.

Run Directory:
It is the path where the file is generated. The files are under the path designserver on Server by default.
For the sake of security, the files are only saved on Server, so the path is on the Server.
Library: Name of library

CellName: Name of cell

Viewname: The name of library, cell and view for the target to be exported. It should be the view
name corresponding to the schematic view, which is schematic by default.

OutputFile: Name of output file

11.3 CDL

Library: Name of library

CellName: Name of cell

Viewname: The name of library, cell and view for the target to be exported. It should be the view
name corresponding to the schematic view, which is schematic by default.

OutputFile: Name of output file

11.4 Spice

Library: Name of library

CellName: Name of cell

Viewname: The name of library, cell and view for the target to be exported. It should be the view
name corresponding to the schematic view, which is schematic by default.

OutputFile: Name of output file

Chapter XII Cross Reference
Bunny software provides the Cross Reference function (shortcut F7), it allows the user to switch
between the layout and schematic view.

 Cross Reference Instances : Cross reference of instances

 Cross Reference Signals: Cross reference of wire nets

 Cross Reference of instances and signals

 12.1 Cross Reference Instances

Examples of cross reference instances:

Example 1
Example 2
 12.2 Cross Reference Signals

Example of cross reference signals:

Example 1
Example 2
12.3 Cross Reference of Instances and Signals

Cross Reference of instances and signals:

 Chapter XIII Net Track Navigation
13.1 Net Track Relationship of Probe

Probe can track and show all elements on the wire net.
Select Create-Probe-Add Net to highlight a wire, then all connected wire nets will be highlighted as
well. Select Create-Probe-Remove Net to cancel the highlighted net, or select Remove All to cancel all
highlighted nets. You may also set the corresponding shortcuts.

Layout net track:

Schematic net track:

The sub module shows the highlighted

wire nets on the matched upper layer.
 13.2 Shortest Route Inspection

When editing the layout, use the function of Track Navigator. Select any two devices to generate the
shortest route, which can facilitate the circuit error checking. Select a net within the cell to highlight it.
Then the connected instances will be shown in the list of Track Navigator, as shown below:

In the list of Track Navigator, click any of two devices and right-click to select Shortest Route, as
shown below. The part highlighted red shows the shortest route in the wire net.
 13.3Pin To Pin Line Shown in Jump Wire

The jump wire allows user to view the Pin To Pin line on the same wire net. Click any net or pin on
the schematic view to extend the related jump wires.
Chapter XIV Circuit Hierarchical Arrangement
Arrange the sub modules based on Top cell version and template. Place the devices in appropriate
position to finish preliminary arrangement. Don’t pack up the cells in this time.

Circuit extraction and arrangement: Layout→ schematic view→ symbol diagram, is the entire process of
circuit hierarchical arrangement. The engineer refers to the previous layout to make the flattened netlist into
hierarchical structure in the easy-to-read format.

When editing the previous layout, user divides the main macro cell TOP/BLOCK. By creating sub cells
and dividing functional modules, it realizes the collaborative operation of multiple users. That is also how
the circuit hierarchical arrangement works. The user must arrange the circuits in the Subschematic of the
sub cell generated from the Schematic of cell. If it is done in the Schematic, the Schematic will become
flattened netlist when the layout needs to be updated in case of error, which may cause loss of arranged
circuits. If it is done in the Subschematic, only the logic relationship will be changed after the update of
sub cell, which won’t change the arranged circuits.
14.1 Export Schematic view, and Create Sub Cell

Before flattening the netlist for the analog circuit, it needs to swap D and S of MOS tube. Open the
layout of analog circuit and select Tools-Swap MOS D/S.
Enter the name of power line in Power Names;
Enter the name of grounding line in Ground Names;
Select the corresponding PMOS and NMOS.
14.1.1 Generate Flattened Netlist

Select Tools-Generate Schematic View and set the Scalar.

14.1.2 Create Subschematic for Sub Cell

After the steps instructed in §14.1.1 Generate Flattened Netlist, press F7 to enter the schematic
view directly. Or find the schematic view corresponding to the library in the Bunny Library Manager
screen. Double-click on it to enter Schematic workspace. Select all and right-click to select Put Into
SubCircuit (or select Edit-SubCircuit-Put into SubCircuit) to create Subschematic of sub cell
successfully.
14.2 Preliminary Hierarchical Arrangement of Circuits

It means the engineer identifies the functional module in the graphical circuit diagram and re-
organizes the hierarchical circuit structure from bottom to top. After that, it draws the circuit
diagram in each layer that is intuitive and easy-to-understand. This is also an overlapping process.
The process from identifying small macro cell to the large cell composed of small macro cells
until the circuit diagram on the top circuit layer is simplified as the symbol of circuit diagram that
contains some large functional modules.

14.2.1 Arrange Modules

Based on the knowledge in the circuit field and by referring to the information of the layout, the
engineer identifies the functional modules, and works out a complete cell template of functional
module through manual arrangement. During this process, it requires performing the operations on
the device/cell, such as alignment, flip, arrangement and replacement.

Drag-and-drop, arrangement and replacement of devices/cells

After Subschematic is created, select all and right-click to select Put Into Trace Window. Then all
devices in the Subschematic of sub cell will be listed in order under Trace column (wire net track
navigation column). The operation can be performed reversely. Select the device type in Trace
column, and move it to the current window/main view window/Sub window/other window by
drag-and-drop. Set the number of rows and columns in Drop Options. Then all devices will be
arranged in torque.
Trace instance:

Select the corresponding instance. shift+ selecting can add the selected instance, while ctrl+
selecting can reduce the selected instance.

Right-click to select “put into trace window” to move the selected instance into the Trace screen.
Trace pin:

Select all devices, right-click to select Trace All Pins. Then all pins will be listed under Trace column.
Select Pins tube of Trace column. Use the cursor to move it to the workspace.

Note: During the arrangement, you may view all devices connected with the pin of highlighted devices
on the Trace column on the right. The red indicates it is not in the cell template, while green indicates it
is in the cell template.
Alignment and flip of devices/cells
In this part, the shortcut function of alignment (upper/lower/left/right) and flip (up-down/left-
right/clockwise/counter-clockwise) is most the most frequently.
As for the shortcut setting, please refer to §Chapter XVI Default Shortcut Setting.

Select Edit-Show Wire Name to show the relationship between the name of wire net and the link of
wire net.
 Finally, work out the complete cell template of functional module, as shown below.

14.2.2 Auto Search Macrocell

This function can help the user to find the wire net with the consistent relationship and replace
the instance used by the functional module of the same structure.

Select Tools-Search Macrocell to access the pop-up window. Click to select the cell

template to be searched, and click OK to confirm.

View the search result in the output column.
Click anywhere in the output column, and right-click Relayout Matched to link up the relationship
automatically. Replace the instance used by the functional module with the same structure.

Optimize the unnecessary lines and texts. For the excessive texts generated during the link, it may
execute Tool Optimize Data to delete.
14.2.3 Error Correction

If any error is found during the circuit arrangement, such as tube type, missing wire, or net

relationship, it needs to return to the layout for modification. After the correction, it should update

the netlist and import the schematic view again. Moreover, it needs to refresh the data by pressing

the shortcut F5 in sub. As shown below, if the tube type of the module marked red is misjudged, it

should select the correct tube in the Property column, and click Apply Currently Only. Then select

Tools-Regenerate Netlist to regenerate the netlist.

After refreshing the netlist, select Tools-Generate Schematic View to generate the schematic view
again.
It is recommended selecting Edit-Refresh Data (or pressing the shortcut F5) in the area of sub cell.

Click the tool icon to check the error of schematic view automatically. Then the check result
will be output in the Output column.
14.3 Layers Integration

After the hierarchical arrangement is done for all circuit diagrams obtained from task allocation, it
also needs to integrate into a complete hierarchical circuit diagram. After all circuit diagrams are
put together, the circuit on top layer includes multiple large functional modules from each circuit
diagram. Continue to create layers for the circuit on top layer to replace these functional modules
with larger functional modules. This step requires a good understanding of the architecture of the
top layer on the chip, which is generally done by a certain engineer. For the circuit in large scale,
when the tasks are allocated to many engineers for arrangement, the homonymous functional
modules can be shown in different circuit diagrams. During the layer creation, the engineer will
create the macro cells with different names for these homonymous functional modules, which
results in the redundancy of macro cell library. Another work in the stage of layer integration is to
remove the redundant macro cell modules.

Bunny function of Auto Search Macrocell can be used to judge whether the homonymous macro
cell exists in the bank. It yes, only one macro cell is reserved, while others will be replaced by the
instance of the reserved macro cell.
Chapter XV Circuit Analysis
In the stage of circuit analysis, the user may check and correct the net relationship and the hierarchical
structure of the circuit diagram by using the functions of “Net Track Navigation” and “Cross
Reference”.

15.1 Net Track Navigation

Please refer to § Chapter XIII Net Track Navigation

15.2 Cross Reference

Please refer to § Chapter XII Cross Reference

Chapter XVI Default Shortcut Setting
The shortcut of the software can be set through Options-Shortcut.
The default shortcut setting is as listed below.

Default shortcut of layout editing:

Name Shortcut Description

New Ctrl+N New

File Open Ctrl+O Open

Close Ctrl+W Close

Save Ctrl+S Save

Refresh Data F5 Refresh Data

Undo U Undo

Edit Redo Shift+U Redo

Move M Move

Duplicate C Duplicate

Stretch S Stretch

Delete Del Delete

Flip Horizontal H Flip Horizontal

Rotate

Flip Vertical V Flip Vertical

 Select All Ctrl+A Select All

Invert Selection Shift+A Invert Selection

Merge Shift+M Merge

Chop Shift+C Chop

Basic Left Move Shift+Left Left Move

Right Move Shift+Right Right Move

Top Move Shift+Up Top Move

Bottom Move Shift+Down Bottom Move

Return To Top Shift+B Return To Top

Edit In Place X Edit In Place

Hierarchy Return To Top Shift+B Return To Top

Return To Level B Return To Level

Properties Cellview Shift+Q Cellview

Select All Ctrl+A Select All

Deselect All Ctrl+D Deselect All

Select Invert Selection Shift+A Invert Selection

Copy To Clipboard Ctrl+C Copy To Clipboard

Paste To Clipboard Ctrl+V Paste To Clipboard

View Zoom In ] Zoom In

 Zoom Out [ Zoom Out

Zoom To Selected Ctrl+T Zoom To Selected

Zoom To Fit F Zoom To Fit

Previous View W Previous View

Next View Shift+W Next View

Hide Select Items Ctrl+` Hide Select Items

Hide Background ` Hide Background

Image Image

Next Item Tab Next Item

Previous Item Ctrl+Tab Previous Item

Location Ctrl+L Location

Show Command Show Command

F3
Dialog Dialog

Add Noconn Add Noconn

Space
Shortcut Key Shortcut Key

Instance I Instance

Rectangle R Rectangle

Create Polygon Shift+P Polygon

Geometric Wire P Geometric Wire

Path Ctrl+P Path

 Label L Label

Via O Via

Cross Reference F7 Cross Reference

Cell and Ins Diffs T Cell and Ins Diffs

Check
Find Marker G Find Marker

Delete Marker Ctrl+G Delete Marker

Find/Replace Shift+S Find/Replace

Tools Create Ruler K Create Ruler

Clear All Rulers Shift+K Clear All Rulers

Default shortcut of circuit arrangement

Name Shortcut Description

New Ctrl+N New

File Open Ctrl+O Open

Close Ctrl+W Close

Save Ctrl+S Save

Refresh Data F5 Refresh Data

Edit Undo U Undo

Redo Shift+U Redo

Move M Move
 Duplicate C Duplicate

Stretch S Stretch

Delete Del Delete

Flip Horizontal H Flip Horizontal

Rotate
Flip Vertical V Flip Vertical

Space Evenly X Ctrl+Shift+X Space Evenly X

Space Evenly Y Ctrl+Shift+Y Space Evenly Y

Left Move Shift+Left Left Move

Basic
Right Move Shift+Right Right Move

Top Move Shift+Up Top Move

Bottom Move Shift+Down Bottom Move

Hierarchy Return To Top Shift+B Return To Top

Properties Cellview Shift+Q Cellview

Select All Ctrl+A Select All

Deselect All Ctrl+D Deselect All

Select Invert Selection Shift+A Invert Selection

Copy To Clipboard Ctrl+C Copy To Clipboard

Paste To Clipboard Ctrl+V Paste To Clipboard

View Zoom In ] Zoom In

 Zoom Out [ Zoom Out

Zoom To Selected Ctrl+T Zoom To Selected

Zoom To Fit F Zoom To Fit

Next Item Tab Next Item

Previous Item Ctrl+Tab Previous Item

Location Ctrl+L Location

Show Command Show Command

F3
Dialog Dialog

Wire(narrow) W Wire(narrow)
Create
Wire(Wide) Shift+W Wire(Wide)

Text Shift+N Text

Note
Shape N Shape

Cross Reference F7 Cross Reference

Check Find Marker G Find Marker

Delete Marker Ctrl+G Delete Marker

Next Ctrl+Tab
Windows
Previous Ctrl+Shift+Backtab
 Chapter XVII FAQ
17.1 Conversion between Cadence514 and Cadence615

 514 to 615 (CDB to OA)

1. Open the terminal, and start Cadence 615. The Command is virtuoso &
Note: This path can’t contain the target library to be converted. It is suggested opening Cadence 615 in
an empty folder.
2. Select Tools Convert Tool Box in the main screen, as shown in Figure 1:

Figure 1
The window as shown in Figure 2 will show up:
 Figure 2 Conversion Tool Box

Click “CDB to OpenAccess Translator” to access the dialog as shown in Figure 3.

 Figure 3 CDB To OpenAccess Dialog

In Path To cds.lib file, select the cds.lib path of the target library to be converted. Move the
library left/right by using the button “-” “-” Libraries to convert is the targets to be converted. Note
that the conversion will follow a certain order, which can be changed by pressing Up, Down,
Order buttons. The bottom layer must be converted first.

 615 to 514 (OA to CDB)

1 . Open the terminal, and start Cadence 615. The Command is virtuoso &
Note: This path can’t contain the target library to be converted. It is suggested opening Cadence 615
in an empty folder. You may create a cds.lib file under this path, and copy the library in bottom
layer that the target library relies on, which is defined in the cds.lib file. If the library in bottom
layer is also 615, it needs to be converted separately. The library in bottom layer should be converted
first, followed by the library in upper layers.
2. Enter the command oa2cdb in the terminal. If it is not found,
view the directory $CDS_ROOT/tools/dfII/bin/oa2cdb.
 3. oa2cdb -lib LEDIC -cdslibpath /home/userhome/LEDIC_PRJ/lib.defs -tech

analogLib -tech basic

-lib Target library to be converted

-cdslibpath : The definition of cadence615 library, which contains the definition of the library to be
converted.

-tech: The technology file to be called must be defined in cds.lib under the startup directory.
4. The specific command is as shown below:
17.2 Modify the coloring scheme of the library

1. In the dialog Bunny Library Manager, select Tools--->Display Resource Editor…as shown in
Figure 1.
 Figure 1

Display Resource Editor screen will show up, as shown in Figure 2.

In Tech Lib, select the target library, and find the target Lpp (layer and Purpose) layer in the left list.
The options on the right are the same as cadence. After the modification, click “X”. It will prompt
to save the modification, click “YES”.
 Figure 2 Resource Editor Dialog

2. After the modification, open the layout view of a cell. Click “Reload” under the small triangle
after Active in the dialog Layers to show the modification synchronously.
17.3 Attach image layer and shape layer

When switching the image layer, the shape layer will be switched accordingly. Each metal layer
has default wire width. The operation such as adding Via and automatic display of the definition of
Via corresponding to the image layer, requires setting the attachment relationship of image layer
and shape layer.
1. Open the layout view corresponding to a cell, click “Options->Display”, with the shortcut “E””.
In the pop-up dialog “Display Option”, selection option “Layer Map”.

Figure 1 Display Option

In the dialog, enter the corresponding layer, Via, default width and the corresponding shortcut for
switching image layer based on different technology files.
 17.4 Change shortcut for switching image layer

1. Open the layout view corresponding to a cell, click “Options->Display”, with the shortcut “E””.
In the pop-up dialog “Display Option”, select option “Layer Map”.

Figure 1 Display Option

In the column Image Key, double-click to enter the corresponding shortcut. The previous version only
supports the number 0-9 .

17.5 Deploy the Image Library to Different Servers or Different

Partitions of the Same Computer

It accesses the image libraries on different computers by sharing folder, which requires Bundy
running on the Server.
1. Create index for image library

In Bunny main screen, click “Tools Image Path Manager” to access Manager dialog.
Click the button “…” to browse the”.icf” file in the image library.

2. Attach the image onto the library

In Bunny main screen, click “Tools Attach Image”. In the pop-up screen, the library is shown
on the left, while the image is shown on the right. Click Value column under the library to access
the drop-down menu, and then select the target image from the list. After that, click “X” to close
the dialog.
For the Server installed on Windows platform, it needs to modify the user account that is used to start
Designserver .

Right-click “This PC”, “ Manage”, “Service”, and locate “designserver” service.

3. Right-click “designserver” to select Properties, enter “Log On”, and select “This account”. Then
enter the user name and password when accessing the shared folder.
17.6 How to modify the width of the entire wire after it is
highlighted by double-clicking?

After a wire net is highlighted by double-clicking, all data (wire, Via and pin) under the same wire
net will be added to the selected list. The steps of modifying the wire width:

1. Click “Tools Reset Data Reset Wire Width” to access the dialog as below
 Figure 1 Modify Wire Width

Fig Type:

Select Figs: Modify the selected wire only

All Select &Visible Figs: Modify visible and available wire (Controlled by Layer
dialog)
Layer Type:
All Layer: All layers
Layer: Modify specified layer
New Width: New wire width

To modify the width of all selected wires upon demands, select All Layers.

To modify the wire net of a certain layer of the selected wire, select Layer and click the specified layer.

1. For the version above V1.3.2 , it may select Apply Current Selected in Properties for
modification. This function can modify all selected wires including those in different layers.

After the wire width is modified, please pay attention to the position of both ends, so as to
prevent short circuit after the modification.
 17.7 How to extend and slight adjust the local parts when the path
line is long, and it contains some line segments , which
indicates some deviation?
Select the target path line, move the cursor to the target position. When the cursor turns to , keep
holding the mouse and move it to the target position.

17.8 When selecting cells, multiple devices in parallel connection are

selected as one. When it needs to be separated, how to separate the
path and cell and remove a single path only?

For the version below V1.3.1, the software supports flattening and re-organizing all devices, and
updating the corresponding parameters.
Re-organize devices:

Query the number of M/L marks included in the selected area of the device, and compare it with the
original parameters to judge whether the “W/L” value and the serial/parallel connection relationship
of the resistor are required.

Flatten devices:
M/L mark layer gets out of the device. In this way, M/L mark won’t be removed after
the device is deleted.
Update device parameters:

Click “Update W/L Mark Parameter” to re-map the updated M/L information to the device.
 For the version above V1.3.1, it supports modifying the selected device.

17.9 It can’t distinguish the target cell when the distance of pins
between the neighboring cells is close. Can the pin be highlighted
when the cell is highlighted?

For the version V1.3.1, it supports modification in the “Display Option” dialog.

After selecting High Light FigGroup Figs and selecting device, the entire device will be highlighted.
However, it doesn’t support shape selection.

17.10 Add the required parameter when the default device parameters
are insufficient

Open the layout view corresponding to the device from Bunny main screen.
The cell property screen will show up, as shown below:
 Cell Property

In the Cell Property screen, click “Add” to add the target parameter.

Screen for adding parameter

Attribute name: Name of property

Value: Default value of property

After the device is labeled, select it to view the value of the property in the
property screen.

17.11 When the circuit diagram only shows M=, or L=,W=

Open the target symbol view, press “Shift+Q” to access the cell property screen. In the Cell
Property screen, add the default value for m, l and w .

17.12 How to modify pin size of the cell when it is not intuitive
enough when connecting with pin?
The pin size is determined by the Via size. For example: the pin size of M1 layer is the size of cut
layer in Via1, and the pin size of M2 layer is the size of cut layer in Via2.

Modify the pin size for the drawn device.

Pop-up Window of Reset Device Pin Size
Size Value: It can be value or percent depending on whether “The Value is scalar” is selected.

If it is selected: It indicates zoom-in by 1.5 time. If it is not selected: It indicates the size is 1.5µm.
Device Pin Size: Modify the pin size of device.

Command Pin Size: Modify the pin size of cell.

Hier: Modify hierarchies
After clicking “OK”, the Output screen will output the error position that may cause short circuit
after the pin size is modified.

Modify the pin size for the next creation

Please refer to Modify Via Size

17.13 Modify Via size

Pop-up Window of Via Setting

Name: Name of Via

Constact: Cut layer parameter of Via

Dimensions: Width and height of cut
layer
Space: Horizontal and vertical spacing
of Via torque

Layer1 Enclosing CONT: Distance of cut layer enclosing layer1

Layer2 Enclosing CONT: Distance of cut layer enclosing layer 2

17.14 When connecting with pin, the default layer of B end

of MOS tube is DIFF, which is POLY for G end. Can they be
modified?

Yes, they can. In different workspace, it needs to modify B and G ends as different layers. The
operation is as instructed below:
 弹出 Device Setting 对话框。

G Pin Layer: Layer of G PIN

B PIN Layer: Layer of BPIN
17.15 How to add new device

The Device Setting screen will show up.

Double-click the column corresponding to the Module Names to edit it. Enter the name of the target
device, which should already exist in the library of Default Symbol.
17.16 What if it is a three-terminal resistor?

The labeled pin is from the symbol view. If the symbol view is a three-terminal pin, the software will
read the same result.

17.17 What if it fails to connect with one end of the device?

1. Check whether the number of pins in the layout view is consistent with that on the symbol view.
In case of inconsistency, delete the layout view of the device. Label another device in the other
workspace to generate new pin.
 Execute the menu to recover the connect relationship

17.18 What if wrong device type is extracted after

labeling some devices?

Enter Navigate menu to show Instances or Cells based on specific demands. Or select the target

device by Shift+ Clicking. In the Property screen, the value of Cell Name is the desired device type.
Lastly, click “Apply All Selected”.
Note: The modification must ensure the device cell name should have the consistent pins.

17.19 What if the device pins are missing after labeling

some devices?

The current solution is to remove all device instances, and the layout view corresponding to the
device. After that, delete the symbol view corresponding to the device. Lastly, label the device again.
In the future version, the function of device repair will be added.

17.20 What if the name of cell created on Windows platform

contains English letters in upper case and %？

For the data of the version below V1.3.1, download libcase software, remove “%”, and modify the
quotation relationship. For the new library, please download the latest Bunny software.

17.21 Automatic extraction of W, L, M values of analog

devices

When extracting the analog area, it extract the required parameters by drawing the mark layer and
extracting the analog device, with the steps as below:

Click the toolbar W/L label to enter W/L drawing status. Press “F3” to access the parameter setting
screen, as shown in Figure 1:
 Figure1 Parameter Setting Screen

Poly Mark Layer: The layer lastly set as without filling style. The configuration is saved on client.
When it is edit by multiple users, please make the setting again into uniform layer.

Shape: Select different shapes based on different types

L Value: Default L value,

L Step: Length increased every time by pressing “Ctrl+

Right Arrow Key”

W Min Value: Default W value,

W Step: Accuracy value of W.

2. The cursor position will show W/L value. After drawing to the target position based on the
image, double-click or press Enter key to exit, as shown in Figure 2.
 Figure 2 Screen of Drawing W/L

When the size is the same, copy multiple devices of the same size, as shown in Figure 3.

Figure 3 Copy Screen

Select “Keep Copying” to enter the status of copying repeatedly. Press “ESC” to exit marking. Click
different device based on the technology. When selecting device, it needs to contain the target shape,
as shown in Figure 4.

Figure 4 Label Device

For the inverted tube, please select “Swap W/L.”.

The resistors can be in serial or parallel connection, as shown in Figure 5 and Figure 6:
Figure 5 Connecting resistors in parallel and exchange W/L value

Figure 6 Connecting resistors

in parallel and exchange W/L
value
Figure 7 Connecting resistors in serial and exchange W/L value

Figure 8 Connecting resistors in serial and exchange W/L value

This Manual user is limited to the purchase, lease and use of the Bunny Software. No
written permission of Silintech Inc. shall not copy and disseminate any part of this
specification for any purpose, in any form of means.

If users have any other questions or suggestions about the use of this software, please
@support: [email protected]. Thank you!

Document Edition: Bunny Version 1.0

© Silintech Inc.