ARM - Advanced RISC Machines

RISC- Reduce Instruction Set Computers

 ARM Design Philosophy

• ARM Core uses a RISC architecture

• ARM licenses its cores out and other
companies make processors based on its
cores
• ARM processor core based
microcontrollers
• Von Neumann architecture.
 ARM Design Philosophy
• Reduce power consumption
• High code density
• Price sensitive
• Reduce the area of the die taken up by the
embedded processor
• Incorporated hardware debug technology
(ICE)
 ARM processor core based
microcontrollers
• Key component of many 32 –bit embedded
systems and Portable Consumer devices
• ARM1 prototype in 1985
• One of the ARM’s most successful cores is the
ARM7TDMI,provides high code density and
low power consumption.
 ARM7TDMI

• T –Thumb 16 bit compressed instruction set

• D – on chip Debug request
• M – enhanced Multiplier(yields 64 bit result)
• I – Embedded ICE hardware to give on-chip
breakpoint and watchpoint support

ICE – in circuit emulator for debugging

 The RISC Design Philosophy
• RISC is characterized by limited number of
instructions
• A complex instruction is obtained as a sequence
of simple instructions.
• So, in RISC processor, software is complex but the
processor architecture is simple.
• Large number of registers are required.
• Pipelined instruction execution.

• Ex : ARM, ATMEL AVR, MIPS, Power PC etc

 The CISC Design Philosophy
• CISC is characterized by large instruction set.
• The aim of designing CISC processors is to
reduce software complexity by increasing the
complexity of processor architecture.
• Very small number of registers are available.
• Ex : Intel X86 family, Motorola 68000 series.
 RISC –4 major design rules
1. Instructions

• Reduced Number of Instructions

• Execute in a single cycle
• The compiler synthesizes complicated
operations
• Each instruction is a fixed length
2. Pipelines

• The processing of instructions is broken down

into smaller units that can be executed in
parallel by pipelines
3. Registers

• Have a large general purpose register set

• Any register can contain either data or address
4. Load –Store Architecture

• Separate load and store instructions transfers

data between the register bank and external
memory.
• Memory accesses are costly, so separating
memory access from data processing provides
an advantage, because you can use data items
held in register banks multiple times without
needing multiple memory accesses.
 Load/Store Architecture
• Memory accesses slow a processor down.
• There are times when the processor is doing nothing, while
waiting for memory accesses to complete.
• So, we define a new architecture. In this new load/store
architecture, the addressing mode for every operand is
fixed. (So, there are no bytes for addressing mode
information.)
• And, for arithmetic/logical type instructions, the addressing
mode for all operands will be register mode.
• We make sure that there are enough registers, because
everything ends up in registers.
• To get stuff to/from memory and into/out of registers, we
have explicit instructions that move data.
• Load instructions read data from memory and copy it to a
register. Store instructions write data from a register to
memory.
 Overview: Core Data Path
 Data items are placed in register file
• No data processing instructions directly manipulate data in
memory
 Instructions typically use two source registers and
single result or destination register
 A Barrel shifter on the data path can pre-process
data before it enters ALU
 Increment/Decrement logic can update register
content for sequential access independent of ALU
Multiply and Accumulate
 Registers
 General purpose registers hold either data or address
 All registers are of 32 bits
 In user mode 16 data registers and 2 status registers
are visible
 Data registers: r0 to r15
• Three registers r13, r14 and r15 perform special functions
• r13: stack pointer
• r14: link register (where return address is stored whenever
a subroutine is called)
• r15: program counter
 Registers contd..
Depending upon context r13 and r14 can also
be used as GPR
In addition, there are two status registers
o CPSR: Current Program Status Register
o SPSR: Saved Program Status Register
 Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V U n d e f i n e d I F T mode
f s x c
• Condition code flags • Interrupt Disable bits.
– N = Negative result from ALU – I = 1: Disables the IRQ.
– Z = Zero result from ALU – F = 1: Disables the FIQ.
– C = ALU operation Carried out • T Bit
– V = ALU operation – Architecture xT only
oVerflowed – T = 0: Processor in ARM state
– T = 1: Processor in Thumb state

• Mode bits
– Specify the processor mode
 Processor modes
Processor modes determine
• Which registers are active and
• Access rights to CPSR register itself
Each processor mode is either
• Privileged: full read-write access to the CPSR
• Non-privileged: only read access to the control
field of the CPSR but read-write access to the
condition flags
 Processor modes contd..
ARM has seven modes
• Privileged: abort, fast interrupt request, interrupt
request, supervisor, system and undefined
• Non-privileged: user

User mode is used for program and

applications
 Privileged modes
Abort: when there is a failed attempt to access
memory
Fast Interrupt Request (FIQ) & interrupt
request: correspond to interrupt levels
available on ARM
Supervisor mode: state after reset and
generally the mode in which OS kernel
executes
 Privileged modes contd..
System mode: special version of user mode
that allows full read-write access of CPSR
Undefined: When processor encounters an
undefined instruction
 Banked Registers
Register file contains in all 37 registers
• 20 registers are hidden from program at different
times. These registers are called banked registers
• Banked registers are available only when the
processor is in a particular mode
• Processor modes (other than system mode) have a set
of associated banked registers.
• Maps one-to-one onto a user mode register
 Register Banking
Current Visible Registers
Current Visible Registers User Registers replaced by
r0
User Mode
User r1r0 banked registers
r2r1
r2
r3 Banked out Registers
r4r3 Banked out Registers
r5r4
r6r5
FIQAbort IRQFIQ IRQ
SVC SVC
Undef Undef
Abort
r7r6
r8r7 r8 r8
r9r8 r9 r9
r9
r10 r10 r10
r10
r11 r11 r11
r11
r12 r12 r12
r12
r13 (sp) r13 (sp) r13r13
r13 (sp) (sp)
(sp) r13 (sp) r13
r13 (sp)
(sp) r13 r13
(sp)(sp)
r13 (sp)
r13(lr)
(sp)
CPSR r14 r14 (lr) r14r14
r14 (lr) (lr)
(lr) r14
r14 (lr)
(lr) r14
r14 (lr)
(lr) r14 r14
(lr)(lr)
r14(pc)
(lr)
copied r15
r15 (pc)
into cpsr
SPSR spsr
cpsr spsr spsr
spsr spsr
spsr spsr
spsr spsr
spsr
 SPSR
• Each privileged mode (except system mode)
has associated with it a SPSR (Stored Program
Status Register)
• This SPSR is used to save the state of CPSR
(Current Program Status Register) when the
privileged mode is entered in order that the
user state can be fully restored when the user
process is resumed
 Mode changing
• Mode changes by writing directly to CPSR or
by hardware when the processor responds to
exception (any condition that needs to halt
the normal sequential execution of
instructions) or interrupt
• To return to user mode a special return
instruction is used that instructs the core to
restore the original CPSR and banked registers