Scribd
Upload
7 views5 pages

Digital Assignment

The document outlines an assignment involving Verilog code for implementing fundamental logic gates (OR, NOT) and their corresponding testbenches. It includes descriptions of key components of Verilog modules and testbenches, along with truth tables and Boolean expressions for the gates. Additionally, it requires the implementation of a specific Boolean expression Y = (A.B)' and its verification code.

Uploaded by

divymathur12345678901
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
7 views5 pages

Digital Assignment

The document outlines an assignment involving Verilog code for implementing fundamental logic gates (OR, NOT) and their corresponding testbenches. It includes descriptions of key components of Verilog modules and testbenches, along with truth tables and Boolean expressions for the gates. Additionally, it requires the implementation of a specific Boolean expression Y = (A.B)' and its verification code.

Uploaded by

divymathur12345678901
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

‘ASSIGNMENT 1’

S24CSEU1843

DIVY MATHUR

LAB TEACHER -: NIHARIKA KESHARI

Q4. Write a Verilog code to implement OR gate. Write the corresponding


Testbench code for the verification of your Verilog code.

OR GATE

FILE ortest.v.txt

Notepad screenshot

FILE orgate.v.txt
Output CMD OR GATE

Question 3. Write a Verilog code to implement NOT gate. Write the


corresponding Testbench code for the verification of your Verilog code.

NOT GATE

FILE nottest.v.txt

FILE notgate.v.txt

Output CMD NOT GATE


Question 2. Draw the Symbol along with their truth tables and Boolean
expressions of fundamental building gates used for digital design.

Ans: There are three fundamental building gates.

Gates Symbol

1.Not(~) 2.And (&) 3.Or (|)

A = input , B = input , Y = output

1. Truth table of Not Gate

A Y

1 0

0 1

2. Truth table of And Gate 3. Truth table of Or Gate


A B Y A B Y

1 1 1 1 1 1

1 0 0 1 0 1

0 1 0 0 1 1

0 0 0 0 0 0

Question1: Describe the key components of a Verilog module and a


testbench. Clearly explain the purpose and role of each component in the
process of hardware design and verification.

Ans: Key Components of a Verilog Module:

1. Module Declaration: Defines the module’s name and specifies its interface,
which includes the input and output ports.

2. Data Types: This includes the definition of input and output ports, which can
be of various data types like `wire`, `reg`, etc.

3. Internal Signals: These are intermediate signals declared within the module
using `wire`, `reg`, or other data types, used for internal computations.

4. Structural Logic: This part includes the combinational and sequential logic,
using constructs like `always` blocks, `assign` statements, and `initial` blocks.

5. Parameterization: Allows modules to be configurable by defining parameters


that can be overridden during module instantiation.
6. End module: Marks the end of the module definition.

-Key Components of a Verilog Testbench:

1. Testbench Module Declaration: Similar to a regular module, but it does not


have ports. It’s used to test the design and ensure functionality.

2. Instantiation of DUT: The design under test is instantiated within the


testbench.

3. Stimuli Generation: This involves creating input signals using `initial` and
`always` blocks to apply different test cases.

4. Clock and Reset Logic: A testbench often includes clock generation and reset
logic to mimic real hardware conditions.

5. Monitoring and Verification: Using display statements (`$monitor`,


`$display`) or testbench-specific constructs to observe the outputs and verify
correctness.

6. End of Simulation: Often includes a statement to terminate the simulation


after the desired test duration.

Question 5. Write a Verilog code to implement the Boolean Expression Y =


(A.B)'. Write the corresponding Testbench code for the verification of your
Verilog code. Identify the gate that matches to this operation.

Answer: Verilog code


]

OUTPUT

You might also like