Unit-II

1. a) Draw the VHDL program file structure and explain the same with the syntax of a VHDL
entity declaration and architecture definition.

Ans) VHDL PROGRAMINIG STRUCTURE

VHDL is a hardware description language that can be used to model a digital system. The digital
system can be as simple as a logic gate or as complex as a complete electronic system. A hardware
abstraction of this digital system is called an entity. An entity is modelled using an entity declaration and at
least one architecture body. The entity declaration describes the external view of the entity, for example,
the input and output signal names. The architecture body contains the internal description of the entity, for
example, as a set of interconnected components that represents the structure of the entity, or as a set of
concurrent or sequential statements that represents the behaviour of the entity.
Entity Declaration
The entity declaration specifies the name of the entity being modeled and lists the set of interface
ports. Ports are signals through which the entity communicates with the other models in its external
environment.
The syntax of a VHDL entity declaration is as shown below

entity entity_name IS
port (signal_names:mode signal_type;
signal_names:mode signal_type;
:
:
signal_names:mode signal_type);
end entity_name;

The following section describes the different elements of entity declaration

Entity name: It is an identifier selected by the user to name the entity.
Signal name: It is a list of user selected identifiers to name external interface signals.
Mode: The ports can be declared in four types which specify the signal direction.
Ports can have one of the fallowing modes:
1. in: the value of an input port can only be read within the entity model.
2. out: the value of an output port can only be updated within the entity model, it cannot be read.
3. inout: the value of a bidirectional port can be read and updated within the entity model.
4. buffer: the value of a buffer port can be read and updated within the entity model. However, it differs
from the inout mode in that it cannot have more than one source.

Figure: Half-Adder Circuit.

Here is an example of an entity declaration for the half-adder circuit.

 entity HALF_ADDER is
Port (A, B: in BIT; SUM, CARRY: out BIT);
end HALF_ADDER;

The entity, called HALF_ADDER, has two input ports, A and B (the mode in specifies input port),
and two output ports, SUM and CARRY (the mode out specifies output port). BIT is a predefined type of
the language.
Architecture Body
The internal details of an entity are specified by an architecture body using any of the following
modeling styles:
1. As a set of interconnected components (to represent structure),
2. As a set of concurrent assignment statements (to represent dataflow),
3. As a set of sequential assignment statements (to represent behavior),
4. Any combination of the above three.

The syntax for architecture is given below

Architecture architecture_name of entity_name is
Declarations
Begin
Concurrent statemants;
End architecture_name;

b).Explain the difference in program structure of VHDL and any other procedural language.
Give an example

2. a)Explain the Design Flow of VHDL

DESIGN FLOW:

There are some basic steps for designing any system using HDL. The sequence of these steps is called
the ‗design flow‘. Design flow is shown in below figure
 FRONT END

Hierarchy/blo Compilation Simulation/

ck diagram Coding verification

Synthesis Fitting/place and Timing

route verification

BACK END

Fig: Steps in a VHDL or other HDL-based design flow

Step 1: Hierarchy / Block diagram

The HDL-based design process begins with block diagram. This step obtains the basic approach
of the system. The block diagram of the system is obtained by figuring out the basic building blocks
needed to build the system.
Step 2: coding
The next step is the actual writing of VHDL code for modules, their interfaces, and their internal
details. Since VHDL is a text based language .Any text editor can be used for writing the VHDL code.
However, it is better to use a specialized HDL text editor for the following reasons.
i) The HDL keywords are highlighted automatically.
ii) The indenting is performed automatically.
iii) There are built –in templates for frequently used program structures.
iv) There is built in syntax checking.
v) The compiler can be accessed using a single click.
Step 3: Compilation
After completion of writing code, check code for syntax errors. AVHDL compiler analyzes code
for syntax errors and also checks it for compatibility with other modules. It also crates the internal
information that is needed for a simulator to process design.
Step 4: Simulation / Verification
A VHDL simulator allows defining and applying inputs to design, and to observe its outputs,
without ever having to build the physical circuit. In small projects generate inputs and observe outputs
manually. But for large projects, VHDL gives the ability to create ―text benches ―that automatically apply
inputs and compare them with expected outputs.
Verification means to verify that the circuit works as desired. There are at least two dimensions to
verification. 1. Functional verification 2.Timing verification .In functional verification, study the circuit‘s
logical operation independent of timing considerations, gate delays and other timing parameters are
considered to be zero.
Step 5: Synthesis
In back end first step is synthesis, converting the VHDL description into a set of primitives or
components that can be assembled in the target technology. For example, with PLDs or CPLDs, the
synthesis tool may generate two-level sum-of-product equations
Step 6: Fitting/ Place and Route
In the fitting step, a fitting tool or fitter maps the synthesized primitives or components onto
available device resources. For a PLD or CPLD, this may mean assigning equations to available AND-OR
elements. For an ASIC, it may be finding ways to connect them within the physical constraints of the
ASIC die; this is called the place-and-route process.
Step 7: Timing Verification
In timing verification, study the circuit‘s logical operation including estimated delays, and verify
that the setup, hold, and other timing requirements for sequential devices. The actual circuit delays due to
wire lengths, electrical loading, and other factors can be calculated with reasonable precision.

b) Write the syntax of a VHDL function definition and write a VHDL function for
converting STD_LOGIC_VECTOR to INTEGER.

Functions
Functions are used to describe frequently used sequential algorithms that return a single value. This
value is returned to the calling program using a return statement. The general syntax of a subprogram
specification for a function body is
Function name (parameter-list) retyrn type is
…… -- declarations
begin
…...
…… --sequential statements
……
Return( );
end name;
The parameter-list describes the list of formal parameters for the function. The only mode allowed for the
parameters is mode in.
VHDL function for converting STD_LOGIC_VECTOR to INTEGER.

Function CONV_INTEGER (X:STD_LOGIC_VECTOR) return INTEGER is

Variable RESULT: INTEGER;
Begin
RESULT:=0;
For i in X‘range loop
RESULT:=RESULT*2;
case X(i) is
When ‗0‘ |‘L‘ => null;
When ‗1‘|‘H‘ => RESULT := RESULT+1;
when others => null;
end case;
end loop;
return RESULT;
end CONV_INTEGER;
3. a) Explain the use of packages. Give the syntax and structure of package in VHDL and explain
with an example.

Packages
A package provides a convenient mechanism to store and share declarations that are common across many
design units. A package is represented by
1. Package declaration
2. Package body.
1. Package Declaration
A package declaration contains a set of declarations that may possibly be shared by many design
units. It defines the interface to the package, that is, it defines items that can be made visible to other
design units, The syntax of a package declaration is
package package-name is
package-item-declarations "> These may be:
- subprogram declarations ~ type declarations
- subtype declarations
- constant declarations
- signal declarations
- file declarations
- alias declarations
- component declarations
- attribute declarations
- attribute specifications
- disconnection specifications
- use clauses
end [ package-name ] ;

An example of a package declaration

package ECE is
constant Rise_time:Time:=10ns;
constant fall_time:Time; --deferred constant
variable do,d1,d2:std_logic;
signal e0,e1,e2:std_logic;
type digit is (‗0‘,‘1‘,‘2‘,‘3‘,‘4‘,‘5‘,‘6‘);
subtype middle is digit range ‗2‘ to ‗5‘;
type OP_CODE is (ADD, SUB, MUL, DIV);
component xor1 is
port(g,h:in std_logic;
i:out std_logic);
end component;
function Add_bits(x,y: in bit); return bit is
end ECE;
2. Package body
A package body primarily contains the behavior of the subprograms and the values of the deferred
constants declared in a package declaration. It may contain other declarations, the syntax for a package
body is
 package body package-name is
package-body-item-daclarations "> These are:
- subprogram bodies -- complete constant declarations
- subprogram declarations
- type and subtype declarations
- file and alias declarations
- use clauses
end [ package-name ];

The package name must be the same as the name of its corresponding package declaration. A
package body is not necessary if its associated package declaration does not have any subprogram or
deferred constant declarations. If it‘s associated package declaration have any subprogram or deferred
constant declarations must be write package body.

package body ECE is

constant fall_time:Time:=20ns;
function Add_bits(x,y: in bit); return bit is
variable Result:bit;
begin
Result:= x xor y;
return Result;
end function;
end package body ECE;

b. Give the syntax and structure of procedures in VHDL and explain with an example

Procedures
Procedures allow decomposition of large behaviors into modular sections. Procedure can return
zero or more values using parameters of mode out and inout. The syntax for the subprogram specification
for a procedure body is
procedure procedure-name ( parameter-list )
--Variable declarations
--Constant declarations
--signal declarations
begin
---
--- --sequential statements
End procedure [procedure-name];
The parameter list specifies the list of formal parameters for the procedure. Parameters may be constants,
variables, or signals and their modes may be in, out, or inout.
The syntax of a procedure call statement is
Procedure-name (list-of-actual-parameters);

ADD_BITS(x,y,z);
This statement specifies called to the ADD_BITS procedure.
Ex: Half Adder
--main program
process (a,b,en)
ADD_bits(a,b,en,result,carry); --Procedure call,
end process;
--sub program
Procedure ADD_bits(x,y,en1:in std_logic; --Procedure called
Temp_result, Temp_carry:out std_logic);
begin
if en1=‘1‘ then
Temp_result<= x xor y;
Temp_carry<=x and y;
else
Temp_result, Temp_carry<=‘0‘;
End procedure;

4. (a) Write the syntax of a VHDL component declaration and by making use of component
declaration write a VHDL program for a prime-number detector.
(OR)
Write a VHDL program for the 4-input prime number detector using structural design and
explain

STRUCTURAL MODELING
An entity is modeled as a set of components connected by signals, that is, as a netlist.
The component instantiation statement is the primary mechanism used for describing such a model of an
entity.

Component Declaration
A component declaration declares the name and the interface of a component. The interface
specifies the mode and the type of ports. The syntax of a simple form of component declaration is
component component-name
port ( list-of-interface-ports ) ;
end component;
The component-name may or may not refer to the name of an already ex-isfing entity in a library.
If it does not, it must be explicitly bound to an entity; otherwise, the model cannot be simulated. The list-
of-interface-ports specify the name, mode, and type for each port of the component in a manner similar to
that specified in an entity declaration. "The names of the ports may also be different from the names of the
ports in the entity
Component Instantiation
A component instantiation statement defines a subcomponent of the entity in which it appears. It
associates the signals in the entity with the ports of that subcomponent. A format of a component
instantiation statement is
Component-label: component-name port map ( association-list) ;
The component-label can be any legal identifier and can be considered as the name of the
instance. The component-name must be the name of a component declared earlier using a component
declaration. The association-list associates signals in the entity, called actuals, with the ports of a
component, called locals.
4 – bit prime number detector:
We have to design a circuit to detect the prime numbers from 0 to 15 i.e. 1,2,3,5,7,11,13

Entity prime is
Port (a,b,c,d:in std_logic;
P:out std_logic);
End prime;
Architecture a_prime of prime is
Signal p0,p1,p2,p3:std_logic;
Component and2
Port(a,b:in std_logic
O:out std_logic);
End component;
Componemt and3
Port(a,b,c:in std_logic;
O:out std_logic);
End component;
Component or4
Port(a,b,c,d:in std_logic
O:out std_logic);
End component;
Begin
A1:and2 portmap(not a,d,p0);
A2:and3 portmap(not a,not b,c,p1);
A3:and3 portmap(not b,c,d,p2);
A4:and3 portmap(b,not c,d,p3);
O:or4 portmap(p0,p1,p2,p3,p);
End a_prime;

(b) Write the syntax of a VHDL process statement and by making use of process statements write
a process-based dataflow VHDL architecture for the prime-number detector
(OR)
Write a VHDL program for the prime-number detector of 4-bit input using behavioural
modeling and explain the flow using logic circuit.
Process Statement
A process statement contains sequential statements that describe the functionality of a portion of an
entity in sequential terms. The syntax of a process statement is

[ process-label: ] process [ ( sensitivity-list ) ]

[ process-item-declarations ]
begin
sequential-statements; these are ->
variable-assignment-statement
signal-assignment-statement
wait-statement
if-statement
case-statement
loop-statement
null-statement
exit-statement
next-statement
procedure-call-statement
return-statement.
end process [ process-label] ;

A set of signals that the process is sensitive to is defined by the sensitivity list. In other words, each
time an event occurs on any of the signals in the sensitivity list, the sequential statements within the
process are executed in a sequential order, that is, in the order in which they appear. The process then
suspends after executing the last sequential statement and waits for another event to occur on a signal in
the sensitivity list.
EX:
entity prime is
port(a:in std_logic_vector(3 downto 0);
f:our std_logic_vector);
end prime;
arichtecture a_prime of prime is
begin
process(a)
begin
case a is
when ―0001‖=>f<=‘1‘,
when ―0010‖=>f<=‘1‘,
when ―0011‖=>f<=‘1‘,
 when ―0101‖=>f<=‘1‘,
when ―0111‖=>f<=‘1‘,
when ―1011‖=>f<=‘1‘,
when ―1101‖=>f<=‘1‘,
when others f<=‘0‘;
end case;
end process;
end a_prime;

5. a)Explain data flow design elements of VHDL and write VHDL program for 4 input prime
number detector
DATAFLOW MODELING
Concurrent Signal Assignment Statement
One of the primary mechanisms for modeling the dataflow behavior of an entity is by using the concurrent
signal assignment statement.
Conditional Signal Assignment Statement
The conditional signal assignment statement selects different values for the target signal based on
the specified, possibly different, conditions (it is like an if statement). A typical syntax for this statement is

Target - signal <= [ waveform-elements when condition else ]

[ waveform-elements when condition else ]
. . . ………..
……………
waveform-elements ;

Whenever an event occurs on a signal used either in any of the waveform expressions (waveform
expression is the value expression in a waveform element) or in any of the conditions, the conditional
signal assignment statement is executed by evaluating the conditions one at a time. For the first true
condition found, the corresponding value (or values) of the waveform is scheduled to be assigned to the
target signal.
Selected Signal Assignment Statement
The selected signal assignment statement selects different values for a target signal based on the,
value of a select expression (it is like a case statement). A typical syntax for this statement is
with expression select —This is the select expression.
target-signal <= waveform-elements when choices,
waveform-elements when choices,
… ……….
………......
waveform-elements when choices ;

Whenever an event occurs on a signal in the select expression or on any signal used in any of the
waveform expressions, the statement is executed. Based on the value of the select expression that matches
the choice value specified, the value (or values) of the corresponding waveform is scheduled to be assigned
to the target signal. All possible values of the select expression must be covered by the choices that are
specified not more than once.
EX:
entity prime is
port(a:in std_logic_vector(3 downto 0);
f:our std_logic_vector);
end prime;
architecture a_prime of prime is
begin
with a select
f<= ‗1‘ when ―0001‖,
‗1‘ when ―0010‖,
‗1‘ when ―0011‖,
‗1‘ when ―0101‖|‖0111‖|‖1011‖|‖1101‖,
‗0‘ when others;;
End a_prime;
b). Explain the Behavioural Model of VHDL
1. Behavioral Modeling

The behavior of the entity is expressed using sequentially executed, procedural type code that is
very similar in syntax and semantics to that of a high-level programming language like C or Pascal. A
process statement is the primary mechanism used to model the procedural type behavior of an entity.

Process Statement
A process statement contains sequential statements that describe the functionality of a portion of an
entity in sequential terms. The syntax of a process statement is

[ process-label: ] process [ ( sensitivity-list ) ]

[ process-item-declarations ]
begin
sequential-statements; these are ->
variable-assignment-statement
signal-assignment-statement
wait-statement
if-statement
case-statement
loop-statement
null-statement
exit-statement
next-statement
procedure-call-statement
return-statement.
end process [ process-label] ;

A set of signals that the process is sensitive to is defined by the sensitivity list. In other words, each
time an event occurs on any of the signals in the sensitivity list, the sequential statements within the
process are executed in a sequential order, that is, in the order in which they appear (similar to statements
in a high-level programming language like C or Pascal). The process then suspends after executing the last
sequential statement and waits for another event to occur on a signal in the sensitivity list.
Variable Assignment Statement
Variables can be declared and used inside a process statement. A variable is assigned a value using
the variable assignment statement that typically has the form
variable-object := expression ;
Signal Assignment Statement
Signals are assigned values using a signal assignment statement, the simplest form of a signal
assignment statement is
signal-object < = expression [ after delay-value ] ;
Wait Statement
The wait statement provides an alternate way to suspend the execution of a process. There are three
basic forms of the wait statement.

wait on sensitivity-list;
wait until boolean-expression ;
wait for time-expression ;

If Statement
An if statement selects a sequence of statements for execution based on the value of a condition.
The condition can be any expression that evaluates to a boolean value. The general form of an if statement
is

if boolean-expression then
sequential-statements
[ elsif boolean-expression then -- elsif clause; if stmt can have 0 or 1
sequential-statements ] -- more elsif clauses.
[ else -- else clause.
sequential-statements ]
end if;

The if statement is executed by checking each condition sequentially until the first true condition is found;
then, the set of sequential statements associated with this condition is executed. The if statement can have
zero or more elsif clauses and an optional else clause. An if statement is also a sequential statement.
Case Statement
The format of a case statement is

case expression is
when choices => sequential-statements -- branch #1
when choices => sequential-statements -- branch #2
-- Can have any number of branches.
[ when others => sequential-statements ] -- last branch
end case;

The case statement selects one of the branches for execution based on the value of the expression.
Choices may be expressed as single values, as a range of values, by using I (vertical bar: represents an
"or"), or by using the others clause(‗when others‖). All possible values of the expression must be covered
in the case statement exactly once.
Null Statement
The statement null; is a sequential statement that does not cause any action to take place and
execution continues with the next statement.

Loop Statement
A loop statement is used to iterate through a set of sequential statements. The syntax of a loop
statement is

[ loop-label : ] iteration-scheme loop

sequential-statements
end loop [ loop-label ] ;
1) For :
Syn: for identifier in range
2)While:
Syn : While bollean_expression loop
Exit Statement
The exit statement is a sequential statement that can be used only inside a loop. It causes execution
to jump out of the innermost loop or the loop whose label is specified. The syntax for an exit statement is

exit [ loop-label] [ when condition ] :

Next statement
The next statements results in skipping the remaining statements in the current iteration of the
specified loop, execution resumes with the first statement in the next iteration of the loop, if no loop label
is specified the inner most is assumed.

Syn:
Next [loop_label] [when condiotion];
6. a) Explain with example the syntax and function of the following VHDL statements:
I) IF, ELSE and ELSE IF statements.
II) CASE statement. III) LOOP statement
If Statement
An if statement selects a sequence of statements for execution based on the value of a condition.
The condition can be any expression that evaluates to a boolean value. The general form of an if statement
is
if boolean-expression then
sequential-statements
[ elsif boolean-expression then -- elsif clause; if stmt can have 0 or 1
sequential-statements ] -- more elsif clauses.
[ else -- else clause.
sequential-statements ]
end if;

The if statement is executed by checking each condition sequentially until the first true condition is found;
then, the set of sequential statements associated with this condition is executed. The if statement can have
zero or more elsif clauses and an optional else clause. An if statement is also a sequential statement.

if SUM <= 100 then -- This is a less-than-or-equal-to operator.

SUM := SUM+10;
end if;

example

If a>b then
a<=a+b;
elsif b>c then
b<=b+c;
else
c<=a-c;
end if;

Case Statement
The format of a case statement is

case expression is
when choices => sequential-statements -- branch #1
when choices => sequential-statements -- branch #2
-- Can have any number of branches.
[ when others => sequential-statements ] -- last branch
end case;
 The case statement selects one of the branches for execution based on the value of the expression.
Choices may be expressed as single values, as a range of values, by using I (vertical bar: represents an
"or"), or by using the others clause(‗when others‖). All possible values of the expression must be covered
in the case statement exactly once.
type WEEK_DAY is (MON, TUE, WED, THU, FRI, SAT, SUN);
type DOLLARS is range 0 to 10;
variable DAY: WEEK_DAY;
variable POCKET_MONEY: DOLLARS
case DAY is
when TUE => POCKET_MONEY := 6; -- branch 1
when MON I WED => POCKET_MONEY := 2; -- branch 2
when FRI to SUN => POCKET_MONEY := 7; -- branch 3
when others => POCKET_MONEY := 0; -- branch 4
end case;
Branch 2 is chosen if DAY has the value of either MON or WED. Branch 3 covers the values FRI,
SAT, and SUN, while branch 4 covers the remaining value, THU. The case statement is also a sequential
statement

Loop Statement
A loop statement is used to iterate through a set of sequential statements. The syntax of a loop
statement is

[ loop-label : ] iteration-scheme loop

sequential-statements
end loop [ loop-label ] ;

1) For :
Syn: for identifier in range

An example of this iteration scheme is

FACTORIAL: = 1;
for i in 2 to N loop
FACTORIAL := FACTORIAL * i;
end loop;

2) While:
Syn : While bollean_expression loop
Ex:
j:=1,fact:=1;
while j< n loop

fact:= fact *j
j=j+1;;
end loop;
3) Loop:
Ex:
J:=1,fact:=1;
L2:Loop
Fact:=fact*j;
J=j+1;
Exit when j>n;
End loop L2;