LOGIC CIRCUIT DESIGN-CCW

1) What is the octal equivalent of (F3B)₁₆?

A. 178543
B. 172101
C. 171661
D. 171541

2) Convert (312)₈ to decimal form:

A. 201

B. 202₁₀

C. 203₁₀
D. 204₁₀
3) The excess-3 code of decimal 7 is:

A. 1001
B. 1100
C. 1011
D. 1010

4) The decimal equivalent of 2's complement representation 1100101 is:

A. +37
B. -31
C. +27
D. -27

5) (E7F6)₁₆ = ( )₁₀

A. 59382
B. 60000
C. 9362
D. 382

6) (1100110)₂ = ( )₈
A. 242
B. 446
C. 146
 D. 58

7) The decimal equivalent of the binary number (1011.101)₂ is:

A. 11.5
B. 11.625
C. 10.625
D. 10.5
8) In sign-magnitude numbers:

A. msb always 1
B. msb 0 stands for the positive numbers
C. msb 0 stands for the negative numbers
D. msb 1 stand for the positive numbers

9) Which of the following is the smallest 4-bit negative number stored in its 2's complement
representation?
A. 1000
B. 0000
C. 1111
D. 0111
10) The 1's complement of the binary number (101100)2 is:
A. (001100)2
B. (010011)2
C. (101101)2
D. (110011)2

11) The code used to reduce the error due to ambiguity in reading of a binary optical encoder is
A. Octal code
B. Excess-3 code
C. Gray code
D. BCD code

12) Which of the following is the Excess-3 code form of decimal (215)?

A. (0101 0100 1000)

B. (1101 1100 1010)
C. (0101 0101 1001)
D. (0111 0110 1100)
13)The IEEE 754 single precision representation has:

A. 8 exponent bits, 23 mantissa bits

B. 10 exponent bits, 20 mantissa bits
C. 12 exponent bits, 24 mantissa bits
D. 6 exponent bits, 18 mantissa bits

14) A 7-bit message has even parity. Which of the following messages contains an error?

A. 1010110
B. 1101001
C. 0110100
D. 1111110

15) The 8-bit two’s complement representation of (-18) is:

A. 11101110
B. 11110010
C. 10010010
D. 11010010

16)What is the result of rounding the floating-point number 3.14159 to 4 decimal places?

A. 3.1416
B. 3.1415
C. 3.1414
D. 3.1413

17) How many parity bits are required to detect and correct 1-bit errors in an 8-bit data word
using Hamming Code?

A. 3
B. 4
C. 5
D. 6

18) A 7-bit data word needs odd parity. What parity bit should be added to 1011001?

A. 1
B. 0
C. 10
D. None of the above
19)The binary equivalent of (3A7)₁₆ is:

A. 111010011

B. 101101111

C. 111010111

D. 110101111

20) There are __ standard ASCII codes.

A. 32

B. 64

C. 96

D. 128

21.Which of the following gates is known as universal gates?

A. NOT
B. NAND,
C. Ex-Nor
D. AND.
22. A.A’____?

A. 0
B. 1
C. A
D. A
23.if A and Bare the Boolean variables, then what is (A+B)(A+B bar)?

A. B,
B. A
C. A-B
D. AB
24.Which law indicates AB + BC + A’C = AB + A’C.

A. Associative law
B. Redundant law
C. Commutative law
D. Absorption law
25.What is the duality of x.0 =0?

A. X.1=1
B. X+1=1
C. X.X=X
D. X.0=0
26. What is the Canonical Sum of Products (SOP) form?

A. AND-ing all the minterms

B. OR-ing all the maxterms
C. AND-ing all the literals in a function
D. OR-ing all the minterms of a function

27.How many cells does a 3-variable Karnaugh Map (K-map) have?

A. 4
B. 8
C. 16
D. 32
28. In Karnaugh Map (K-map), adjacent cells differ by how many bits?

A. 1 bit
B. 2 bits
C. 3 bits
D. None of the above
29. What is the default data type of signals in Verilog

A. wire
B. reg
C. bit
D. integer
30.Which Verilog gate implementation is correct for a NAND gate

A. assign Y = A & B;
B. assign Y = ~(A & B);
C. assign Y = A | B;
D. assign Y = ~(A | B);
31. In Verilog, which of the following is used to define an OR gate?

A. assign Y = A & B;
B. assign Y = A | B;
C. assign Y = ~(A & B);
D. assign Y = ~(A | B);
32. What is the Product of Sums (POS) representation in Boolean Algebra?

A. AND-ing the maxterms

B. OR-ing the minterms
C. AND-ing the minterms
D. OR-ing the maxterms
33. The function F(A,B,C) = Σ(1,2,5,6) in SOP form has which minterms?

A. m1, m2, m5, m6

B. m0, m3, m4, m7
C. m1, m2, m4, m7
D. None of the above
34.Which of the following Verilog statements implements a 2-input XOR gate?

A. assign Y = A ^ B;
B. assign Y = A & B;
C. assign Y = A | B;
D. assign Y = ~(A & B);
35.Which logic gate is represented by the Boolean equation (A + B)’?

A. AND
B. NAND
C. NOR
D. XNOR
36. How many fundamental logic gates are there?

A. 2
B. 3
C. 4
D. 5
37.The Boolean equation A + AB simplifies to:

A. A
B. B
 C. AB
D. A + B
38.Which of the following terms can be minimized in a K-map by combining adjacent 1s?

A. Minterms
B. Maxterms
C. Both
D. None
39. How many NAND gates are required to implement an XOR gate?

A. 2
B. 3
C. 4
D. 5
40. How many outputs will be generated in a D/A converter having four inputs?
A. sixteen
B. fifteen
C. twenty
D. none of these
41. What is the primary function of a comparator in a combinatorial logic circuit?
42. In a 4-to-1 multiplexer, how many select lines are required?
D) 1
43. Which of the following is a characteristic of a demultiplexer?
A. It takes multiple inputs and produces a single output
B. It routes a single input to one of many outputs
C. It performs arithmetic operations on binary inputs
D. It converts analog signals to digital
44. Which logic gate is used in the construction of a full adder?
A. AND
B. OR
C. XOR
D. D) All of the above
45. In which situation would you use a BCD (Binary Coded Decimal) adder?
A. Adding two binary numbers
 B. Adding two decimal numbers and outputting the result in binary form
C. Adding two decimal numbers and outputting the result in decimal form
D. None of the above
46. Which of the following is true for a half adder?
A. It can add two 3-bit numbers
B. It produces a sum and carry output
C. It only produces a sum output
D. It is used for subtraction
47. Which of the following is the main function of an encoder in combinational logic?
A. Convert a binary number to a decimal number
B. Convert a decimal number to a binary number
C. Convert multiple inputs to a binary code representing the active input
D. Convert an input binary number to a Gray code
48. What is the primary role of a decoder in a digital system?
A. 4
49. Which of the following circuits can be used to add multiple bits in parallel?
A. Full Adder
B. Serial Adder
C. Parallel Adder
D. Half Adder
50. In a 4-bit comparator, what is the output when the two inputs are equal?
A. 1
B. 0
C. High
D. Low
51. Which gate is required to create a NAND gate from basic gates?
A. OR and NOT gates
B. AND and NOT gates
C. XOR and NOT gates
D. NOR and NOT gates
52. In a 2-to-4 line decoder, what is the maximum number of output lines that can be HIGH
simultaneously?
A. 1
 B. 2
C. 3
D. 4
53. What is the output of a 1-bit full adder when the inputs are A=1, B=1, and Carry-in=1?\
A. Sum = 0, Carry-out = 1
B. Sum = 1, Carry-out = 1
C. Sum = 0, Carry-out = 0
D. Sum = 1, Carry-out = 0
54. Which of the following is the primary role of an AND gate?
A. Produces an output of 1 only if all inputs are 1
B. Produces an output of 0 only if one input is 1
C. Produces an output of 0 only if all inputs are 0
D. Inverts the input signal
55. Which of the following components is needed to create a binary-to-decimal encoder?
A. Decoder
B. Multiplexer
C. Comparator
D. Priority encoder
56. Which logic gate combination will produce the same result as a NAND gate?
A. AND + NOT
B. OR + NOT
C. XOR + NOT
D. NOR + NOT
57. Which of the following gates can be used to build a half adder circuit?
A. AND gate and OR gate
B. XOR gate and AND gate
C. NAND gate and NOR gate
D. Only OR gate
58. Which of the following is NOT a combinational logic system?
A. Multiplexer
B. Full adder
C. Flip-flop
D. Decoder
59. What is the main difference between a half adder and a full adder?
A. A full adder adds two bits, while a half adder adds three bits.
B. A half adder only produces a sum, while a full adder also produces a carry-out.
C. A full adder can handle carry-in bits, while a half adder cannot.
D. There is no difference between a half adder and a full adder.

60. What is the output of a 2-input XOR gate when both inputs are the same?
A. 0
B. 1
C. High
D. Low
61. In a shift register with parallel load, what operation can be performed?

A) Only shifting left

B) Only shifting right
C) Only parallel loading
D) Both shifting and parallel loading

62. A Ring Counter with N flip-flops will have how many states?

A) N
B) 2^N
C) N/2
D) 2N

63. In a Johnson Counter, the number of unique states is:

A) N
B) 2N
C) 2^N
D) N/2

64. Which type of counter changes state in response to a clock signal applied to all flip-flops
simultaneously?
 A) Asynchronous Counter
B) Synchronous Counter
C) Ripple Counter
D) Mod-N Counter

65. What is the modulus of a counter that cycles through 10 states?

A) 2
B) 8
C) 10
D) 16

66. What is the main disadvantage of an asynchronous counter?

A) High power consumption

B) Propagation delay
C) Requires a large number of flip-flops
D) Low-speed operation

67. How many flip-flops are required to construct a MOD-16 counter?

A) 2
B) 4
C) 8
D) 16

68. What is the key difference between a Johnson Counter and a Ring Counter?

A) Ring Counter uses feedback, Johnson Counter does not

B) Johnson Counter has twice the states of a Ring Counter
C) Johnson Counter uses more flip-flops than a Ring Counter
D) Ring Counter operates asynchronously

69. In a PISO (Parallel-In, Serial-Out) shift register, how is data shifted out?
 A) One bit per clock cycle
B) All bits at once
C) Data is not shifted out
D) It depends on the mode selection

70. Which of the following flip-flops can be converted into any other type of flip-flop?

A) D Flip-Flop
B) JK Flip-Flop
C) SR Flip-Flop
D) T Flip-Flop

71. What is the invalid state in an SR flip-flop?

A) S = 0, R = 0

B) S = 1, R = 0

C) S = 0, R = 1

D) S = 1, R = 1

72. In a JK flip-flop, when both J and K inputs are 1, what happens on the next clock edge?

A) Output remains the same

B) Output toggles
C) Output resets
D) Output is set

73. How does a Master-Slave JK Flip-Flop work?

A) It triggers on both edges of the clock

B) Master stores the input, and the slave updates on the next clock edge
C) It operates asynchronously
D) It cannot toggle like a normal JK flip-flop

74. Which type of flip-flop responds only to the clock's rising or falling edge?
 A) Synchronous Flip-Flop
B) Master-Slave Flip-Flop
C) Level-Triggered Flip-Flop
D) Edge-Triggered Flip-Flop

75. The characteristic equation of a D Flip-Flop is:

A) Q(next) = Q + D
B) Q(next) = D
C) Q(next) = JQ’ + K’Q
D) Q(next) = S + RQ

76. How many flip-flops are needed to construct a Mod-8 ripple counter?

A) 2
B) 3
C) 4
D) 8

77. What is the main difference between a Synchronous and Ripple Counter?

A) Synchronous counters operate faster since all flip-flops trigger together

B) Ripple counters are faster than synchronous counters

C) Ripple counters do not use flip-flops

D) Synchronous counters have more delay than ripple counters

78. A 4-bit Johnson Counter will have how many unique states?

A) 4
B) 8
C) 16
D) 10

79. Which shift register shifts data only in one direction, either left or right?
 A) SISO (Serial-In, Serial-Out)
B) PIPO (Parallel-In, Parallel-Out)
C) PISO (Parallel-In, Serial-Out)
D) Bidirectional Shift Register

80. Which shift register takes parallel input and provides parallel output?

A) SISO
B) PIPO
C) PISO
D) SIPO

81.Which has the lowest propagation delay?

A. (a)ECL
B. (b)TTL
C. (c)CMOS
D. (d)PMOS

82.The full form of the abbreviations of TTL and CMOS in reference to logic families are

A. (a)Transistor-transistor logic and chip metal oxide semiconductor

B. (b)Tristate transistor logic and chip metal oxide semiconductor
C. (c)Transistor-transistor logic and complementary metal oxide semiconductor
D. (d)Tristate transistor logic and complementary metal oxide semiconductor

83.The output of the 74 series of TTL gates is taken from a BJT is

A. (a)Totem pole and common collector configuration

B. (b)Either totem pole or open collector configuration
C. (c)Common base configuration
D. (d)Common collector configuration

84.The typical quiescent power dissipation of low power CMOS unit is

 A. 0.5nW
B. 0.5mW
C. (c)1mW
D. (d)2nW

85The noise margin of a TTL gate is about

A. 0.2V
B. 0.4V
C. 0.8V
D. 0.6V

86.As compared to TTL, CMOS logic has

A. smaller physical size

B. high power dissipation
C. high speed of operation
D. none of the above

87.The main advantage of CMOS is its

A. (a)High power rating

B. (b)small signal operation
C. (c)switching capability
D. (d)low power consumption

88.Which of the following IC logic families has the highest fan-out?

A. (a)TTL
B. (b)CMOS
C. (c)ECL
D. (d)Schottky TTL

89.An acceptable voltage range of a logic 0 for TTL

A. 0 to 0.8V
 B. (b) 0 to 1.5V
C. 2 to 5V
D. 3.5 to 5

90.Which character of IC in digital circuits represent a function of the switching time of a

particular transistor?

A. (a)fan-out
B. (b)fan-in
C. (c)propagation delay
D. (d)power dissipation

91.Which of the following majorly determines the number of emitters in a TTL digital

circuit?

A. (a)fan-in
B. (b)fan-out
C. (c)propagation delay
D. (d)noise immunity

92.How must the output of a gate in a TTL digital circuit acts when it is HIGH?

A. (a)acts as a voltage source

B. (b)acts as a current sink
C. (c)acts as a current source
D. (d)acts as a voltage sink

93.Which of the following is the typical characteristics of a TTL NAND gate?

A. (a)high noise margin

B. (b)low input impedance
C. (c)high power consumption
D. d)slow switching time
94.What is the primary function of the noise margin in logic gates?

A. (a)To provide resistance against voltage fluctuations

B. (b)To ensure the output is properly recognized by other gates
C. (c)To improve signal propagation
D. (d)To reduce power consumption

95.How does the transition time of a logic gate impact its performance?

A. shorter transition time reduces noise

B. longertransitiontimeleadstofasterswitching
C. shorter transition time leads to faster switching
D. longer transition time reduces power consumption

96.Which of the following is a characteristic feature of a TTL NAND gate’s electrical

behaviour?

A. (a)The output current is high when the input is low

B. (b)The output is low when both inputs are high
C. (c)The gate consumes a very little power
D. (d)The output is high when both inputs are low

97.What is the primary role of a pull-up resistor in a TTL logic gate circuit?

A. To pull the input to a logic low when not active

B. To prevent a floating output state
C. To limit the output current
D. To store charge at the input

98.What is the fan-out of a logic gate?

A. The maximum current a gate can output

B. The number of gates that can be connected to the output
C. The voltage drop across the gate
D. The number of inputs a gate can accept
100.In a CMOS inverter, when the input is high, the output will be

A. high
B. low
C. undefined
D. oscillating

101.In ECL (Emitter Coupled Logic), the output state is determined by

A. voltage levels
B. current levels
C. transistor switching
D. logic level inversion

102.What characteristic will a TTL digital circuit posses due to its multi-emitter transistor?

A. (a)low capacitance
B. (b)high capacitance
C. (c)low inductance
D. (d)high inductance

103.How must the output of a gate act when it is LOW in a TTL circuit?

A. (a)acts as a voltage source

B. (b)acts as current source
C. (c)acts as a voltage sink
D. (d)acts as a current sink

104.Which of the following options is a Current-Mode logic used in digital circuits?

A. (a)TTL
B. (b)RTL
C. (c)ECL
D. (d)IIC

105.What will a TTL circuit possess due to the presence of multi-emitter transistor?
 A. (a)smaller resistance
B. (b)larger area
C. (c)smaller area
D. (d)larger resistance

106.TTL is a class of digital circuits built from

A. (a)JFET only
B. (b)BJT
C. (c)Resistors
D. (d)BJT and resistors

107.What is the propagation delay in a logic circuit?

A. (a)time taken for the output to change state

B. (b)time taken for the input to change state
C. (c)time taken for the gate to switch on
D. (d)the time taken for the gate to switch off

108.What is the power-delay product of a logic gate?

A. (a)product of consumption and propagation delay

B. (b)sum of power consumption and propagation delay
C. (c)difference of power consumption and propagation delay
D. (d)ratio of power consumption and propagation delay

109.What is the main disadvantage of TTL compared to CMOS?

A. (a)lower noise margin

B. (b)higher power consumption
C. (c)slower speed
D. (d)lower fan-out

110.What is the structure of a CMOS NOR gate in terms of a transistor arrangement?

A. (a)PMOS in series, NMOS in parallel

B. (b)PMOS in parallel, NMOS in series
C. (c)Both PMOS and NMOS in series
D. (d)Both PMOS and NMOS in parallel
 Answer key
1. c

2. b

3. (d)
4. (d)
5. (a)
6. (c)
7. (b)

8. (b)

9. (a)

10.(b)
11.(c)
12.(a)

13.(a)

14.(b)
15.(a)
16.(a)
17.(b)
18.(b)

19.(c)

20.(d)
21.B
22.A
23.B
24.B
25.B
26.D
27.B
28.A
29.A
30.B
31.B
32.A
33.A
34.A
35.C
36.B
37.A
38.A
39.D
40.A
41.B
42.A
43.B
44.D
45.C
46.B
47.C
48.B
49.C
50.A
51.B
52.A
53.A
54.A
55.D
56.A
57.B
58.C
59.C
60. A
61.D

62.A
63.B

64.B

65.C

66.B

67.B

68.B

69.A

70.B

71.D

72.B

73.B

74.D

75.B

76.B

77.A

78.B

79.A

80.B

81.H

82.(A)
83.(C)
84.(B)
85.(D)
86.(B)
87.(A)
88.(D)
89.(B)
90.(A)
91.(D)
92.(A)
93.(C)
94.(C)
95.(B)
96.(C)
97.(B)
98.(B)
99.(B)
100 (B)
101 (B)
102 (A)
103 (D)
104 (C
105 (C)
106 (D)
107 (A)
108 (A)
109 (B)
110 (A)

\
 Solutions

1) Convert each hexadecimal number (F3B)₁₆ to binary:

F = 1111

3 = 0011

B = 1011

1 = 0001

Make a group of binary numbers into sets of 3:

1111 001 110 110 001

Add zeros to get a complete group of 3:

001 111 001 110 110 001

Combine these octal numbers:

001 → 1

111 → 7

001 →

1 110 →

110 → 6

001 → 1

The octal equivalent of (F3B)₁₆ is 171661.

2) Octal-to-decimal conversion is done by multiplying 8 to the power of the

base along with the value at the index position:

(312)₈ = 3 × 8² + 1 × 8¹ + 2 × 8⁰
= 192 + 8 + 2 = (202)₁₀

3) Decimal digit = 7

Adding 3 to the above, we get:

7 + 3 = 10

Convert 10₁₀ to binary:

10 ÷ 2 = 5 remainder 0

5÷2=2

remainder 1 2 ÷ 2

= 1 remainder 0

1 ÷ 2 = 0 remainder 1

Thus, (10)₁₀ = (1010)₂.

The excess-3 code of 7 is 1010.

4) Given binary: 1100101 Find the 1's complement:

1's complement: 0011010
Add 1 to the 1's complement:
0011010
+1

0011011

2's complement: 001101

Convert to decimal form:
(1x2⁰)+(1x2¹)+(1x2³)+(1x2⁴)
=1+2+8+16=27
Since it is 2's complement, it is a negative answer.
So, 2's complement of 1100101 is -27.

5) E = 14
F = 15

(E7F6)₁₆ = (14x16³)+(7x16²)+(15x16¹)+(6x16⁰)= (59382) ₁₀

6) Given binary, 1100110

Since octal, split into group of 3-bit:
1 100 110
Add zero to get group of 3:
001 100 110
Corresponding decimal numbers:
001 → 1
100 → 4
110 → 6
So, the octal form of 1100110 is (146)₈.

7) (1011.101) ₂ = (1x2³)+(0x2²)+(1x2¹)+(1x2⁰)+(1x2-¹)+(1x-²)+(1x2-³)
=8+0+2+1+0.5+0+0.125
=11.625

10)The 1's complement of the given binary digit will be:

 (101100) → (010011)

12) Decimal number → (215) ₁₀

Equivalent binary number → (0010 0001 0101) ₂
If we add 0011 to each four bit group in binary code
Then,
0010 0001 0101
+ 0011 0011 0011

0101 0100 1000

Therefore, the Excess-3 code form of decimal (215) will be (0101 0100 1000)
₂

14) Even parity means the number of 1s should be even:

1010110 → 4 ones
1101001 → 3 ones (Error)
0110100 → 2 ones
1111110 → 6 ones

15) +18 in Binary (8-bit): 00010010

Take 1’s complement: 11101101
Add 1: 11101110

16) Identify the first four decimal places: 3.14159 → 3.1415

Look at the next digit (the fifth decimal place): 9

Since 9 is greater than 5, round up the last digit in the four-decimal sequence
(5) by 1.
Thus, 3.1415 becomes 3.1416 after rounding.

17) For n data bits, number of parity bits (p) is given by:

2^p >= n+p+1

For 8-bit data, solving 2^p >= 8+p+1 gives p = 4.

18) Number of 1s in 1011001 = 4 (Even)

To maintain odd parity, add 1 → Answer: 1

19) Convert each hex digit to 4-bit binary:

(3A7)₁₆ =(0011 1010 0111) ₂ = (111010111) ₂

20) No

21) Because it can be used to implement any Boolean function, including

all basic logic gates (AND, OR, and NOT)
22) AND laws
23) A·A + A B + B A + B B’
A + A B + A B’
A+AB+AB’
A(1+B)+AB’
A+AB’
A(1+B’)
A×1
A
24) Redundant
25) X+1=1
Applying the Duality Principle:
Replace AND (·) with OR (+)
Replace 0 with 1
26) Canonical SOP expresses a Boolean function as a sum (OR) of
minterms (AND terms where all variables appear in true or complemented
form)
27) A K-map has 2ⁿ cells, where n is the number of variables. For a 3-
variable K-map, the number of cells is 2³ = 8.
28) Adjacent cells in a K-map represent minterms differing in only one
variable, meaning only one bit change occurs between them.
29) Wire is the default data type in Verilog for connecting components
unless otherwise declared as reg.
30) A NAND gate is the negation of AND. In Verilog, the bitwise AND
(&) is used first, followed by negation (~) to get NAND.
31) The | operator in Verilog represents the bitwise OR operation, which
performs logical OR on individual bits.
32) POS represents a function as a Product (AND) of Sums (OR terms,
also called maxterms). This is the dual of SOP.
33) The Σ(m1, m2, m5, m6) notation represents a Sum of Products
(SOP) where minterms 1, 2, 5, and 6 are used.
34) The bitwise XOR operator (^) is used in Verilog to implement an
XOR gate.
35) (A + B)’ represents the NOR gate, which is the negation of OR.
36) The three fundamental gates are AND, OR, and NOT. Other gates
like NAND, NOR, XOR, and XNOR are derived from these.
37) Using the Absorption Theorem:
A + AB = A(1 + B) = A(1) = A.
38) In SOP (Sum of Products) form, adjacent 1s in a K-map are
combined to form simplified minterms.
39) An XOR gate can be implemented using 5 NAND gates following

A ⊕ B = (A NAND (A NAND B)) NAND (B NAND (A NAND B)).

the Boolean equation:
40) 16
41) 1. B) Compare two binary numbers and determine if one is greater,

less than, or equal to the other

A comparator compares two binary values and produces an output

indicating which value is greater, or if they are equal. It is commonly used

in circuits for sorting, decision making, and control systems.

42) 2. A) 2

A 4-to-1 multiplexer selects one of four data inputs based on the values of

2 select lines. The number of select lines required for a multiplexer is

calculated using the formula ,Select lines=log2(Number of inputs), which

in this case is log2(4)=2.

43) 3. B) It routes a single input to one of many outputs

A demultiplexer (DEMUX) takes a single input and routes it to one of

many outputs based on control or selection lines. It's essentially the reverse

operation of a multiplexer.

44) 4. D) All of the above

A full adder can be constructed using AND, OR, and XOR gates. The sum

output is derived from the XOR gates, while the carry output is derived

from combinations of AND and OR gates.

45) 5. C) Adding two decimal numbers and outputting the result in

decimal form

A BCD adder is designed to add two decimal numbers represented in

binary form (BCD format) and output the result in BCD. It handles carry-

over between decimal digits properly.

46) 6. B) It produces a sum and carry output

A half adder adds two single-bit binary numbers and produces a sum and

carry output. It does not handle carry-in values, which is why a full adder

is used for adding multiple bits.

47) C) Convert multiple inputs to a binary code representing the active

input

An encoder takes multiple input lines and produces a binary output

corresponding to the active input. For example, a 4-to-2 encoder has 4

inputs and 2 outputs, where the output is a binary code indicating which

input is active.

48) B) To convert a binary input into a set of outputs based on the input

code

A decoder takes a binary input and activates one specific output line

corresponding to the binary value of the input. It’s commonly used in

systems that require addressing, such as memory units.

49) 9. c) Parallel Adder

A parallel adder adds two binary numbers bit by bit in parallel, whereas a

serial adder adds bits one at a time.

50) 10. a) 1

A comparator outputs a HIGH (1) when the inputs are equal.

51) 11. b) AND and NOT gates

A NAND gate can be created by applying a NOT operation to the output

of an AND gate.

52) 12. a) 1

A 2-to-4 decoder outputs a HIGH on only one of the four lines at a time,

based on the 2-bit input.

53) a) Sum = 0, Carry-out = 1

For inputs A=1, B=1, and Carry-in=1, the sum will be 0, and the carry-out

will be 1.

54) a) Produces an output of 1 only if all inputs are 1

An AND gate produces a HIGH output (1) only when all inputs are HIGH

(1).

55) d) Priority encoder

A priority encoder converts binary inputs into a corresponding binary

code, prioritizing the highest active input.

56) 16. a) AND + NOT

A NAND gate is equivalent to an AND gate followed by a NOT gate (i.e.,

an inverted AND gate).

57) 17. b) XOR gate and AND gate

A half adder is constructed using an XOR gate for the sum and an AND

gate for the carry output.

58) 18. C) Flip-flop

A flip-flop is a sequential logic element, not a combinational one.

59) 19. C) A full adder can handle carry-in bits, while a half adder

cannot.

A half adder adds two bits and produces a sum and a carry-out, while a full

adder also includes a carry-in bit.

60) 20. a) 0 An XOR gate produces a HIGH (1) output only when the

inputs are different. If both inputs are the same, the output is LOW (0).

61) Both shifting and parallel loading

62) N

63) 2N

64) Synchronous Counter

65) 10

66) Propagation delay

67) 4

68) B) Johnson Counter has twice the states of a Ring Counter

69) One bit per clock cycle

70) JK Flip-Flop

71) S = 1, R = 1

72) Output toggles

73) Master stores the input, and the slave updates on the next clock edge

74) Edge-Triggered Flip-Flop

75) Q(next) = D

76) 3

77) Synchronous counters operate faster since all flip-flops trigger

together

78) 8

79) SISO (Serial-In, Serial-Out)

80) PIPO